https://git.qemu.org/?p=qemu.git;a=commitdiff;h=45b1a243b81a7c9ae562
** Changed in: qemu
Status: Fix Committed => Fix Released
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https://bugs.launchpad.net/bugs/1836078
Title:
R
** Changed in: qemu
Status: In Progress => Fix Committed
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Title:
Regressions on arm-linux-gnueabihf target with some GCC tests
Status in
I think the ieee6 test is due to a broken runtime:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78314
** Bug watch added: GCC Bugzilla #78314
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78314
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I confirm this patch fixes the problem I reported.
Thanks!
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Title:
Regressions on arm-linux-gnueabihf target with some GCC tests
Status in QEMU
In the ieee6 test case it is attempting to write OFE, bit [10] which:
This bit is RW only if the implementation supports the trapping of
floating-point exceptions. In an implementation that does not support
floating-point exception trapping, this bit is RAZ/WI.
When this bit is RW, it app
The IEEE6 test comes down to:
commit a15945d98d3a3390c3da344d1b47218e91e49d8b
Author: Peter Maydell
Date: Tue Feb 5 16:52:42 2019 +
target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI
The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for
enabling trapped IEEE
I bisected the failure for all but the IEEE6 test to:
commit 602f6e42cfbfe9278be34e9b91d2ceb695837e02
Author: Peter Maydell
Date: Thu Feb 28 10:55:16 2019 +
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
Instead of gating the A32/T32 FP16 conversion instructi
** Tags added: arm testcase
** Changed in: qemu
Status: New => In Progress
** Changed in: qemu
Assignee: (unassigned) => Alex Bennée (ajbennee)
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