On Mon, 29 Oct 2018, Aleksandar Markovic wrote:
> > > Without TARGET_MIPS64, we can't say we emulate R5900 - we are emulating
> > > some other CPU that never existed.
> > >
> > > Convince me that I am wrong.
> >
> > R5900 O32 is usable.
>
> Absolutely not. This kind of emulation infidelity
> From: Fredrik Noring
> Subject: Re: [PATCH] target/mips: Support Toshiba specific three-operand MADD
> and MADDU
>
> Hi Aleksandar,
>
> > Without TARGET_MIPS64, we can't say we emulate R5900 - we are emulating
> > some other CPU that never existed.
> >
> > Convince me that I am wrong.
>
>
Hi Aleksandar,
> Without TARGET_MIPS64, we can't say we emulate R5900 - we are emulating
> some other CPU that never existed.
>
> Convince me that I am wrong.
R5900 O32 is usable. The R5900 toolchain is not yet ready for N32. Regarding
your proposal to rename TX79_MMI to MMI: what other ISAs do
>
> From: Aleksandar Markovic
> Subject: Re: [PATCH] target/mips: Support Toshiba specific three-operand MADD
> and MADDU
>
> > From: Richard Henderson
> > Sent: Tuesday, October 16, 2018 8:37 PM
> > Subject: Re: [PATCH] target/mips: Support Toshiba specific three-operand
> > MADD and > MADDU
On Sun, 28 Oct 2018, Aleksandar Markovic wrote:
> I truly need your help here. As you can conclude from the discussion,
> R5900 folks (anybody correct me if I am wrong) have some problems using
> any ABI other than O32.
The maximum the R5900 can support is the n32 ABI, owing to 32-bit virtual
> From: Richard Henderson
> Sent: Tuesday, October 16, 2018 8:37 PM
> Subject: Re: [PATCH] target/mips: Support Toshiba specific three-operand MADD
> and MADDU
>
> On 10/16/18 11:19 AM, Fredrik Noring wrote:
> > /* global register indices */
> > static TCGv cpu_gpr[32], cpu_PC;
> > static TCGv
> I'm queueing your MADD and MADDU patch...
You don't queue, you submit.
Thanks,
Aleksandar
From: Fredrik Noring
Sent: Wednesday, October 24, 2018 8:01:15 PM
To: Philippe Mathieu-Daudé
Cc: Maciej W . Rozycki; Richard Henderson; Aleksandar Markovic;
Hi Philippe,
> The three-operand MADD and MADDU are specific to the
> Toshiba TX19/TX39/TX79 cores.
>
> The "32-Bit TX System RISC TX39 Family Architecture manual"
> is available at https://wiki.qemu.org/File:DSAE0022432.pdf
>
> Signed-off-by: Philippe Mathieu-Daudé
I'm queueing your MADD and
> Perhaps a better alternative is to define the MMI registers as 128-bit,
> similar to
>
> static TCGv_u128 mmi_gpr[32];
>
> and then copy cpu_gpr to/from mmi_gpr as needed when running the MMIs?
Fredrik, hi.
I think this is fine. In any case, this could be changed, if we hit any
obstacle
On Tue, 16 Oct 2018, Fredrik Noring wrote:
> > I would not implement r5900 for mips32 in that case,
> > I would implement it only for TARGET_MIPS64.
>
> R5900 Linux implements the O32 ABI, which is why 32-bit QEMU user-mode is
> very useful. Perhaps a better alternative is to define the MMI
On Tue, 16 Oct 2018, Fredrik Noring wrote:
> One option is to create a new array such as
>
> static TCGv_i64 mmi_gpr[32];
>
> that represents the upper 64 bits of each GPR. Then cpu_gpr must be of
> a 64-bit type too, even when QEMU runs in 32-bit user mode. The R5900
> does not implement
Hi Richard,
> > /* global register indices */
> > static TCGv cpu_gpr[32], cpu_PC;
> > static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
> >
> > One option is to create a new array such as
> >
> > static TCGv_i64 mmi_gpr[32];
> >
> > that represents the upper 64 bits of each GPR. Then
On 10/16/18 11:19 AM, Fredrik Noring wrote:
> /* global register indices */
> static TCGv cpu_gpr[32], cpu_PC;
> static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
>
> One option is to create a new array such as
>
> static TCGv_i64 mmi_gpr[32];
>
> that represents the upper 64 bits of each
Hi Aleksandar,
> A peculiar case of DMULTU would be interesting.
Agreed, DMULTU would be good to test as well. (DMULTU isn't part of the
R5900 ISA, though.)
> It would be nice to implement just a single instruction from MMI, let's
> say PAND, and have a test for it.
Most if not all multimedia
> From: Fredrik Noring
> Sent: Monday, October 15, 2018 7:02 PM
> To: Maciej W. Rozycki
> Cc: Philippe Mathieu-Daudé; Richard Henderson; Aleksandar Markovic; Aurelien
> Jarno; > qemu-devel@nongnu.org Developers; Jürgen Urban
> Subject: Re: [PATCH] target/mips: Support Toshiba specific
Hi Maciej, Philippe,
> So results of individual operations are as in the comments with this
> code:
>
> mthi$0 # HI <- 0
> mtlo$0 # LO <- 0
> addiu $2, $0, 1 # $2 <- 1
> lui $3, 0x4000 # $3 <- 0x4000
> maddu
Hi Philippe,
> That's true it is not reachable, it lacks the INSN_R3900 definition,
> used by the R3900 mips_def_t.
>
> I'll stop bothering with this until the code is reachable (my branch posted).
I would be happy if your patch could be merged soon. Adding the following
five lines to it would
On Sun, 14 Oct 2018, Philippe Mathieu-Daudé wrote:
> > > +gen_move_low32(cpu_LO[acc], t2);
> > > +gen_move_high32(cpu_HI[acc], t2);
> > > +if (rd) {
> > > +gen_move_low32(cpu_gpr[rd], t2);
> >
> > As above, are LO, HI and GPR[rd] sign-extended
Hi Fredrik,
On Sun, Oct 14, 2018 at 6:41 PM Fredrik Noring wrote:
>
> Hi Philippe,
>
> > --- a/target/mips/translate.c
> > +++ b/target/mips/translate.c
> > @@ -3843,6 +3843,46 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t
> > opc,
>
> What about documenting MADD and MADDU along with
Hi Philippe,
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -3843,6 +3843,46 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t
> opc,
What about documenting MADD and MADDU along with MULT and MULTU in the
note above?
> +case OPC_MADD:
This case is unreachable,
The three-operand MADD and MADDU are specific to the
Toshiba TX19/TX39/TX79 cores.
The "32-Bit TX System RISC TX39 Family Architecture manual"
is available at https://wiki.qemu.org/File:DSAE0022432.pdf
Signed-off-by: Philippe Mathieu-Daudé
---
Based-on:
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