Hello,
On 09/27/2013 08:25 PM, Richard Henderson wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 28 +++
target-arm/helper-a64.h| 1 +
On Mon, Nov 18, 2013 at 11:15 AM, Claudio Fontana
claudio.font...@linaro.org wrote:
Hello,
On 09/27/2013 08:25 PM, Richard Henderson wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
Hi,
On Mon, 18 Nov 2013, Claudio Fontana wrote:
+case 3:
+tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
+break;
Incorrect rotate for 32bit?
32bit rotates and shifts were fixed in a patch later than the 60er series
Alex posted. See attached. (Generally there are
On 18 November 2013 13:12, Michael Matz m...@suse.de wrote:
Hi,
On Mon, 18 Nov 2013, Claudio Fontana wrote:
+case 3:
+tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
+break;
Incorrect rotate for 32bit?
32bit rotates and shifts were fixed in a patch later than the
On 11/18/2013 02:15 PM, Peter Maydell wrote:
On 18 November 2013 13:12, Michael Matz m...@suse.de wrote:
Hi,
On Mon, 18 Nov 2013, Claudio Fontana wrote:
+case 3:
+tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
+break;
Incorrect rotate for 32bit?
32bit rotates and
Btw, in the first patch:
On 11/18/2013 02:12 PM, Michael Matz wrote:
From df54486da31d6329696effa61096eda5ab85395a Mon Sep 17 00:00:00 2001
From: Michael Matz m...@suse.de
Date: Sun, 24 Mar 2013 02:52:42 +0100
Subject: [PATCH] Fix 32bit rotates.
The 32bit shifts generally weren't careful
On 18 November 2013 13:43, Claudio Fontana claudio.font...@linaro.org wrote:
We are using gen_rotr_i32, but passing tcg_shift, which is a TCGv_i64.
I remember I had compilation failures in the past when I tried something
similar,
so my understanding is that this can work with a certain
Hi,
On Mon, 18 Nov 2013, Peter Maydell wrote:
+case 3:
+tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
+break;
Incorrect rotate for 32bit?
32bit rotates and shifts were fixed in a patch later than the 60er series
Alex posted. See attached. (Generally
On 18 November 2013 13:46, Michael Matz m...@suse.de wrote:
On Mon, 18 Nov 2013, Peter Maydell wrote:
I think we're going to need to look through and fold in those fixes,
otherwise we'll end up reduplicating that work in the course of code
review :-(
Most probably. Authorship will be lost
Hi,
On Mon, 18 Nov 2013, Claudio Fontana wrote:
+tcg_gen_trunc_i64_i32(tmp, cpu_reg(reg));
+ tcg_gen_rotr_i32(tmp, tmp, tcg_shift);
Isn't this problematic?
We are using gen_rotr_i32, but passing tcg_shift, which is a TCGv_i64.
With CONFIG_DEBUG_TCG it'll break, yes.
On 11/18/2013 11:55 PM, Michael Matz wrote:
I think we need to either explicitly convert the tcg_shift to a
TCGv_i32, or we need to use an open coded version of the rotr_i64 that
inserts at (32 - n) instead of (64 - n)
What do you think?
I think converting tcg_shift might eventually
On 27.09.2013, at 11:25, Richard Henderson r...@twiddle.net wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 28 +++
target-arm/helper-a64.h
On 31 October 2013 00:29, Alexander Graf ag...@suse.de wrote:
On 27.09.2013, at 11:25, Richard Henderson r...@twiddle.net wrote:
Why are you not using the same split apart bits as A32?
There is an architecturally defined register that specifies
what pstate looks like and IIRC that includes
On 09/26/2013 05:48 PM, Alexander Graf wrote:
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 28 +++
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 120
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 28 +++
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 120 +
3 files changed, 149
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