Peter Maydell writes:
On 24 July 2014 16:52, Alex Bennée alex.ben...@linaro.org wrote:
+/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance
instructions
+ * Page D4-1736 (DDI0487A.b) For TLB maintenance instructions that
+ * take an address, the maintenance of VA[63:56] is
According to the ARM ARM we weren't correctly flushing the TLB entries
where bits 63:56 didn't match bit 55 of the virtual address. This
exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to
12 for aarch64.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git
On 24 July 2014 16:52, Alex Bennée alex.ben...@linaro.org wrote:
+/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance
instructions
+ * Page D4-1736 (DDI0487A.b) For TLB maintenance instructions that
+ * take an address, the maintenance of VA[63:56] is interpreted as
+ * being
