On 04/10/2018 03:04 AM, Antony Pavlov wrote:
+++ b/include/hw/riscv/sifive_uart.h
+
+typedef struct SiFiveUARTState {
+/*< private >*/
+SysBusDevice parent_obj;
>>>
>>>
>>> You use SysBusDevive in this header file but there is no 'include
>>> "hw/sysbus.h"' in
On Tue, Apr 10, 2018 at 8:04 PM, Antony Pavlov
wrote:
> On Tue, 10 Apr 2018 08:17:32 +0200
> Thomas Huth wrote:
>
> > On 10.04.2018 05:21, Antony Pavlov wrote:
> > > On Sat, 3 Mar 2018 02:51:47 +1300
> > > Michael Clark wrote:
> > >
On Tue, 10 Apr 2018 08:17:32 +0200
Thomas Huth wrote:
> On 10.04.2018 05:21, Antony Pavlov wrote:
> > On Sat, 3 Mar 2018 02:51:47 +1300
> > Michael Clark wrote:
> >
> >> QEMU model of the UART on the SiFive E300 and U500 series SOCs.
> >> BBL supports the
On 10.04.2018 05:21, Antony Pavlov wrote:
> On Sat, 3 Mar 2018 02:51:47 +1300
> Michael Clark wrote:
>
>> QEMU model of the UART on the SiFive E300 and U500 series SOCs.
>> BBL supports the SiFive UART for early console access via the SBI
>> (Supervisor Binary Interface) and
On Sat, 3 Mar 2018 02:51:47 +1300
Michael Clark wrote:
> QEMU model of the UART on the SiFive E300 and U500 series SOCs.
> BBL supports the SiFive UART for early console access via the SBI
> (Supervisor Binary Interface) and the linux kernel SBI console.
>
> The SiFive UART
On 03/16/2018 07:36 PM, Michael Clark wrote:
> On Fri, Mar 16, 2018 at 11:30 AM, Michael Clark wrote:
>
>>
>>
>> On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann <
>> kbast...@mail.uni-paderborn.de> wrote:
>>
>>> Hi Mark,
>>>
>>> On 03/10/2018 10:40 AM, Mark Cave-Ayland
On Fri, Mar 16, 2018 at 11:30 AM, Michael Clark wrote:
>
>
> On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann <
> kbast...@mail.uni-paderborn.de> wrote:
>
>> Hi Mark,
>>
>> On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote:
>> > On 10/03/18 03:02, Michael Clark wrote:
>> >
>> >>
On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann <
kbast...@mail.uni-paderborn.de> wrote:
> Hi Mark,
>
> On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote:
> > On 10/03/18 03:02, Michael Clark wrote:
> >
> >> On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé <
> f4...@amsat.org>
> >> wrote:
Hi Mark,
On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote:
> On 10/03/18 03:02, Michael Clark wrote:
>
>> On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé
>> wrote:
>>
[...]
> Another general note: for each of the main QEMU platforms supported
> there is a home page on the
On 10/03/18 03:02, Michael Clark wrote:
On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé
wrote:
On 03/02/2018 02:51 PM, Michael Clark wrote:
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the
On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé
wrote:
> On 03/02/2018 02:51 PM, Michael Clark wrote:
> > QEMU model of the UART on the SiFive E300 and U500 series SOCs.
> > BBL supports the SiFive UART for early console access via the SBI
> > (Supervisor Binary
On 03/02/2018 02:51 PM, Michael Clark wrote:
> QEMU model of the UART on the SiFive E300 and U500 series SOCs.
> BBL supports the SiFive UART for early console access via the SBI
> (Supervisor Binary Interface) and the linux kernel SBI console.
>
> The SiFive UART implements the pre qom legacy
QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.
The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in
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