On 05/23/18 09:32, Laszlo Ersek wrote:
> On 05/23/18 01:40, Michael S. Tsirkin wrote:
>> On Wed, May 23, 2018 at 12:42:09AM +0200, Laszlo Ersek wrote:
>>> Hold on,
>>>
>>> On 05/22/18 21:51, Laszlo Ersek wrote:
>>>
It had taken years until the edk2 core gained a universal
2018-05-24 1:33 GMT+08:00 Marcel Apfelbaum :
>
>> * IOMMUs cannot span domains either, so bringing new domains introduces
>> the need
>> to add a VT-d DHRD or vIOMMU per PCIe domain
>
>
> Not really, you may have PCI domains not associated to an vIOMMU. As a first
>
> > The original purpose was just to support multiple segments in Intel
> > Q35 archtecure for PCIe topology, which makes bus number a less scarce
> > resource. The patches are very primitive and many things are left for
> > firmware to finish(the initial plan was to implement it in SeaBIOS),
> >
On 05/23/2018 02:11 PM, Zihan Yang wrote:
Hi all,
Thanks for all your comments and suggestions, I wasn't expecting so
many professional
reviewers. Some of the things you mentioned are beyond my knowledge
right now.
Please correct me if I'm wrong below.
The original purpose was just to
On 05/23/18 19:11, Marcel Apfelbaum wrote:
> On 05/23/2018 10:32 AM, Laszlo Ersek wrote:
>> On 05/23/18 01:40, Michael S. Tsirkin wrote:
>>> On Wed, May 23, 2018 at 12:42:09AM +0200, Laszlo Ersek wrote:
If we figure out a placement strategy or an easy to consume
representation of these
On 05/23/2018 03:28 PM, Laszlo Ersek wrote:
On 05/23/18 13:11, Zihan Yang wrote:
Hi all,
The original purpose was just to support multiple segments in Intel
Q35 archtecure for PCIe topology, which makes bus number a less scarce
resource. The patches are very primitive and many things are left
On 05/23/2018 10:32 AM, Laszlo Ersek wrote:
On 05/23/18 01:40, Michael S. Tsirkin wrote:
On Wed, May 23, 2018 at 12:42:09AM +0200, Laszlo Ersek wrote:
Hold on,
On 05/22/18 21:51, Laszlo Ersek wrote:
It had taken years until the edk2 core gained a universal
PciHostBridgeDxe driver with a
Hi Alex,
On 05/23/2018 12:17 AM, Alex Williamson wrote:
On Tue, 22 May 2018 21:51:47 +0200
Laszlo Ersek wrote:
On 05/22/18 21:01, Marcel Apfelbaum wrote:
Hi Laszlo,
On 05/22/2018 12:52 PM, Laszlo Ersek wrote:
On 05/21/18 13:53, Marcel Apfelbaum wrote:
On 05/20/2018
On 05/23/2018 05:25 PM, Michael S. Tsirkin wrote:
On Tue, May 22, 2018 at 10:28:56PM -0600, Alex Williamson wrote:
On Wed, 23 May 2018 02:38:52 +0300
"Michael S. Tsirkin" wrote:
On Tue, May 22, 2018 at 03:47:41PM -0600, Alex Williamson wrote:
On Wed, 23 May 2018 00:44:22
On Wed, 23 May 2018 17:25:32 +0300
"Michael S. Tsirkin" wrote:
> On Tue, May 22, 2018 at 10:28:56PM -0600, Alex Williamson wrote:
> > On Wed, 23 May 2018 02:38:52 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > On Tue, May 22, 2018 at 03:47:41PM -0600, Alex
On Wed, May 23, 2018 at 08:57:51AM -0600, Alex Williamson wrote:
> On Wed, 23 May 2018 17:25:32 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Tue, May 22, 2018 at 10:28:56PM -0600, Alex Williamson wrote:
> > > On Wed, 23 May 2018 02:38:52 +0300
> > > "Michael S. Tsirkin"
On Tue, May 22, 2018 at 10:28:56PM -0600, Alex Williamson wrote:
> On Wed, 23 May 2018 02:38:52 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Tue, May 22, 2018 at 03:47:41PM -0600, Alex Williamson wrote:
> > > On Wed, 23 May 2018 00:44:22 +0300
> > > "Michael S. Tsirkin"
On 05/23/18 13:11, Zihan Yang wrote:
> Hi all,
> The original purpose was just to support multiple segments in Intel
> Q35 archtecure for PCIe topology, which makes bus number a less scarce
> resource. The patches are very primitive and many things are left for
> firmware to finish(the initial
Hi all,
Thanks for all your comments and suggestions, I wasn't expecting so many
professional
reviewers. Some of the things you mentioned are beyond my knowledge right
now.
Please correct me if I'm wrong below.
The original purpose was just to support multiple segments in Intel Q35
archtecure
On 05/23/18 01:40, Michael S. Tsirkin wrote:
> On Wed, May 23, 2018 at 12:42:09AM +0200, Laszlo Ersek wrote:
>> Hold on,
>>
>> On 05/22/18 21:51, Laszlo Ersek wrote:
>>
>>> It had taken years until the edk2 core gained a universal
>>> PciHostBridgeDxe driver with a well-defined platform
On Wed, 23 May 2018 02:38:52 +0300
"Michael S. Tsirkin" wrote:
> On Tue, May 22, 2018 at 03:47:41PM -0600, Alex Williamson wrote:
> > On Wed, 23 May 2018 00:44:22 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > On Tue, May 22, 2018 at 03:36:59PM -0600, Alex
On Wed, May 23, 2018 at 12:42:09AM +0200, Laszlo Ersek wrote:
> Hold on,
>
> On 05/22/18 21:51, Laszlo Ersek wrote:
>
> > It had taken years until the edk2 core gained a universal
> > PciHostBridgeDxe driver with a well-defined platform customization
> > interface, and that interface doesn't
On Tue, May 22, 2018 at 03:47:41PM -0600, Alex Williamson wrote:
> On Wed, 23 May 2018 00:44:22 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Tue, May 22, 2018 at 03:36:59PM -0600, Alex Williamson wrote:
> > > On Tue, 22 May 2018 23:58:30 +0300
> > > "Michael S. Tsirkin"
Hold on,
On 05/22/18 21:51, Laszlo Ersek wrote:
> It had taken years until the edk2 core gained a universal
> PciHostBridgeDxe driver with a well-defined platform customization
> interface, and that interface doesn't support multiple domains /
> segments.
after doing a bit more research: I was
On 05/22/18 23:47, Alex Williamson wrote:
> On Wed, 23 May 2018 00:44:22 +0300
> "Michael S. Tsirkin" wrote:
>
>> On Tue, May 22, 2018 at 03:36:59PM -0600, Alex Williamson wrote:
>>> On Tue, 22 May 2018 23:58:30 +0300
>>> "Michael S. Tsirkin" wrote:
On 05/22/18 23:22, Michael S. Tsirkin wrote:
> On Tue, May 22, 2018 at 03:17:32PM -0600, Alex Williamson wrote:
>> On Tue, 22 May 2018 21:51:47 +0200
>> Laszlo Ersek wrote:
>>> But 64-bit is ill-partitioned and/or crowded too: first you have the
>>> cold-plugged >4GB DRAM
On 05/22/18 23:17, Alex Williamson wrote:
> On Tue, 22 May 2018 21:51:47 +0200
> Laszlo Ersek wrote:
Thanks Michael and Alex for the education on ARI.
I'd just like to comment on one sub-topic:
>> There are signs that the edk2 core supports ARI if the underlying
>> platform
On Wed, 23 May 2018 00:44:22 +0300
"Michael S. Tsirkin" wrote:
> On Tue, May 22, 2018 at 03:36:59PM -0600, Alex Williamson wrote:
> > On Tue, 22 May 2018 23:58:30 +0300
> > "Michael S. Tsirkin" wrote:
> > >
> > > It's not hard to think of a use-case where
On Tue, May 22, 2018 at 03:36:59PM -0600, Alex Williamson wrote:
> On Tue, 22 May 2018 23:58:30 +0300
> "Michael S. Tsirkin" wrote:
> >
> > It's not hard to think of a use-case where >256 devices
> > are helpful, for example a nested virt scenario where
> > each device is passed
On Tue, 22 May 2018 23:58:30 +0300
"Michael S. Tsirkin" wrote:
>
> It's not hard to think of a use-case where >256 devices
> are helpful, for example a nested virt scenario where
> each device is passed on to a different nested guest.
>
> But I think the main feature this is
On Tue, May 22, 2018 at 03:17:32PM -0600, Alex Williamson wrote:
> On Tue, 22 May 2018 21:51:47 +0200
> Laszlo Ersek wrote:
>
> > On 05/22/18 21:01, Marcel Apfelbaum wrote:
> > > Hi Laszlo,
> > >
> > > On 05/22/2018 12:52 PM, Laszlo Ersek wrote:
> > >> On 05/21/18 13:53,
On Tue, 22 May 2018 21:51:47 +0200
Laszlo Ersek wrote:
> On 05/22/18 21:01, Marcel Apfelbaum wrote:
> > Hi Laszlo,
> >
> > On 05/22/2018 12:52 PM, Laszlo Ersek wrote:
> >> On 05/21/18 13:53, Marcel Apfelbaum wrote:
> >>>
> >>> On 05/20/2018 10:28 AM, Zihan Yang wrote:
>
On Tue, May 22, 2018 at 09:51:47PM +0200, Laszlo Ersek wrote:
> On 05/22/18 21:01, Marcel Apfelbaum wrote:
> > Hi Laszlo,
> >
> > On 05/22/2018 12:52 PM, Laszlo Ersek wrote:
> >> On 05/21/18 13:53, Marcel Apfelbaum wrote:
> >>>
> >>> On 05/20/2018 10:28 AM, Zihan Yang wrote:
> Currently only
On 05/22/18 21:01, Marcel Apfelbaum wrote:
> Hi Laszlo,
>
> On 05/22/2018 12:52 PM, Laszlo Ersek wrote:
>> On 05/21/18 13:53, Marcel Apfelbaum wrote:
>>>
>>> On 05/20/2018 10:28 AM, Zihan Yang wrote:
Currently only q35 host bridge us allocated space in MCFG table. To
put pxb host
Hi Laszlo,
On 05/22/2018 12:52 PM, Laszlo Ersek wrote:
On 05/21/18 13:53, Marcel Apfelbaum wrote:
On 05/20/2018 10:28 AM, Zihan Yang wrote:
Currently only q35 host bridge us allocated space in MCFG table. To
put pxb host
into sepratate pci domain, each of them should have its own
On 05/22/2018 09:03 AM, Zihan Yang wrote:
> An interesting point is if we want to limit the MMFCG size for PXBs,
as we may not be
> interested to use all the buses in a specific domain.
OK, perhaps providing an option for the user to specify the desired
bus numbers?
Right, specifying
On 05/21/18 13:53, Marcel Apfelbaum wrote:
>
>
> On 05/20/2018 10:28 AM, Zihan Yang wrote:
>> Currently only q35 host bridge us allocated space in MCFG table. To
>> put pxb host
>> into sepratate pci domain, each of them should have its own
>> configuration space
>> int MCFG table
>>
>>
> An interesting point is if we want to limit the MMFCG size for PXBs, as
we may not be
> interested to use all the buses in a specific domain.
OK, perhaps providing an option for the user to specify the desired bus
numbers?
> For each bus we require some address space that remains unused.
Does
On 05/20/2018 10:28 AM, Zihan Yang wrote:
Currently only q35 host bridge us allocated space in MCFG table. To put pxb host
into sepratate pci domain, each of them should have its own configuration space
int MCFG table
Signed-off-by: Zihan Yang
---
Currently only q35 host bridge us allocated space in MCFG table. To put pxb host
into sepratate pci domain, each of them should have its own configuration space
int MCFG table
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 83
35 matches
Mail list logo