Implemented cadence Triple Timer Counter (TCC)
It looks like you're implementing a periodic timer as sequence of chained
oneshot timers. This is a bad idea. In qemu interrupt latency may be
high,
so you're likely to suffer from significant time skew.
Ok, I could implemented the
2012/2/8 Paul Brook p...@codesourcery.com
Implemented cadence Triple Timer Counter (TCC)
It looks like you're implementing a periodic timer as sequence of
chained
oneshot timers. This is a bad idea. In qemu interrupt latency may be
high,
so you're likely to suffer from
- When are interrupts raised. You mention a user specified match value.
Do we also get an interrupt on wraparound?
Yes, an interrupts occur on wrap around of the 16 bit timer value. There
are three match registers which correspond to three more
(separately maskable) interrupts which
2012/2/8 Paul Brook p...@codesourcery.com
- When are interrupts raised. You mention a user specified match
value.
Do we also get an interrupt on wraparound?
Yes, an interrupts occur on wrap around of the 16 bit timer value. There
are three match registers which correspond to three
Implemented cadence Triple Timer Counter (TCC)
It looks like you're implementing a periodic timer as sequence of chained
oneshot timers. This is a bad idea. In qemu interrupt latency may be high,
so you're likely to suffer from significant time skew.
Paul
2012/2/7 Paul Brook p...@codesourcery.com
Implemented cadence Triple Timer Counter (TCC)
It looks like you're implementing a periodic timer as sequence of chained
oneshot timers. This is a bad idea. In qemu interrupt latency may be
high,
so you're likely to suffer from significant time
Implemented cadence Triple Timer Counter (TCC)
Signed-off-by: Peter A. G. Crosthwaite peter.crosthwa...@petalogix.com
Signed-off-by: John Linn john.l...@xilinx.com
---
changes from v1
refactored event driven code
marked vmsd as unmigratable
Makefile.target |1 +
hw/cadence_ttc.c | 399
