On Sat, Mar 10, 2018 at 9:11 AM, Michael Clark wrote:
>
>
> On Sat, Mar 10, 2018 at 5:49 AM, Peter Maydell
> wrote:
>
>> On 9 March 2018 at 14:28, Peter Maydell wrote:
>> > NB: there was a test failure on OpenBSD host:
>> >
On Sat, Mar 10, 2018 at 5:49 AM, Peter Maydell
wrote:
> On 9 March 2018 at 14:28, Peter Maydell wrote:
> > NB: there was a test failure on OpenBSD host:
> >
> > TEST: tests/qom-test... (pid=64016)
> > /riscv32/qom/spike_v1.9.1:
On 9 March 2018 at 14:28, Peter Maydell wrote:
> NB: there was a test failure on OpenBSD host:
>
> TEST: tests/qom-test... (pid=64016)
> /riscv32/qom/spike_v1.9.1: **
> ERROR:/home/qemu/tests/qom-test.c:64:test_properties:
On 9 March 2018 at 15:15, Alex Bennée wrote:
>
> Michael Clark writes:
>
>
>>
>> BTW - I've integrated the following 3 branches into the riscv tree:
>>
>> - https://github.com/riscv/riscv-qemu/tree/softfloat-snan-abort-fix
>> -
Michael Clark writes:
>
> BTW - I've integrated the following 3 branches into the riscv tree:
>
> - https://github.com/riscv/riscv-qemu/tree/softfloat-snan-abort-fix
> - https://github.com/riscv/riscv-qemu/tree/riscv-qemu-upstream-v8.2
> -
On Sat, Mar 10, 2018 at 3:28 AM, Peter Maydell
wrote:
> On 8 March 2018 at 19:53, Michael Clark wrote:
> > I re-iterate Palmer's apology.
> >
> > I shouldn't be polling git.qemu.org/qemu.git and answering emails near
> to
> > 3am in the morning after 4
On 8 March 2018 at 19:53, Michael Clark wrote:
> I re-iterate Palmer's apology.
>
> I shouldn't be polling git.qemu.org/qemu.git and answering emails near to
> 3am in the morning after 4 months of working on trying to get the RISC-V
> port in shape to go upstream.
>
> It appears
On Fri, Mar 9, 2018 at 8:29 AM, Palmer Dabbelt wrote:
> On Thu, 08 Mar 2018 03:41:33 PST (-0800), Michael Clark wrote:
>
>> On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark wrote:
>>
>>> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark wrote:
>>>
On Thu, 08 Mar 2018 03:41:33 PST (-0800), Michael Clark wrote:
On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark wrote:
On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark wrote:
On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell
wrote:
On 6
On Tue, Mar 6, 2018 at 8:00 AM, Emilio G. Cota wrote:
> On Sat, Mar 03, 2018 at 02:26:12 +1300, Michael Clark wrote:
> > It was qemu-2.7.50 (late 2016). The benchmarks were generated mid last
> year.
> >
> > I can run the benchmarks again... Has it doubled in speed?
>
> It
On Sat, Mar 03, 2018 at 02:26:12 +1300, Michael Clark wrote:
> It was qemu-2.7.50 (late 2016). The benchmarks were generated mid last year.
>
> I can run the benchmarks again... Has it doubled in speed?
It depends on the benchmarks. Small-ish benchmarks such as rv8-bench
show about a 1.5x
On Thu, Mar 1, 2018 at 9:40 AM, Michael Clark wrote:
>
>
> On Thu, Mar 1, 2018 at 12:53 AM, Peter Maydell
> wrote:
>
>> On 28 February 2018 at 00:09, Michael Clark wrote:
>> > I've just talked to SiFive about this. They have agreed
On Thu, Mar 1, 2018 at 11:26 AM, Emilio G. Cota wrote:
> On Wed, Feb 28, 2018 at 13:09:11 +1300, Michael Clark wrote:
> > BTW somewhat coincidentally, the binary translator I wrote; RV8, which is
> > practicaly twice as fast as QEMU only supports privileged ISA v1.9.1 and
> I
> >
On Wed, Feb 28, 2018 at 13:09:11 +1300, Michael Clark wrote:
> BTW somewhat coincidentally, the binary translator I wrote; RV8, which is
> practicaly twice as fast as QEMU only supports privileged ISA v1.9.1 and I
> personally want to keep binary compatiblity with it.
(snip)
> - https://rv8.io/
>
On Thu, Mar 1, 2018 at 12:53 AM, Peter Maydell
wrote:
> On 28 February 2018 at 00:09, Michael Clark wrote:
> > I've just talked to SiFive about this. They have agreed that we can
> remove
> > the sifive_e300 and sifive_u500 boards from the patch series
On 28 February 2018 at 11:53, Peter Maydell wrote:
> With my 'upstream dev' hat on, I tend to be suspicious of this
> line of argument, because in a lot of cases what tends to happen
> is that the code for some new target or device goes in-tree, and
> then the people who
On 28 February 2018 at 00:09, Michael Clark wrote:
> I've just talked to SiFive about this. They have agreed that we can remove
> the sifive_e300 and sifive_u500 boards from the patch series that we are
> going to submit upstream again later this week or early next week. These
>
On Wed, 28 Feb 2018 13:41:25 +1300
Michael Clark wrote:
> On Wed, Feb 28, 2018 at 5:00 AM, Igor Mammedov wrote:
>
> > On Tue, 27 Feb 2018 14:01:05 +
> > Peter Maydell wrote:
> >
> > > On 27 February 2018 at 00:15, Michael
On Wed, Feb 28, 2018 at 5:00 AM, Igor Mammedov wrote:
> On Tue, 27 Feb 2018 14:01:05 +
> Peter Maydell wrote:
>
> > On 27 February 2018 at 00:15, Michael Clark wrote:
> > > -BEGIN PGP SIGNED MESSAGE-
> > > Hash: SHA1
>
On Wed, Feb 28, 2018 at 6:50 AM, Peter Maydell
wrote:
> On 27 February 2018 at 15:50, Stef O'Rear wrote:
> > On Tue, Feb 27, 2018 at 6:01 AM, Peter Maydell
> wrote:
> >> On 27 February 2018 at 00:15, Michael Clark
On Wed, Feb 28, 2018 at 4:50 AM, Stef O'Rear wrote:
> On Tue, Feb 27, 2018 at 6:01 AM, Peter Maydell
> wrote:
> > On 27 February 2018 at 00:15, Michael Clark wrote:
> >> -BEGIN PGP SIGNED MESSAGE-
> >> Hash: SHA1
> >>
> >>
On 27 February 2018 at 15:50, Stef O'Rear wrote:
> On Tue, Feb 27, 2018 at 6:01 AM, Peter Maydell
> wrote:
>> On 27 February 2018 at 00:15, Michael Clark wrote:
>>> The spike_v1.9
>>> machine has been renamed to spike_v1.9.1 to
On Tue, Feb 27, 2018 at 6:01 AM, Peter Maydell wrote:
> On 27 February 2018 at 00:15, Michael Clark wrote:
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA1
>>
>> The following changes since commit 0a773d55ac76c5aa89ed9187a3bc5af8c5c2a6d0:
>>
>>
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