[Qemu-devel] Support for Intel Pro network cards
Hi, I'm trying to get Juniper software running on QEMU. I've managed to get it installed and operational however I can't setup a network interface as the software is very specific about the type of network card it will accept. In vmware you can do the following to have it emulate an intel adaptor ethernet0.virtualDev = e1000, which shows up as an em interface under freeBSD. Is there any support for this with QEMU? Regards Jeff This communication, including any attachments, is confidential. If you are not the intended recipient, you should not read it - please contact me immediately, destroy it, and do not copy or use any part of this communication or disclose anything about it. Thank you. Please note that this communication does not designate an information system for the purposes of the Electronic Transactions Act 2002.
Re: [Qemu-devel] [PATCH] Fix TLS support on x86
Hi,
these are the updated patches for TLS support:
qemu-cvs-futex.patch
This patches futex support into qemu-user. It is basically done by David
Woodhouse and I implemented FUTEX_WAKE_OP because actually one
application did not work without (I don't really remember which one
though). If FUTEX_WAKE_OP gets triggered qemu throws a warning though so
if anyone experiences problems with it and it works without we should
disable it then.
qemu-cvs-sched_getaffinity.patch
Flash9 needs sys_get_getaffinity to work properly. As far as I can tell
there should be no need for endianness-conversion, because the
information is written bit-wise.
qemu-cvs-tls.patch
implements set_thread_area for x86 and modifies the do_clone function,
so TLS is evaluated. This is 90% done by David Woodhouse, I only changed
it so it works for me (TID setters, proper segment register setters,
fork() fix, made clone() work).
Alex
Index: qemu/linux-user/syscall.c
===
--- qemu.orig/linux-user/syscall.c
+++ qemu/linux-user/syscall.c
@@ -17,6 +17,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+
+#define __user
#include stdlib.h
#include stdio.h
#include stdarg.h
@@ -60,6 +62,7 @@
#define tchars host_tchars /* same as target */
#define ltchars host_ltchars /* same as target */
+#include linux/futex.h
#include linux/termios.h
#include linux/unistd.h
#include linux/utsname.h
@@ -2554,6 +2557,91 @@ static inline void host_to_target_timesp
unlock_user_struct(target_ts, target_addr, 1);
}
+#ifdef BSWAP_NEEDED
+static int futex_op(int oldval, int op, int oparg)
+{
+ int retval = oparg;
+ switch(op) {
+ case FUTEX_OP_SET: break;
+ case FUTEX_OP_ADD: retval += oparg; break;
+ case FUTEX_OP_OR: retval |= oparg; break;
+ case FUTEX_OP_ANDN: retval = oparg; break;
+ case FUTEX_OP_XOR: retval ^= oparg; break;
+ }
+ return retval;
+}
+
+static int futex_cmp(int oldval, int cmp, int cmparg)
+{
+ switch(cmp) {
+ case FUTEX_OP_CMP_EQ: return oldval == cmparg;
+ case FUTEX_OP_CMP_NE: return oldval != cmparg;
+ case FUTEX_OP_CMP_LT: return oldval cmparg;
+ case FUTEX_OP_CMP_LE: return oldval = cmparg;
+ case FUTEX_OP_CMP_GT: return oldval cmparg;
+ case FUTEX_OP_CMP_GE: return oldval = cmparg;
+ }
+ return -1;
+}
+#endif
+
+static long do_futex(target_ulong uaddr, int op, uint32_t val,
+target_ulong utime, target_ulong uaddr2,
+uint32_t val3)
+{
+ struct timespec host_utime;
+ unsigned long val2 = utime;
+ long retval;
+
+ if (utime (op == FUTEX_WAIT || op == FUTEX_LOCK_PI)) {
+ target_to_host_timespec(host_utime, utime);
+ val2 = (unsigned long)host_utime;
+ }
+
+#ifdef BSWAP_NEEDED
+ switch(op) {
+ case FUTEX_CMP_REQUEUE:
+ val3 = tswap32(val3);
+ case FUTEX_REQUEUE:
+ val2 = tswap32(val2);
+ case FUTEX_WAIT:
+ case FUTEX_WAKE:
+ case FUTEX_WAKE_OP:
+ val = tswap32(val);
+ case FUTEX_LOCK_PI: /* This one's icky, but comes out OK */
+ case FUTEX_UNLOCK_PI:
+ break;
+ default:
+ gemu_log(qemu: Unsupported futex op %d\n, op);
+ return -ENOSYS;
+ }
+ if (op == FUTEX_WAKE_OP) {
+ /* Need to munge the secondary operation (val3) */
+ gemu_log(qemu: Tricky FUTEX_WAKE_OP - trying to emulate it\n);
+ val3 = tswap32(val3);
+ int op2 = (val3 28) 0xf;
+ int cmp = (val3 24) 0xf;
+ int oparg = (val3 12) 0xfff;
+ int cmparg = val3 0xfff;
+ int shift = val3 (FUTEX_OP_OPARG_SHIFT 28);
+ int oldval = tget32(uaddr2);
+ if (shift)
+ oparg = 1 oparg;
+
+ tput32(uaddr2,futex_op(oldval, op2, oparg));
+ retval = syscall(__NR_futex, g2h(uaddr), FUTEX_WAKE, val, 0, 0, 0);
+ if(futex_cmp(oldval, cmp, cmparg)) {
+ retval = syscall(__NR_futex, g2h(uaddr2), FUTEX_WAKE, val2, 0, 0, 0);
+ }
+ } else {
+ retval = syscall(__NR_futex, g2h(uaddr), op, val, val2, g2h(uaddr2), val3);
+ }
+#else
+ retval = syscall(__NR_futex, g2h(uaddr), op, val, val2, g2h(uaddr2), val3);
+#endif
+ return retval;
+}
+
long do_syscall(void *cpu_env, int num, long arg1, long arg2, long arg3,
long arg4, long arg5, long arg6)
{
@@ -4713,6 +4801,11 @@ long do_syscall(void *cpu_env, int num,
}
#endif
+#ifdef TARGET_NR_futex
+case TARGET_NR_futex:
+ret = get_errno(do_futex(arg1, arg2, arg3, arg4, arg5, arg6));
+break;
+#endif
#if defined(TARGET_NR_set_tid_address) defined(__NR_set_tid_address)
case TARGET_NR_set_tid_address:
ret
Re: [Qemu-devel] [PATCH] ARM (Thumb) read from R15
On Saturday 30 June 2007 04:19, Paul Brook wrote: QEMU does not set the Thumb bit when reading from R15 in Thumb mode. Neither does real hardware. You are, unsurprisingly, right. The problem seems to be a different one. Quoting the ARM on pop pc: In ARM architecture 5 and above, bit[0] of the loaded value determines whether execution continues after this branch in ARM state or in Thumb state[...] In T variants of architecture version 4, bit[0] of the loaded value is ignored and execution continues in Thumb state[...] My code is supposed to run on a 4T. I guess I'll have to implement an ARM_FEATURE_THUMB1. CU Uli -- SUSE LINUX Products GmbH, GF: Markus Rex, HRB 16746 (AG Nürnberg)
[Qemu-devel] [PATCH] Ignore PROT_GROWSDOWN and PROT_GROWSUP
In an mprotect call the flags PROT_GROWSDOWN and PROT_GROWSUP can be
defined. Currently qemu returns an EINVAL as soon as one of these is
found, which breaks some programs (especially mplayer).
As far as I can tell it is safe to ignore these flags and just go on as
if nothing happened. To be on the safe side a warning message to the
user is thrown though.
Is there anything wrong with ignoring these? Should they be implemented
properly? Comments appreciated.
Alex
Index: qemu/linux-user/mmap.c
===
--- qemu.orig/linux-user/mmap.c
+++ qemu/linux-user/mmap.c
@@ -48,8 +48,10 @@ int target_mprotect(target_ulong start,
end = start + len;
if (end start)
return -EINVAL;
-if (prot ~(PROT_READ | PROT_WRITE | PROT_EXEC))
-return -EINVAL;
+if (prot ~(PROT_READ | PROT_WRITE | PROT_EXEC)) {
+ gemu_log(WARNING: dirty hack in mprotect: setting prot (%#x - %#x)\n, prot, prot (PROT_READ | PROT_WRITE | PROT_EXEC));
+prot = (PROT_READ | PROT_WRITE | PROT_EXEC);
+}
if (len == 0)
return 0;
Re: [Qemu-devel] [PATCH] ARM (Thumb) read from R15
On Monday 02 July 2007, Ulrich Hecht wrote: On Saturday 30 June 2007 04:19, Paul Brook wrote: QEMU does not set the Thumb bit when reading from R15 in Thumb mode. Neither does real hardware. You are, unsurprisingly, right. The problem seems to be a different one. Quoting the ARM on pop pc: In ARM architecture 5 and above, bit[0] of the loaded value determines whether execution continues after this branch in ARM state or in Thumb state[...] In T variants of architecture version 4, bit[0] of the loaded value is ignored and execution continues in Thumb state[...] My code is supposed to run on a 4T. I guess I'll have to implement an ARM_FEATURE_THUMB1. As you have found out, qemu doesn't currently emulate v4t. There are a couple of other instructions that should be disabled (blx) if you do this. Paul
[Qemu-devel] [PATCH] ARM7TDMI emulation
Hi!
This patch adds ARM7TDMI emulation with Thumb v1 (no BLX, no BKPT, ignore
bit 0 on POP PC) and without CP15.
CU
Uli
--
SUSE LINUX Products GmbH, GF: Markus Rex, HRB 16746 (AG Nürnberg)
Index: cpu.h
===
RCS file: /sources/qemu/qemu/target-arm/cpu.h,v
retrieving revision 1.28
diff -u -r1.28 cpu.h
--- cpu.h 24 Jun 2007 12:09:48 - 1.28
+++ cpu.h 2 Jul 2007 13:16:12 -
@@ -247,7 +247,9 @@
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
-ARM_FEATURE_MPU /* Only has Memory Protection Unit, not full MMU. */
+ARM_FEATURE_MPU,/* Only has Memory Protection Unit, not full MMU. */
+ARM_FEATURE_THUMB1, /* Thumb v1 (ARM v4 with Thumb) */
+ARM_FEATURE_NO_CP15 /* ARM7TDMI, ARM7TDMI-S, ARM7EJ-S, and ARM9TDMI cores do not have a CP15 */
};
static inline int arm_feature(CPUARMState *env, int feature)
@@ -262,6 +264,7 @@
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
void *opaque);
+#define ARM_CPUID_ARM7TDMI 0x41807000 /* guess; no CP15 on ARM7TDMI */
#define ARM_CPUID_ARM1026 0x4106a262
#define ARM_CPUID_ARM9260x41069265
#define ARM_CPUID_ARM9460x41059461
Index: helper.c
===
RCS file: /sources/qemu/qemu/target-arm/helper.c,v
retrieving revision 1.17
diff -u -r1.17 helper.c
--- helper.c 24 Jun 2007 12:09:48 - 1.17
+++ helper.c 2 Jul 2007 13:16:12 -
@@ -14,6 +14,11 @@
{
env-cp15.c0_cpuid = id;
switch (id) {
+case ARM_CPUID_ARM7TDMI:
+set_feature(env, ARM_FEATURE_THUMB1);
+set_feature(env, ARM_FEATURE_NO_CP15);
+/* no CP15 here */
+break;
case ARM_CPUID_ARM926:
set_feature(env, ARM_FEATURE_VFP);
env-vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
@@ -98,6 +103,7 @@
};
static const struct arm_cpu_t arm_cpu_names[] = {
+{ ARM_CPUID_ARM7TDMI, arm7tdmi},
{ ARM_CPUID_ARM926, arm926},
{ ARM_CPUID_ARM946, arm946},
{ ARM_CPUID_ARM1026, arm1026},
Index: translate.c
===
RCS file: /sources/qemu/qemu/target-arm/translate.c,v
retrieving revision 1.53
diff -u -r1.53 translate.c
--- translate.c 11 Jun 2007 18:59:35 - 1.53
+++ translate.c 2 Jul 2007 13:16:13 -
@@ -1589,7 +1589,7 @@
uint32_t rd;
/* ??? Some cp15 registers are accessible from userspace. */
-if (IS_USER(s)) {
+if (IS_USER(s) || arm_feature(env, ARM_FEATURE_NO_CP15)) {
return 1;
}
if ((insn 0x0fff0fff) == 0x0e070f90
@@ -2958,7 +2958,7 @@
}
}
-static void disas_thumb_insn(DisasContext *s)
+static void disas_thumb_insn(CPUState *env, DisasContext *s)
{
uint32_t val, insn, op, rm, rn, rd, shift, cond;
int32_t offset;
@@ -3058,6 +3058,7 @@
break;
case 3:/* branch [and link] exchange thumb register */
if (insn (1 7)) {
+if(arm_feature(env, ARM_FEATURE_THUMB1)) goto undef;
val = (uint32_t)s-pc | 1;
gen_op_movl_T1_im(val);
gen_movl_reg_T1(s, 14);
@@ -3367,11 +3368,16 @@
/* write back the new stack pointer */
gen_movl_reg_T1(s, 13);
/* set the new PC value */
-if ((insn 0x0900) == 0x0900)
-gen_bx(s);
+if ((insn 0x0900) == 0x0900) {
+if(arm_feature(env, ARM_FEATURE_THUMB1))
+ gen_movl_reg_T0(s, 15);
+else
+ gen_bx(s);
+}
break;
case 0xe: /* bkpt */
+if(arm_feature(env, ARM_FEATURE_THUMB1)) goto undef;
gen_op_movl_T0_im((long)s-pc - 2);
gen_op_movl_reg_TN[0][15]();
gen_op_bkpt();
@@ -3442,6 +3448,7 @@
/* unconditional branch */
if (insn (1 11)) {
/* Second half of blx. */
+if(arm_feature(env, ARM_FEATURE_THUMB1)) goto undef;
offset = ((insn 0x7ff) 1);
gen_movl_T0_reg(s, 14);
gen_op_movl_T1_im(offset);
@@ -3571,7 +3578,7 @@
}
if (env-thumb)
- disas_thumb_insn(dc);
+ disas_thumb_insn(env, dc);
else
disas_arm_insn(env, dc);
[Qemu-devel] qemu vl.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Andrzej Zaborowski balrog 07/07/02 13:20:18 Modified files: . : vl.c Log message: gdb stub support and loadvm should work together, patch by Jason Wessel CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemur1=1.317r2=1.318
[Qemu-devel] qemu vl.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Andrzej Zaborowski balrog 07/07/02 13:31:53 Modified files: . : vl.c Log message: Fix qemu_can_send_packet(), makes DHCP with multiple nics work - patch by Jason Wessel. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemur1=1.318r2=1.319
[Qemu-devel] qemu/hw eepro100.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Andrzej Zaborowski balrog 07/07/02 13:38:46 Modified files: hw : eepro100.c Log message: E100 savevm/loadvm support, patch by Jason Wessel. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/eepro100.c?cvsroot=qemur1=1.2r2=1.3
[Qemu-devel] qemu dyngen.h exec-all.h
CVSROOT:/sources/qemu Module name:qemu Changes by: Andrzej Zaborowski balrog 07/07/02 14:06:26 Modified files: . : dyngen.h exec-all.h Log message: Remove unaligned accesses in ia64_apply_fixes(). Make sure that the static variables are not optimized away in GOTO_TB. (patch by Andreas Schwab) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/dyngen.h?cvsroot=qemur1=1.14r2=1.15 http://cvs.savannah.gnu.org/viewcvs/qemu/exec-all.h?cvsroot=qemur1=1.57r2=1.58
Re: [Qemu-devel] [PATCH] qemu-i386 segfaults running hello world.
Hi,
this is the patch we are currently using to build qemu-0.9.0. Does this
work for you?
Alex
--- i386.ld
+++ i386.ld
@@ -1,116 +1,164 @@
-/* ld script to make i386 Linux kernel
- * Written by Martin Mares [EMAIL PROTECTED];
- */
-OUTPUT_FORMAT(elf32-i386, elf32-i386, elf32-i386)
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT(elf32-i386, elf32-i386,
+ elf32-i386)
OUTPUT_ARCH(i386)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/alpha-unknown-linux-gnu/lib);
ENTRY(_start)
+SEARCH_DIR(/usr/i586-suse-linux/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib);
SECTIONS
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[Qemu-devel] qemu vl.c
CVSROOT:/sources/qemu Module name:qemu Changes by: Andrzej Zaborowski balrog 07/07/02 15:03:13 Modified files: . : vl.c Log message: Retry interrupted open() calls (proposed by Yigael Felishman). Linux open(2) doesn't list EINTR, but FreeBSD's open(2) does. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemur1=1.319r2=1.320
Re: [Qemu-devel] [PATCH] ARM7TDMI emulation
On Monday 02 July 2007 15:40, Paul Brook wrote:
You should add/use ARM_FEATURE_V5/ARCH(5) instead.
Alright.
The ARM7TDMI implements the base updated abort model.
Er, yes, but there is no MMU that could actually cause an abort, right?
Anyway, here's the 920T version. The magic numbers may or may not be
correct.
CU
Uli
--
SUSE LINUX Products GmbH, GF: Markus Rex, HRB 16746 (AG Nürnberg)
Index: target-arm/cpu.h
===
RCS file: /sources/qemu/qemu/target-arm/cpu.h,v
retrieving revision 1.28
diff -u -r1.28 cpu.h
--- target-arm/cpu.h 24 Jun 2007 12:09:48 - 1.28
+++ target-arm/cpu.h 2 Jul 2007 15:09:41 -
@@ -247,7 +247,9 @@
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
-ARM_FEATURE_MPU /* Only has Memory Protection Unit, not full MMU. */
+ARM_FEATURE_MPU,/* Only has Memory Protection Unit, not full MMU. */
+ARM_FEATURE_V5, /* ARM v5 instruction set */
+ARM_FEATURE_NO_CP15 /* ARM7TDMI, ARM7TDMI-S, ARM7EJ-S, and ARM9TDMI cores do not have a CP15 */
};
static inline int arm_feature(CPUARMState *env, int feature)
@@ -262,7 +264,9 @@
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
void *opaque);
+#define ARM_CPUID_ARM7TDMI 0x41807000 /* guess; no CP15 on ARM7TDMI */
#define ARM_CPUID_ARM1026 0x4106a262
+#define ARM_CPUID_ARM920T 0x41129200
#define ARM_CPUID_ARM9260x41069265
#define ARM_CPUID_ARM9460x41059461
#define ARM_CPUID_PXA2500x69052100
Index: target-arm/helper.c
===
RCS file: /sources/qemu/qemu/target-arm/helper.c,v
retrieving revision 1.17
diff -u -r1.17 helper.c
--- target-arm/helper.c 24 Jun 2007 12:09:48 - 1.17
+++ target-arm/helper.c 2 Jul 2007 15:09:41 -
@@ -14,20 +14,27 @@
{
env-cp15.c0_cpuid = id;
switch (id) {
+case ARM_CPUID_ARM920T:
+env-cp15.c0_cachetype = 0x0d172172;
+env-cp15.c1_sys = 0x0078;
+break;
case ARM_CPUID_ARM926:
set_feature(env, ARM_FEATURE_VFP);
+set_feature(env, ARM_FEATURE_V5);
env-vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env-cp15.c0_cachetype = 0x1dd20d2;
env-cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
set_feature(env, ARM_FEATURE_MPU);
+set_feature(env, ARM_FEATURE_V5);
env-cp15.c0_cachetype = 0x0f004006;
env-cp15.c1_sys = 0x0078;
break;
case ARM_CPUID_ARM1026:
set_feature(env, ARM_FEATURE_VFP);
set_feature(env, ARM_FEATURE_AUXCR);
+set_feature(env, ARM_FEATURE_V5);
env-vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env-cp15.c0_cachetype = 0x1dd20d2;
env-cp15.c1_sys = 0x00090078;
@@ -38,6 +45,7 @@
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
set_feature(env, ARM_FEATURE_XSCALE);
+set_feature(env, ARM_FEATURE_V5);
/* JTAG_ID is ((id 28) | 0x09265013) */
env-cp15.c0_cachetype = 0xd172172;
env-cp15.c1_sys = 0x0078;
@@ -49,6 +57,7 @@
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
set_feature(env, ARM_FEATURE_XSCALE);
+set_feature(env, ARM_FEATURE_V5);
/* JTAG_ID is ((id 28) | 0x09265013) */
set_feature(env, ARM_FEATURE_IWMMXT);
env-iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
@@ -98,6 +107,7 @@
};
static const struct arm_cpu_t arm_cpu_names[] = {
+{ ARM_CPUID_ARM920T, arm920t},
{ ARM_CPUID_ARM926, arm926},
{ ARM_CPUID_ARM946, arm946},
{ ARM_CPUID_ARM1026, arm1026},
Index: target-arm/translate.c
===
RCS file: /sources/qemu/qemu/target-arm/translate.c,v
retrieving revision 1.53
diff -u -r1.53 translate.c
--- target-arm/translate.c 11 Jun 2007 18:59:35 - 1.53
+++ target-arm/translate.c 2 Jul 2007 15:09:41 -
@@ -1589,7 +1589,7 @@
uint32_t rd;
/* ??? Some cp15 registers are accessible from userspace. */
-if (IS_USER(s)) {
+if (IS_USER(s) || arm_feature(env, ARM_FEATURE_NO_CP15)) {
return 1;
}
if ((insn 0x0fff0fff) == 0x0e070f90
@@ -2958,7 +2958,7 @@
}
}
-static void disas_thumb_insn(DisasContext *s)
+static void disas_thumb_insn(CPUState *env, DisasContext *s)
{
uint32_t val, insn, op, rm, rn, rd, shift, cond;
int32_t offset;
@@ -3058,6 +3058,7 @@
break;
case 3:/* branch [and link] exchange thumb register */
if (insn (1 7)) {
+if(!arm_feature(env, ARM_FEATURE_V5)) goto undef;
val = (uint32_t)s-pc | 1;
gen_op_movl_T1_im(val);
gen_movl_reg_T1(s, 14);
@@ -3367,11 +3368,16 @@
/*
[Qemu-devel] [PATCH] Netlink broken if endianness is wrong
While using i386 X applications on ppc I had to find out that netlink communication is not endianness-aware (X apps just hang forever waiting for a reply on a netlink socket). Because it is basically only used for programs that are not really supposed to be emulated (like udev afaik) there should be no problem to just shut it off. Alex Index: qemu/linux-user/syscall.c === --- qemu.orig/linux-user/syscall.c +++ qemu/linux-user/syscall.c @@ -898,6 +906,7 @@ static long do_socket(int domain, int ty break; } #endif +if(domain == PF_NETLINK) return -EAFNOSUPPORT; /* do not make NETLINK socket connections possible */ return get_errno(socket(domain, type, protocol)); }
[Qemu-devel] [PATCH] ipc endianness and ipc_64 fixes
ipc_semop
This patch fixes an endianness issue with the semop-call.
ipc
This patch implements IPC_64 semantics to the semctl and shmctl calls.
This was tested on ppc host and i386 target and might work on others as
well. This is necessary to get alsa running.
As always: comments and suggestions appreciated
Alex
Index: qemu/linux-user/syscall.c
===
--- qemu.orig/linux-user/syscall.c
+++ qemu/linux-user/syscall.c
@@ -29,7 +29,7 @@
#include unistd.h
#include fcntl.h
#include time.h
-#include sys/types.h
+#include linux/types.h
#include sys/ipc.h
#include sys/msg.h
#include sys/wait.h
@@ -46,6 +46,9 @@
#include sys/uio.h
#include sys/poll.h
#include sys/times.h
+#include asm/ipcbuf.h
+#include asm/shmbuf.h
+#include asm/sembuf.h
#include sys/shm.h
#include sys/sem.h
#include sys/statfs.h
@@ -150,6 +153,7 @@ type name (type1 arg1,type2 arg2,type3 a
#define __NR_sys_tgkill __NR_tgkill
#define __NR_sys_clone __NR_clone
#define __NR_sys_sched_getaffinity __NR_sched_getaffinity
+#define __NR_sys_ipc __NR_ipc
#if defined(__alpha__) || defined (__ia64__) || defined(__x86_64__)
#define __NR__llseek __NR_lseek
@@ -172,6 +176,10 @@ _syscall3(int,sys_rt_sigqueueinfo,int,pi
_syscall3(int,sys_syslog,int,type,char*,bufp,int,len)
_syscall3(int,sys_tgkill,int,tgid,int,pid,int,sig)
_syscall5(int,sys_clone, int, flags, void *, child_stack, int *,
parent_tidptr, void *, newtls, int *, child_tidptr)
+#ifdef __NR_ipc
+_syscall6(int,sys_ipc, long, call, long, first, long, second, long, third,
void *, ptr, long, fifth)
+#define semctl(a,b,c,d) sys_ipc(IPCOP_semctl,a,b,c,d,0l)
+#endif
_syscall3(int,sys_sched_getaffinity,pid_t,pid,unsigned
int,cpusetsize,void*,mask)
#ifdef __NR_exit_group
_syscall1(int,exit_group,int,error_code)
@@ -1255,6 +1263,21 @@ struct target_ipc_perm
target_ulong __unused2;
};
+struct target_ipc64_perm
+{
+ int key;
+ unsigned intuid;
+ unsigned intgid;
+ unsigned intcuid;
+ unsigned intcgid;
+ unsigned short mode;
+ unsigned short __pad1;
+ unsigned short seq;
+ unsigned short __pad2;
+ target_ulong__unused1;
+ target_ulong__unused2;
+};
+
struct target_semid_ds
{
struct target_ipc_perm sem_perm;
@@ -1267,6 +1290,18 @@ struct target_semid_ds
target_ulong __unused4;
};
+struct target_semid64_ds
+{
+ struct target_ipc64_perm sem_perm;
+ target_ulong sem_otime;
+ target_ulong __unused1;
+ target_ulong sem_ctime;
+ target_ulong __unused2;
+ target_ulong sem_nsems;
+ target_ulong __unused3;
+ target_ulong __unused4;
+};
+
static inline void target_to_host_ipc_perm(struct ipc_perm *host_ip,
target_ulong target_addr)
{
@@ -1301,6 +1336,41 @@ static inline void host_to_target_ipc_pe
unlock_user_struct(target_sd, target_addr, 1);
}
+static inline void target_to_host_ipc64_perm( struct ipc64_perm *host_ip,
target_ulong target_addr )
+{
+struct target_ipc64_perm *target_ip;
+struct target_semid64_ds *target_sd;
+
+lock_user_struct(target_sd, target_addr, 1);
+target_ip=(target_sd-sem_perm);
+host_ip-key = tswapl(target_ip-key);
+host_ip-uid = tswapl(target_ip-uid);
+host_ip-gid = tswapl(target_ip-gid);
+host_ip-cuid = tswapl(target_ip-cuid);
+host_ip-cgid = tswapl(target_ip-cgid);
+host_ip-mode = tswap16(target_ip-mode);
+host_ip-seq = tswap16(target_ip-seq);
+unlock_user_struct(target_sd, target_addr, 1);
+}
+
+static inline void host_to_target_ipc64_perm(target_ulong target_addr,
+ struct ipc64_perm *host_ip)
+{
+struct target_ipc64_perm *target_ip;
+struct target_semid64_ds *target_sd;
+
+lock_user_struct(target_sd, target_addr, 0);
+target_ip = (target_sd-sem_perm);
+target_ip-key = tswapl(host_ip-key);
+target_ip-uid = tswapl(host_ip-uid);
+target_ip-gid = tswapl(host_ip-gid);
+target_ip-cuid = tswapl(host_ip-cuid);
+target_ip-cgid = tswapl(host_ip-cgid);
+target_ip-mode = tswap16(host_ip-mode);
+target_ip-seq = tswap16(host_ip-seq);
+unlock_user_struct(target_sd, target_addr, 1);
+}
+
static inline void target_to_host_semid_ds(struct semid_ds *host_sd,
target_ulong target_addr)
{
@@ -1327,6 +1397,32 @@ static inline void host_to_target_semid_
unlock_user_struct(target_sd, target_addr, 1);
}
+static inline void target_to_host_semid64_ds(struct semid64_ds *host_sd,
+ target_ulong target_addr)
+{
+struct target_semid64_ds *target_sd;
+
+lock_user_struct(target_sd, target_addr, 1);
+target_to_host_ipc64_perm((host_sd-sem_perm),target_addr);
+host_sd-sem_nsems = tswapl(target_sd-sem_nsems);
+host_sd-sem_otime = tswapl(target_sd-sem_otime);
+host_sd-sem_ctime = tswapl(target_sd-sem_ctime);
+
Re: [Qemu-devel] [PATCH] Fix two typos
On Sat, Jun 23, 2007 at 11:01:00PM +0200, Stefan Weil wrote: Here is one more formating patch. I've found a whole load of misspellings that I could submit patches for, but I've been waiting until Stefan's fixes are committed. Could they be applied, please? Cheers, -- Stuart Brady
