On 24 June 2015 at 10:09, Fabien Chouteau chout...@adacore.com wrote:
If we completely change the thread synchronization on Windows, maybe
SuspendeThread is not needed anymore, but with the current scheme (at
least what I know of it), I don't see how we can remove it.
As I said before we must
On 2015-06-23 16:38, Yongbok Kim wrote:
The function will be also used for microMIPS Release 6.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c | 472 +++---
1 files
On 24/06/2015 13:40, Pavel Dovgaluk wrote:
+/* If not executing code then assume we are ok. */
+if (cpu-current_tb == NULL) {
+return true;
+}
+return cpu-can_do_io != 0;
For what it's worth, I think the if here is dead. Pavel?
cpu_can_do_io can be
Useful for removing devices from the tree
Signed-off-by: Pavel Fedin p.fe...@samsung.com
---
device_tree.c| 10 ++
include/sysemu/device_tree.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/device_tree.c b/device_tree.c
index d2de580..f666df4 100644
---
Certain machines do not have working vGIC hardware. Linux kernel (at least
up to v4) has configuration options which would still allow to use KVM,
but GIC and timer have to be emulated in userspace. Unfortunately, ARM CPUs
do not have an option to trap access to CP15 virtual timer registers.
size_t is an unsigned type, thus the error case is never reached in
the below call to pread. If bytes is negative, it will be seen as
a very high positive value.
Spotted by Coverity.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
hw/vfio/pci.c | 2 +-
1 file changed, 1 insertion(+), 1
Calling SuspendThread() is not enough to suspend Win32 thread.
We need to call GetThreadContext() after SuspendThread()
to make sure that OS have really suspended target thread.
But GetThreadContext() needs for THREAD_GET_CONTEXT
access right on thread object.
More info about this technique can be
On 2015-06-23 16:38, Yongbok Kim wrote:
Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c | 68
Hi, Paolo,
Sorry, but I don't know what does bisect mean exactly. Could you please
explain it? I feel it might be some kernel configuration items introduce this
problem. I am also trying other kernel versions from 2.6.34 to 2.6.38 (2.6.33.3
has good performance like 2.6.32) and will show
Hi Paolo,
I am not sure if the following information is clear:
I have run a guest on qemu 2.3.0 within different kernels (linux-2.6.32 and
higher versions) on the same PC and tested the FTP performance of the guest
(the server is a windows OS on a remote PC). I found that the FTP download
On Tue, Jun 23, 2015 at 01:57:55PM -0400, John Snow wrote:
On 06/15/2015 10:42 AM, Stefan Hajnoczi wrote:
On Fri, Jun 12, 2015 at 03:02:33PM -0400, John Snow wrote:
On 06/10/2015 10:30 AM, Stefan Hajnoczi wrote:
On Mon, Jun 08, 2015 at 06:21:20PM +0300, Vladimir Sementsov-Ogievskiy
From: Dr. David Alan Gilbert dgilb...@redhat.com
A typo means that the tests dependent on glib with subprocess
support are never run.
Fixes: 9d41401b90fa10b335d2e739149d36437cfbf622
Signed-off-by: Dr. David Alan Gilbert dgilb...@redhat.com
---
configure | 2 +-
1 file changed, 1 insertion(+),
For vfio device, we need to propagate the aer error to
Guest OS. we use the pcie_aer_msg() to send aer error
to guest.
Signed-off-by: Chen Fan chen.fan.f...@cn.fujitsu.com
Reviewed-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pcie_aer.c | 2 +-
include/hw/pci/pcie_aer.h | 1 +
2
On 24/06/2015 06:22, Peter Crosthwaite wrote:
For a summary here is the review state of the multi-arch patch queue.
I have too many reviewed-but-unapplied patches I have stopped working
on the feature until I get some of this already-reviewed work off my
hands (read bottom up):
git log
On 15/06/2015 18:33, Eric Auger wrote:
VFIO platform device needs to setup irqfd but it does not know the
gsi corresponding to the device qemu_irq. This series proposes to
store a hash table in kvm_state using the qemu_irq as key and the gsi
as a value.
kvm_irqchip_set_qemuirq_gsi allows
On 24/06/2015 06:29, Peter Crosthwaite wrote:
Ping!
Can this go via the TCG queue, is there something for VFIO, or can
Peter pick it up as a between-the-maintainerships straggler?
Regards,
Peter
On Fri, Jun 5, 2015 at 11:17 PM, Peter Crosthwaite
crosthwaitepe...@gmail.com wrote:
Hi
On 24 June 2015 at 11:09, Paolo Bonzini pbonz...@redhat.com wrote:
On 23/06/2015 22:30, Peter Crosthwaite wrote:
I'm confused. arm_cpu_is_big_endian() tells you whether the CPU
is *currently* big-endian or not. That doesn't help you with
answering the question I'm about to run a signal
Right now, we don't have an interface to detect that cases and
got back to the iterative stage.
How about go back to the iterative stage when detect that the
pending_size is larger Than max_size, like this:
+/* do flush here is aimed to shorten the VM
pcie_aer_init was used to emulate an aer capability for pcie device,
but for vfio device, the aer config space size is mutable and is not
always equal to PCI_ERR_SIZEOF(0x48). it depends on where the TLP Prefix
register required, so here we add a size argument.
Signed-off-by: Chen Fan
Particularly, For vfio devices, Once need to recovery devices
by bus reset such as AER, we always need to reset the host bus
to recovery the devices under the bus, so we need to add pci bus
callbacks to specify to do host bus reset.
Signed-off-by: Chen Fan chen.fan.f...@cn.fujitsu.com
---
Device's Offset and size can reach PCIE_CONFIG_SPACE_SIZE,
fix the corresponding assert.
Signed-off-by: Chen Fan chen.fan.f...@cn.fujitsu.com
Reviewed-by: Marcel Apfelbaum mar...@redhat.com
---
hw/pci/pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c
squeeze out vfio_pci_do_hot_reset to do host bus reset when AER recovery.
Signed-off-by: Chen Fan chen.fan.f...@cn.fujitsu.com
---
hw/vfio/pci.c | 75 +++
1 file changed, 44 insertions(+), 31 deletions(-)
diff --git a/hw/vfio/pci.c
Hi Paolo
On 06/24/2015 11:55 AM, Paolo Bonzini wrote:
On 15/06/2015 18:33, Eric Auger wrote:
Now that the platform-bus is instantiated in virt, the ARM sysbus-fdt
infrastructure, the VFIO platform device and its first Calxeda xgmac
specialization also are on the master, let's complete the
On 15/06/2015 18:33, Eric Auger wrote:
The arm_gic_kvm now calls kvm_irqchip_set_qemuirq_gsi to build
the hash table storing qemu_irq/gsi mappings. From that point on
irqfd can be setup directly from the qemu_irq using
kvm_irqchip_add_irqfd_notifier.
Signed-off-by: Eric Auger
On 24/06/2015 11:59, Eric Auger wrote:
I think I've now acked everything that's needed from me?
Thanks. what about the
[RESEND PATCH v16 5/6] sysbus: add irq_routing_notifier?
Is that one for Peter C. or anyone else?
There is no real maintainer, so I think Peter's Reviewed-by is
On 06/23/2015 04:38 PM, David Gibson wrote:
On Thu, Jun 18, 2015 at 09:37:36PM +1000, Alexey Kardashevskiy wrote:
This adds support for Dynamic DMA Windows (DDW) option defined by
the SPAPR specification which allows to have additional DMA window(s)
This implements DDW for emulated and VFIO
From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
Bonzini
On 31/05/2015 08:11, Peter Crosthwaite wrote:
+/* If not executing code then assume we are ok. */
+if (cpu-current_tb == NULL) {
+return true;
+}
+return cpu-can_do_io != 0;
Signed-off-by: Pavel Fedin p.fe...@samsung.com
---
hw/arm/boot.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 1e7fd28..35a2aa2 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -10,6 +10,7 @@
#include config.h
#include hw/hw.h
#include
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
On 24/06/2015 13:40, Pavel Dovgaluk wrote:
+/* If not executing code then assume we are ok. */
+if (cpu-current_tb == NULL) {
+return true;
+}
+return cpu-can_do_io != 0;
For what it's worth, I
The TSC frequency fits comfortably in an int when expressed in kHz,
but it may overflow when converted to Hz. In this case,
tsc-frequency returns a negative value because x86_cpuid_get_tsc_freq
does a 32-bit multiplication before assigning to int64_t.
For simplicity just make tsc_khz a 64-bit
Le 24/06/2015 13:56, Paolo Bonzini a écrit :
The miscellaneous commands part of the register is 3 bits wide.
Spotted by Coverity and confirmed in the datasheet, downloadable from
http://cache.freescale.com/files/32bit/doc/ref_manual/MCF5307BUM.pdf
(figure 14-6).
Signed-off-by: Paolo
On 06/24/2015 01:05 AM, Jindřich Makovička wrote:
Fixes a crash during image compression
Signed-off-by: Jindřich Makovička makov...@gmail.com
---
block/qcow2-refcount.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
Rich Jones already confirmed that this
On Tue, Jun 23, 2015 at 11:23:16PM +0200, Michael S. Tsirkin wrote:
On Tue, Jun 23, 2015 at 05:42:04PM +0100, Daniel P. Berrange wrote:
On Tue, Jun 23, 2015 at 06:33:05PM +0200, Michael S. Tsirkin wrote:
On Tue, Jun 23, 2015 at 05:25:55PM +0100, Daniel P. Berrange wrote:
On Tue, Jun 23,
Am 24.06.2015 um 16:11 schrieb Liviu Ionescu:
On 24 Jun 2015, at 16:50, Andreas Färber afaer...@suse.de wrote:
You're still doing the {...} thing I asked you not to do.
thank you for your suggestions.
It's not a suggestion. Our Coding Style is a mandatory requirement for
code review. I
Am 11.04.2015 um 20:34 schrieb Andreas Färber:
Hello,
In my quest to improve our test coverage, in light of the recent cpu_copy()
breakage,
I've taken a stab at make test and actually managed to get most of it to work
on x86_64.
Regards,
Andreas
Ping for 2.4. CC'ing Marc-André.
On 2015-06-19 11:08, Leon Alrae wrote:
From: Maciej W. Rozycki ma...@codesourcery.com
Correct addresses passed around in semihosting to use a data type suitable
for both 32-bit and 64-bit targets.
Signed-off-by: Maciej W. Rozycki ma...@codesourcery.com
Signed-off-by: Leon Alrae
On 2015-06-19 11:08, Leon Alrae wrote:
Signed-off-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c | 25 -
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1d128ee..6fd6dd9 100644
On 24/06/2015 16:54, Peter Maydell wrote:
It's certainly okay for libvirt and OpenStack to use the host CPU
features in order to check whether a node will run a given VM. However,
libvirt should trust that QEMU developers will not prevent a VM from
running on a previously viable host,
On 24 June 2015 at 15:38, Paolo Bonzini pbonz...@redhat.com wrote:
It's certainly okay for libvirt and OpenStack to use the host CPU
features in order to check whether a node will run a given VM. However,
libvirt should trust that QEMU developers will not prevent a VM from
running on a
On 2015-06-24 13:31, Leon Alrae wrote:
On 24/06/2015 12:04, Aurelien Jarno wrote:
+static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
+ int bp)
{
+TCGv t0;
+if (rd == 0) {
+/* Treat as NOP. */
+return;
+}
+
On 2015-06-23 16:38, Yongbok Kim wrote:
add microMIPS32 Release 6 opcode enum
remove RI checking for pre-R6 reserved opcode.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
---
target-mips/translate.c | 119 --
1 files changed, 103
On 24/06/2015 16:16, Eduardo Habkost wrote:
So any single CPU flag now needs to be added in
- kvm
- qemu
- libvirt
Next thing libvirt will decide it's a policy thing and so
needs to be pushed up to openstack.
I don't think that will happen, but if they really decide do do it,
On 2015-06-23 16:38, Yongbok Kim wrote:
add new microMIPS32 Release 6 pool32a/pool32axf instructions.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c | 80 --
1 files
On 2015-06-23 16:38, Yongbok Kim wrote:
add new microMIPS32 Release 6 Major opcode instructions
Signed-off-by: Yongbok Kim yongbok@imgtec.com
---
target-mips/translate.c | 62
++-
1 files changed, 45 insertions(+), 17 deletions(-)
Am 24.06.2015 um 04:31 schrieb Peter Crosthwaite:
From: Bharata B Rao bhar...@linux.vnet.ibm.com
Currently CPUState.cpu_index is monotonically increasing and a newly
created CPU always gets the next higher index. The next available
index is calculated by counting the existing number of CPUs.
On Tue, Jun 23, 2015 at 01:00:44PM -0400, John Snow wrote:
Stefan: I know you said this wasn't expressly requisite, but I was
encouraged by Kevin to send it out as a usability patch for non-libvirt
users, so here it is.
Final Yeah sure or No, definitely not as 2.4 approaches?
Also note
On 2015-06-23 16:38, Yongbok Kim wrote:
add new microMIPS32 Release 6 branch and jump instructions.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c | 242
+++
1 files
Am 24.06.2015 um 11:29 schrieb Liviu Ionescu:
the machine init code now looks like this:
static void stm32_h103_board_init_callback(MachineState *machine)
{
cm_board_greeting(machine);
{
/* Create the MCU */
DeviceState *mcu = cm_create(TYPE_STM32F103RB);
* Wen Congyang (ghost...@gmail.com) wrote:
At 2015/6/19 18:49, Stefan Hajnoczi Wrote:
On Fri, Jun 19, 2015 at 08:54:56AM +0800, Wen Congyang wrote:
On 06/19/2015 12:06 AM, Stefan Hajnoczi wrote:
On Thu, Jun 18, 2015 at 10:36:39PM +0800, Wen Congyang wrote:
At 2015/6/18 20:55, Stefan Hajnoczi
On Wed, Jun 24, 2015 at 11:16:51AM -0300, Eduardo Habkost wrote:
IMHO -M pc is not supposed to mean can break at any time.
It means it may have new host-side requirements and may become runnable
in your host (or require additional command-line flags to run) at any time.
That would be pretty
On Tue, Jun 23, 2015 at 03:56:09PM +0100, Stefan Hajnoczi wrote:
Commit f006cf7fa9a63ba8e4ccf57d46231ce594301727 (qdev-monitor:
Propagate errors through qdev_device_add()) dropped a meaningless error
message. This change in output caused qemu-iotests 051 to fail:
QEMU_PROG: -device
On 24 Jun 2015, at 17:18, Andreas Färber afaer...@suse.de wrote:
... our Coding Style.
sorry, but I checked both QEMU Coding Style and QEMU Coding Guidelines and
could not find any rule forbidding the use of blocks for introducing local
scopes.
regards,
Liviu
On 2015-06-19 11:08, Leon Alrae wrote:
Convert only errno values which can be returned by system calls in
mips-semi.c and are not generic to all archs.
Signed-off-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/mips-semi.c | 44 +---
1 file
On 2015-06-23 16:38, Yongbok Kim wrote:
add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
Signed-off-by: Yongbok Kim yongbok@imgtec.com
---
target-mips/translate.c | 27 +--
1 files changed, 21 insertions(+), 6 deletions(-)
Reviewed-by: Aurelien
Hello Zhu,
Are you still working on this feature? Could you provide a rebased
version of this series?
Regards,
On Fri, Feb 13, 2015 at 06=40=15PM +0800, Zhu Guihua wrote:
This series is based on chen fan's previous i386 cpu hot remove patchset:
On Tue, Jun 23, 2015 at 11:28:06PM +0200, Michael S. Tsirkin wrote:
On Tue, Jun 23, 2015 at 02:42:37PM -0300, Eduardo Habkost wrote:
On Tue, Jun 23, 2015 at 07:29:15PM +0200, Andreas Färber wrote:
In summary you seem to be saying that all the years we have spent
fiddling around with those
On Tue, Jun 23, 2015 at 11:34:45PM +0200, Michael S. Tsirkin wrote:
On Tue, Jun 23, 2015 at 02:11:22PM -0300, Eduardo Habkost wrote:
Even if it is a bug fix. If it is a change that can make the VM
unrunnable, it needs to be controlled by a separate flag, not by the
machine-type.
I agree
Am 24.06.2015 um 11:51 schrieb Paolo Bonzini:
On 24/06/2015 11:29, Liviu Ionescu wrote:
ok, I managed to restructure my code to get rid of the explicit
constructor. :-)
I also avoided properties aliases, and did prop setting in two steps,
in machine init I set props in MCU, and from here I
On 2015-06-23 16:38, Yongbok Kim wrote:
Define a new CPU definition supporting MIPS32 Release 6 ISA and
microMIPS32 Release 6 ISA.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
---
target-mips/translate_init.c | 37 +
1 files changed, 37
On 24/06/2015 13:28, Aurelien Jarno wrote:
On 2015-06-23 16:38, Yongbok Kim wrote:
64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
On Wed, Jun 24, 2015 at 11:18:18AM -0300, Eduardo Habkost wrote:
On Tue, Jun 23, 2015 at 11:28:06PM +0200, Michael S. Tsirkin wrote:
On Tue, Jun 23, 2015 at 02:42:37PM -0300, Eduardo Habkost wrote:
On Tue, Jun 23, 2015 at 07:29:15PM +0200, Andreas Färber wrote:
In summary you seem to be
On 2015-06-19 11:08, Leon Alrae wrote:
Add UHI semihosting support for MIPS. QEMU run with -semihosting option
will alter the behaviour of SDBBP 1 instruction -- UHI operation will be
called instead of generating a debug exception.
Also tweak Malta's pseudo-bootloader. On CPU reset the $4
Add new microMIPS32 Release 6 POOL32F instructions
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 231 ---
1 files changed,
Add new microMIPS32 Release 6 branch and jump instructions.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 242 +++
1 files
Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 27 +--
1 files changed, 21 insertions(+), 6 deletions(-)
diff --git
The function will be also used for microMIPS Release 6.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 472 +++---
1 files
Add new microMIPS32 Release 6 pool32a/pool32axf instructions.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 80 --
1
Add new microMIPS32 Release 6 Major opcode instructions
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 62 ++-
1 files changed, 45 insertions(+), 17 deletions(-)
diff
On Wed, Jun 24, 2015 at 11:29 AM, Andreas Färber afaer...@suse.de wrote:
Am 24.06.2015 um 20:00 schrieb Andreas Färber:
Am 24.06.2015 um 05:19 schrieb Peter Crosthwaite:
Use cpu_set_pc() for setting program counters when bootloading. This
removes an instance of system level code having to
From: Chen Fan chen.fan.f...@cn.fujitsu.com
After CPU hotplug has been converted to BUS-less hot-plug infrastructure,
the only function ICC bus performs is to propagate reset to LAPICs. However
LAPIC could be reset by registering its reset handler after all device are
initialized.
Do so and drop
Add a wrapper to specify reset order when registering reset handler,
instead of non-obvious initiazation code ordering.
Signed-off-by: Zhu Guihua zhugh.f...@cn.fujitsu.com
---
include/hw/hw.h | 4
vl.c| 18 +-
2 files changed, 21 insertions(+), 1 deletion(-)
From: Chen Fan chen.fan.f...@cn.fujitsu.com
Replace mapping APIC at global system address space with
mapping it at per-CPU address spaces.
Signed-off-by: Chen Fan chen.fan.f...@cn.fujitsu.com
Signed-off-by: Zhu Guihua zhugh.f...@cn.fujitsu.com
---
exec.c| 5 +
hw/i386/pc.c
ICC Bus was used for providing a hotpluggable bus for APIC and CPU,
but now we use HotplugHandler to make hotplug. So ICC Bus is
unnecessary.
This code has passed the new pc-cpu-test.
And I have tested with kvm along with kernel_irqchip=on/off,
it works fine.
This patch series is based on the
Refactor those instructions in order to reuse them for microMIPS32
Release 6.
Rearrange gen_move_low32().
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 166
The patchset implements the latest microMIPS32 Release 6 Instruction Set.
However LLX, LLXE, SCX and SCXE aren't included in the patchset.
For more information, microMIPS R6 Instruction Set document is available:
MIPS Architecture for Programmers Volume II-B: microMIPS32 Instruction Set
Revision
rt, rs were swapped
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Reviewed-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c
Add microMIPS TLBINV, TLBINVF
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
Reviewed-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git
Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 68
microMIPS32 Release 6 POOL16A/ POOL16C instructions
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 133 +-
1 files changed, 118 insertions(+), 15 deletions(-)
diff
64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in FCSR0(FIR)
but do
Define a new CPU definition supporting MIPS32 Release 6 ISA and
microMIPS32 Release 6 ISA.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate_init.c | 37 +
1 files changed, 37
On 24 June 2015 at 17:34, Alex Bennée alex.ben...@linaro.org wrote:
Testing with Alexander's bare metal syncronisation tests fails in MTTCG
leaving one CPU spinning forever waiting for the second CPU to wake up.
We simply need to poke the halt_cond once we have processed the PSCI
power on
On 06/24/2015 10:07 PM, Dr. David Alan Gilbert wrote:
* Wen Congyang (ghost...@gmail.com) wrote:
At 2015/6/19 18:49, Stefan Hajnoczi Wrote:
On Fri, Jun 19, 2015 at 08:54:56AM +0800, Wen Congyang wrote:
On 06/19/2015 12:06 AM, Stefan Hajnoczi wrote:
On Thu, Jun 18, 2015 at 10:36:39PM +0800,
On Wed, 06/24 19:01, Paolo Bonzini wrote:
On 24/06/2015 11:08, Fam Zheng wrote:
Stefan,
The only controversial patches are the qmp/drive-mirror ones (1-3), while
patches 4-8 are still useful on their own: they fix the mentioned crash and
improve iotests.
Shall we merge the
On Wed, 06/24 16:19, Stefan Hajnoczi wrote:
On Tue, Jun 23, 2015 at 03:43:53PM +0100, Dr. David Alan Gilbert (git) wrote:
From: Dr. David Alan Gilbert dgilb...@redhat.com
Add a gdb command to print the current set of IOHandlers and
if one of them is a thread yielding for data print the
Is there anything else you would like me to test?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1467240
Title:
Regression - bridged networking broken for Mac OS X guest
Status in QEMU:
New
Bug
On Wed, 06/24 18:14, Max Reitz wrote:
On 09.06.2015 04:13, Fam Zheng wrote:
In block/backup.c, we already check and add blocker on the target bs,
which is necessary so that it won't be intervened with other operations.
In block/mirror.c we should also protect the mirror target bs, because it
On Wed, 06/24 18:34, Max Reitz wrote:
On 09.06.2015 04:13, Fam Zheng wrote:
This is the part that will be reused by blockdev-mirror.
Signed-off-by: Fam Zheng f...@redhat.com
---
blockdev.c | 158
+++--
1 file changed, 92
Remove an unused argument from decode_micromips32_opc()
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Leon Alrae leon.al...@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
Add microMIPS32 Release 6 opcode enum.
Remove RI checking for pre-R6 reserved opcode.
Signed-off-by: Yongbok Kim yongbok@imgtec.com
Reviewed-by: Aurelien Jarno aurel...@aurel32.net
---
target-mips/translate.c | 119 --
1 files changed, 103
ICC bus impl has been droped, so all icc related files are not useful
any more; delete them.
Signed-off-by: Zhu Guihua zhugh.f...@cn.fujitsu.com
---
default-configs/i386-softmmu.mak | 1 -
default-configs/x86_64-softmmu.mak | 1 -
hw/cpu/Makefile.objs | 1 -
On 24/06/2015 15:37, Aurelien Jarno wrote:
On 2015-06-19 11:08, Leon Alrae wrote:
Signed-off-by: Leon Alrae leon.al...@imgtec.com
---
target-mips/translate.c | 25 -
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/target-mips/translate.c
On Mon, Jun 22, 2015 at 08:10:28PM -0300, Paulo Alcantara wrote:
This block is mapped into memory space, using the Root Complex Base
Address (RCBA) register of the PCI-to-LPC bridge. Accesses in this space
must be limited to 32-(DW) bit quantities. Burst accesses are not
allowed.
All
I think this will reboot the discussion in a good way.
I have talked to Paolo on the phone, and I think I had a big assumption
that was not true:
On Wed, Jun 24, 2015 at 04:37:33PM +0200, Michael S. Tsirkin wrote:
On Wed, Jun 24, 2015 at 11:24:46AM -0300, Eduardo Habkost wrote:
[...]
There
From: Dimitris Aragiorgis dim...@arrikto.com
Building the QEMU tools fails if we #define DEBUG_BLOCK inside
block/raw-posix.c. Here instead of adding qemu-log.o in block-obj-y
so that DEBUG_BLOCK_PRINT can be used, we substitute the latter with
a simple DPRINTF() (that does not cause bit-rot).
Both is_netdev and !is_netdev paths already check that
net_client_init_func[opts-kind] is non-NULL so there is no need for the
if statement.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
Reviewed-by: Thomas Huth th...@redhat.com
Message-id:
Drop the union and move the hubport creation into the !is_netdev case.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
Reviewed-by: Thomas Huth th...@redhat.com
Message-id: 1432743412-15943-6-git-send-email-stefa...@redhat.com
---
net/net.c | 38 --
1 file
Am 24.06.2015 um 16:57 schrieb Michael S. Tsirkin:
On Wed, Jun 24, 2015 at 04:35:13PM +0200, Andreas Färber wrote:
Am 24.06.2015 um 16:19 schrieb Michael S. Tsirkin:
On Wed, Jun 24, 2015 at 11:16:51AM -0300, Eduardo Habkost wrote:
IMHO -M pc is not supposed to mean can break at any time.
It
The following changes since commit a3206972a9eab65ec8e8f9ae320ad628ba4b58f1:
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2015-06-22'
into staging (2015-06-23 10:38:00 +0100)
are available in the git repository at:
git://github.com/stefanha/qemu.git tags/net-pull-request
From: Lu Lina lina.lul...@huawei.com
Signed-off-by: Lu Lina lina.lul...@huawei.com
Acked-by: Keith Busch keith.bu...@intel.com
Message-id: 1434695254-69808-1-git-send-email-kathy.wangt...@huawei.com
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
hw/block/nvme.c | 1 +
1 file changed, 1
101 - 200 of 339 matches
Mail list logo
