Re: [Qemu-devel] [PATCH v2 14/67] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group

On 23 February 2018 at 17:25, Richard Henderson wrote: > On 02/23/2018 05:08 AM, Peter Maydell wrote: >>> +# SVE unary bit operations (predicated) >>> +# Note esz != 0 for FABS and FNEG. >>> +CLS0100 .. 011 000 101 ... . . @rd_pg_rn

Re: [Qemu-devel] [PATCH v2 15/29] qapi: Record 'include' directives in parse tree

Michael Roth writes: > Quoting Markus Armbruster (2018-02-11 03:35:53) >> The parse tree is a list of expressions. Except include expressions >> currently get replaced by the included file's parse tree. >> >> Instead of throwing away the include expression, keep it

[Qemu-devel] [PATCH v4 2/3] s390x/sclp: clean up sclp masks

Introduce an sccb_mask_t to be used for SCLP event masks instead of just unsigned int or uint32_t. This will allow later to extend the mask with more ease. Signed-off-by: Claudio Imbrenda --- hw/char/sclpconsole-lm.c | 4 ++-- hw/char/sclpconsole.c

[Qemu-devel] [PATCH v4 1/3] s390x/sclp: proper support of larger send and receive masks

Until 67915de9f0383ccf4a ("s390x/event-facility: variable-length event masks") we only supported sclp event masks with a size of exactly 4 bytes, even though the architecture allows the guests to set up sclp event masks from 1 to 1021 bytes in length. After that patch, the behaviour was almost

Re: [Qemu-devel] [PATCH v2 23/29] Include less of the generated modular QAPI headers

Eric Blake writes: > On 02/11/2018 03:36 AM, Markus Armbruster wrote: >> In my "build everything" tree, a change to the types in >> qapi-schema.json triggers a recompile of about 4800 out of 5100 >> objects. >> >> The previous commit split up qmp-commands.h, qmp-event.h,

[Qemu-devel] [PATCH v4 3/3] s390x/sclp: extend SCLP event masks to 64 bits

Extend the SCLP event masks to 64 bits. Notice that using any of the new bits results in a state that cannot be migrated to an older version. Signed-off-by: Claudio Imbrenda --- hw/s390x/event-facility.c | 56 ++-

Re: [Qemu-devel] [PATCH v2 1/1] hw: register: Run post_write hook on reset

On 22 February 2018 at 19:45, Alistair Francis wrote: > On Thu, Feb 15, 2018 at 3:05 PM, Alistair Francis > wrote: >> On Mon, Feb 5, 2018 at 10:44 AM, Alistair Francis >> wrote: >>> Ensure that the post write hook

Re: [Qemu-devel] [PATCH v2 19/36] rbd: Factor out qemu_rbd_connect()

Am 23.02.2018 um 00:10 hat Max Reitz geschrieben: > On 2018-02-21 14:53, Kevin Wolf wrote: > > The code to establish an RBD connection is duplicated between open and > > create. In order to be able to share the code, factor out the code from > > qemu_rbd_open() as a first step. > > > >

Re: [Qemu-devel] [PATCH v2 27/36] sheepdog: QAPIfy "redundacy" create option

Am 21.02.2018 um 14:53 hat Kevin Wolf geschrieben: > The "redundacy" option for Sheepdog image creation is currently a string > that can encode one or two integers depending on its format, which at > the same time implicitly selects a mode. > > This patch turns it into a QAPI union and converts

[Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags

Half-precision flush to zero behaviour is controlled by a separate FZ16 bit in the FPCR. To handle this we pass a pointer to fp_status_fp16 when working on half-precision operations. The value of the presented FPCR is calculated from an amalgam of the two when read. Signed-off-by: Alex Bennée

[Qemu-devel] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment fix

We do implement all the opcodes. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c

[Qemu-devel] [PATCH v3 01/31] include/exec/helper-head.h: support f16 in helper calls

This allows us to explicitly pass float16 to helpers rather than assuming uint32_t and dealing with the result. Of course they will be passed in i32 sized registers by default. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson ---

[Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values

Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 267a9d7e2f..c2bce23fa5 100644 --- a/target/arm/cpu.h +++

[Qemu-devel] [PATCH v3 18/31] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16

This covers all the floating point convert operations. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/helper-a64.c| 32 + target/arm/helper-a64.h| 2 ++ target/arm/translate-a64.c | 85

[Qemu-devel] [PATCH v3 11/31] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16

Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/helper-a64.c| 24 target/arm/helper-a64.h| 2 ++ target/arm/translate-a64.c | 15 +++ 3 files changed, 41 insertions(+)

[Qemu-devel] [PATCH v3 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16

This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/translate-a64.c | 208 + 1 file changed, 133 insertions(+), 75 deletions(-) diff --git

[Qemu-devel] [PATCH v3 15/31] arm/translate-a64: add FP16 x2 ops for simd_indexed

A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get

[Qemu-devel] [PATCH v9 02/13] s390-ccw: refactor eckd_block_num to use CHS

Add new cylinder/head/sector struct. Use it to calculate eckd block numbers instead of a BootMapPointer (which used eckd chs anyway). Signed-off-by: Collin L. Walling Reviewed-by: Thomas Huth --- pc-bios/s390-ccw/bootmap.c | 28

[Qemu-devel] [PATCH v3 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16

Neither of these operations alter the floating point status registers so we can do a pure bitwise operation, either squashing any sign bit (ABS) or inverting it (NEG). Signed-off-by: Alex Bennée --- v3 - fixup re-base conflicts - make both operations pure bitwise TCG

[Qemu-devel] [PATCH v9 08/13] s390-ccw: read stage2 boot loader data to find menu

Read the stage2 boot loader data block-by-block. We scan the current block for the string "zIPL" to detect the start of the boot menu banner. We then load the adjacent blocks (previous block and next block) to account for the possibility of menu data spanning multiple blocks. Signed-off-by:

[Qemu-devel] [PATCH v3 24/31] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16

We go with the localised helper. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/helper-a64.c| 29 + target/arm/helper-a64.h| 1 + target/arm/translate-a64.c | 4 3 files

[Qemu-devel] [PATCH v3 22/31] arm/helper.c: re-factor recpe and add recepe_f16

It looks like the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final

[Qemu-devel] [PATCH v9 07/13] s390-ccw: set up interactive boot menu parameters

Reads boot menu flag and timeout values from the iplb and sets the respective fields for the menu. Signed-off-by: Collin L. Walling Reviewed-by: Thomas Huth --- pc-bios/s390-ccw/Makefile | 2 +- pc-bios/s390-ccw/main.c | 24

[Qemu-devel] [PATCH v9 13/13] s390-ccw: interactive boot menu for scsi

Interactive boot menu for scsi. This follows a similar procedure as the interactive menu for eckd dasd. An example follows: s390x Enumerated Boot Menu. 3 entries detected. Select from index 0 to 2. Signed-off-by: Collin L. Walling Reviewed-by: Thomas Huth

[Qemu-devel] [PATCH v1 3/8] aarch64.risu: add cryptographic extensions for v8.2

Signed-off-by: Alex Bennée --- aarch64.risu | 32 1 file changed, 32 insertions(+) diff --git a/aarch64.risu b/aarch64.risu index 838bded..06a9f3c 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2937,3 +2937,35 @@ FCVTZUsi_RES A64_V sf:1

[Qemu-devel] [PATCH v1 8/8] aarch64.risu: update Floating-point data-processing (1 source)

This adds the half-precision encoding and shuffles around the RES space to indicate this. Signed-off-by: Alex Bennée --- aarch64.risu | 55 +++ 1 file changed, 27 insertions(+), 28 deletions(-) diff --git

Re: [Qemu-devel] [edk2] [PATCH 1/7] SecurityPkg/Tcg2Pei: drop Tcg2PhysicalPresenceLib dependency

On 02/23/18 14:23, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Apparently, unnecessary. Avoids extra build dependency and churn. > > CC: Laszlo Ersek > CC: Stefan Berger > Contributed-under:

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 01/67] target/arm: Enable SVE for aarch64-linux-user

Richard Henderson writes: > Enable ARM_FEATURE_SVE for the generic "any" cpu. > > Signed-off-by: Richard Henderson > --- > target/arm/cpu.c | 7 +++ > target/arm/cpu64.c | 1 + > 2 files changed, 8 insertions(+) > > diff --git

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 00/67] target/arm: Scalable Vector Extension

Richard Henderson writes: > This is 99% of the instruction set. There are a few things missing, > notably first-fault and non-fault loads (even these are decoded, but > simply treated as normal loads for now). > > The patch set is dependant on at least 3 other

Re: [Qemu-devel] [PATCH v1 4/8] new contrib/generate_all.sh: batch risugen script

On Fri, Feb 23, 2018 at 05:01:42PM +, Peter Maydell wrote: > On 23 February 2018 at 16:49, Daniel P. Berrangé wrote: > > If it is going to live in QEMU source tree, then avoiding introducing a new > > license is desirable. > > It isn't -- risu has its own repository.

Re: [Qemu-devel] [PATCH 3/3] qapi: Rename .json to .qapi

Marc-André Lureau writes: > Hi > > On Mon, Feb 12, 2018 at 10:52 AM, Daniel P. Berrangé > wrote: >> On Sat, Feb 10, 2018 at 06:40:13PM -0600, Eric Blake wrote: >>> Our QAPI input files aren't quite true JSON (comments being the obvious >>>

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 42/67] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/helper-sve.h| 25 + > target/arm/sve_helper.c| 41 ++ > target/arm/translate-sve.c | 135 >

[Qemu-devel] [PATCH v6 1/3] xlnx-zynqmp-rtc: Initial commit

Initial commit of the ZynqMP RTC device. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- v5: - Don't use intermediate val V2: - Delete unused realise function - Remove DB_PRINT() include/hw/timer/xlnx-zynqmp-rtc.h | 84

[Qemu-devel] [PATCH v6 0/3] Add and connect the ZynqMP RTC

V6: - Migrate tick_offset and add a pre_save call V5: - Recalculate tick_offset after migration V4: - Use the RegisterAccessInfo .unimp functionality V3: - Store an offset value - Use mktimegm() - Log unimplemented writes V2: - Delete unused realise function - Add cover letter -

[Qemu-devel] [PATCH] ppc: Fix size of ppc64 xer register (fwd)

The normal gdb definition of the XER registers is only 32 bit, and that's what the current version of power64-core.xml also says (seems copied from gdb's). But qemu's idea of the XER register is target_ulong (in CPUPPCState, ppc_gdb_register_len and ppc_cpu_gdb_read_register) That mismatch leads

Re: [Qemu-devel] [edk2] [PATCH 2/7] ovmf: link with Tcg2ConfigPei module

On 02/23/18 14:23, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > This module initializes TPM device type based on variable and > detection. (1) I suggest we say the following here: "The Tcg2ConfigPei module informs the firmware globally about the

[Qemu-devel] [PATCH v1] numa: s390x has no NUMA

Right now it is possible to crash QEMU for s390x by providing e.g. -numa node,nodeid=0,cpus=0-1 Problem is, that numa.c uses mc->cpu_index_to_instance_props as an indicator whether NUMA is supported by a machine type. We don't implement NUMA on s390x (and that concept also doesn't really

Re: [Qemu-devel] [PATCH v2 22/29] qapi: Generate separate .h, .c for each module

Eric Blake writes: > On 02/11/2018 03:36 AM, Markus Armbruster wrote: >> Our qapi-schema.json is composed of modules connected by include >> directives, but the generated code is monolithic all the same: one >> qapi-types.h with all the types, one qapi-visit.h with all the >>

[Qemu-devel] [PATCH v4 0/3] s390x/sclp: 64 bit event masks

Until 67915de9f0383ccf4a ("s390x/event-facility: variable-length event masks") we only supported 32bit sclp event masks, even though the archiecture allows the guests to set up sclp event masks up to 1021 bytes in length. With that patch the behaviour was almost compliant, but some issues were

Re: [Qemu-devel] [PATCH v2 24/29] qapi: Empty out qapi-schema.json

Eric Blake writes: > On 02/11/2018 03:36 AM, Markus Armbruster wrote: >> The previous commit improved compile time by including less of the >> generated QAPI headers. This is impossible for stuff defined directly >> in qapi-schema.json, because that ends up in headers that

Re: [Qemu-devel] [PATCH] maintainers: Add myself as a OpenBSD maintainer

On Fri, 02/16 14:44, Philippe Mathieu-Daudé wrote: > On 02/16/2018 02:41 PM, Kamil Rytarowski wrote: > > On 16.02.2018 18:30, Philippe Mathieu-Daudé wrote: > >> But before announcing the host OS being supported again, I'd rather see > >> reproducible build/tests logs, in a (public - if possible)

Re: [Qemu-devel] [PATCH v3 2/3] util/uri.c: only remove `return`'s brackets

On 23.02.2018 08:51, Su Hang wrote: > only remove brackets that wrap `return` statements' content. > > use `perl -pi -e "s/return \((.*?)\);/return \1;/g" util/uri.c` > to remove pattern like this: "return (1);" > > Signed-off-by: Su Hang > --- > util/uri.c | 160 >

Re: [Qemu-devel] [PATCH v8 00/13] Interactive Boot Menu for DASD and SCSI Guests on s390x

Hmmm, on my ubuntu 16.04 guest, I get the boot menu with no timeout even if I do not specify loadparm or boot menu: qemu-kvm -drive file=/var/lib/libvirt/qemu/image.zhyp140,if=none,id=d1 -device virtio-blk-ccw,drive=d1,bootindex=1 LOADPARM=[] Using virtio-blk. Using SCSI scheme.

Re: [Qemu-devel] [PATCH] vl: introduce vm_shutdown()

On Tue, 02/20 13:10, Stefan Hajnoczi wrote: > 1. virtio_scsi_handle_cmd_vq() racing with iothread_stop_all() hits the >virtio_scsi_ctx_check() assertion failure because the BDS AioContext >has been modified by iothread_stop_all(). Does this patch fix the issue completely? IIUC

Re: [Qemu-devel] [PATCH v3 1/3] util/uri.c: replace TAB with whitespace

Hi, thanks for splitting your patch in more reviewable parts :-) Meta-comment: If you send a patch series, please include a cover letter next time ("PATCH 0/3") with a brief summary. Then the patch series shows up nicely as a thread in the e-mail programs of the reviewers (you also got to send

Re: [Qemu-devel] [PATCH v4 4/7] qdev: add hotpluggable to DeviceState

Hi, > > What type of device is only sometimes hotpluggable ? > > The commit message says "display devices" and "consoles", > > but I would expect those to both be types of device which > > have a class which is never hotpluggable, so you can mark > > them non-hotpluggable with the existing

Re: [Qemu-devel] [PATCH v3 1/3] s390x/sclp: proper support of larger send and receive masks

On Fri, 23 Feb 2018 15:27:02 +0100 Christian Borntraeger wrote: [...] > > +/* copy up to dst_len bytes and fill the rest of dst with zeroes > > */ > > you just moved this function but shouldnt it be > > src_len bytes and fill will zeroes until dst_len?

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 29/67] target/arm: Implement SVE Permute - Interleaving Group

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/helper-sve.h| 15 ++ > target/arm/sve_helper.c| 72 > ++ >

[Qemu-devel] [RFC PATCH 0/5] atapi: change unlimited recursion to while loop

Real hardware doesn't have an unlimited stack, so the unlimited recursion in the ATAPI code smells a bit. In fact, the call to ide_transfer_start easily becomes a tail call with a small change to the code (patch 4). The remaining four patches move code around so as to the turn the call back to

[Qemu-devel] [PATCH 4/5] atapi: call ide_set_irq before ide_transfer_start

The ATAPI_INT_REASON_IO interrupt is raised when I/O starts, but in the AHCI case ide_set_irq was actually called at the end of a mutual recursion. Move it early, with the side effect that ide_transfer_start becomes a tail call in ide_atapi_cmd_reply_end. Signed-off-by: Paolo Bonzini

[Qemu-devel] [PATCH v3 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16

I've re-factored the handle_simd_intfp_conv helper to properly handle half-precision as well as call plain conversion helpers when we are not doing fixed point conversion. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson ---

[Qemu-devel] [PATCH v3 09/31] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16

The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - add absh helper - fix checkpatch violation - make

[Qemu-devel] [PATCH v9 04/13] s390-ccw: update libc

Moved: memcmp from bootmap.h to libc.h (renamed from _memcmp) strlen from sclp.c to libc.h (renamed from _strlen) Added C standard functions: isdigit Added non C-standard function: uitoa atoui Signed-off-by: Collin L. Walling Acked-by: Christian

[Qemu-devel] [PATCH v3 28/31] arm/translate-a64: add FP16 FMOV to simd_mod_imm

Only one half-precision instruction has been added to this group. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes v3 - use vfp_expand_imm --- target/arm/translate-a64.c | 35 +-- 1 file changed, 25 insertions(+), 10 deletions(-)

[Qemu-devel] [PATCH v9 01/13] s390-ccw: refactor boot map table code

Some ECKD bootmap code was using structs designed for SCSI. Even though this works, it confuses readability. Add a new BootMapTable struct to assist with readability in bootmap entry code. Also: - replace ScsiMbr in ECKD code with appropriate structs - fix read_block messages to reflect

[Qemu-devel] [PATCH v9 11/13] s390-ccw: set cp_receive mask only when needed and consume pending service irqs

It is possible while waiting for multiple types of external interrupts that we might have pending irqs remaining between irq consumption and irq-type disabling. Those interrupts could potentially propagate to the guest after IPL completes and cause unwanted behavior. As it is today, the SCLP will

[Qemu-devel] [PATCH v3 23/31] arm/translate-a64: add FP16 FRECPE

Now we have added f16 during the re-factoring we can simply call the helper. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 8 1 file changed, 8 insertions(+) diff --git

[Qemu-devel] [PATCH v1 4/8] new contrib/generate_all.sh: batch risugen script

This is a simple script for generating all instructions in a given RISU file. You can split up the batch size by passing a -n N command line options. For example: ./contrib/generate_all.sh -n 2 hp.risu testcases.armv8.2_hp Signed-off-by: Alex Bennée ---

Re: [Qemu-devel] [edk2] [PATCH 0/7] RFC: ovmf: preliminary TPM2 support

On 02/23/18 14:23, marcandre.lur...@redhat.com wrote: > From: Marc-André Lureau > > Hi, > > The following series adds basic TPM2 support for OVMF-on-QEMU (I > haven't tested TPM1, for lack of interest). It links with the modules > to initializes the device in PEI

[Qemu-devel] [PATCH v1 7/8] contrib/run_risu.sh: add a visual cue for a clean-run

It saves you from having to check the status code or wonder if the errors just scrolled off your screen. Signed-off-by: Alex Bennée --- contrib/run_risu.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/contrib/run_risu.sh b/contrib/run_risu.sh index

[Qemu-devel] [PATCH v1 5/8] contrib/run_risu.sh: allow appending of QEMU_FLAGS

Useful if you want to disable a feature for your run. For example: set -x QEMU_FLAGS "-cpu fp16=off" Signed-off-by: Alex Bennée --- contrib/run_risu.sh | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/contrib/run_risu.sh b/contrib/run_risu.sh

[Qemu-devel] [PATCH v1 2/8] aarch64.risu: clean-up and annotate with groups

Clean-up the risu definitions by: - removing out-dated section numbers - fixing section titles to match ASL encoding groups - add @Section markers Signed-off-by: Alex Bennée --- aarch64.risu | 200 +-- 1 file

[Qemu-devel] [PATCH v3 12/31] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16

As some of the constants here will also be needed elsewhere (specifically for the upcoming SVE support) we move them out to softfloat.h. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v3 - move constants used for estimate

Re: [Qemu-devel] [PATCH v2 36/67] target/arm: Implement SVE Integer Compare - Vectors Group

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c > index 86cd792cdf..ae433861f8 100644 > --- a/target/arm/sve_helper.c >

Re: [Qemu-devel] [PATCH v2 21/36] rbd: Pass BlockdevOptionsRbd to qemu_rbd_connect()

On 2018-02-23 17:19, Kevin Wolf wrote: > Am 23.02.2018 um 00:25 hat Max Reitz geschrieben: >> On 2018-02-21 14:53, Kevin Wolf wrote: >>> With the conversion to a QAPI options object, the function is now >>> prepared to be used in a .bdrv_co_create implementation. >>> >>> Signed-off-by: Kevin Wolf

Re: [Qemu-devel] [PATCH v2 17/36] gluster: Support .bdrv_co_create

On 02/21/2018 07:53 AM, Kevin Wolf wrote: This adds the .bdrv_co_create driver callback to gluster, which enables image creation over QMP. Signed-off-by: Kevin Wolf --- qapi/block-core.json | 18 ++- block/gluster.c | 135

Re: [Qemu-devel] [PATCH v2 18/36] rbd: Fix use after free in qemu_rbd_set_keypairs() error path

On 02/21/2018 07:53 AM, Kevin Wolf wrote: If we want to include the invalid option name in the error message, we can't free the string earlier than that. Signed-off-by: Kevin Wolf --- block/rbd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) D'oh. Should this

Re: [Qemu-devel] [PATCH v2 28/67] target/arm: Implement SVE Permute - Predicates Group

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/helper-sve.h| 6 + > target/arm/sve_helper.c| 280 > + >

[Qemu-devel] [PATCH v3 05/31] target/arm/helper: pass explicit fpst to set_rmode

As the rounding mode is now split between FP16 and the rest of floating point we need to be explicit when tweaking it. Instead of passing the CPU env we now pass the appropriate fpst pointer directly. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson

[Qemu-devel] [PATCH v3 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16

This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Bennée Reviewed-by: Richard

[Qemu-devel] [PATCH v3 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16

These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/helper-a64.c| 49

[Qemu-devel] [PATCH v3 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16

This actually covers two different sections of the encoding table: Advanced SIMD scalar two-register miscellaneous FP16 Advanced SIMD two-register miscellaneous (FP16) The difference between the two is covered by a combination of Q (bit 30) and S (bit 28). Notably the FRINTx instructions

[Qemu-devel] [PATCH v3 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16

Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ba3926262e..faec8084fa 100644

[Qemu-devel] [PATCH v9 03/13] s390-ccw: refactor IPL structs

ECKD DASDs have different IPL structures for CDL and LDL formats. The current Ipl1 and Ipl2 structs follow the CDL format, so we prepend "EckdCdl" to them. Boot info for LDL has been moved to a new struct: EckdLdlIpl1. Signed-off-by: Collin L. Walling Acked-by:

[Qemu-devel] [PATCH v3 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed

The helpers use the new re-factored muladd support in SoftFloat for the float16 work. Signed-off-by: Alex Bennée --- v3 - re-jigged switch statement to fall-through for unalloc - added is_fp16 bool for fpst - fixed up some long lines --- target/arm/translate-a64.c

[Qemu-devel] [PATCH v1 1/8] risugen: support @GroupName in risu files

The existing pattern support is useful but it does get a little tedious when faced with large groups of instructions. This introduces the concept of a @GroupName which can be sprinkled in the risu definition and is attached to all instructions following its definition until the next group or an

[Qemu-devel] [PATCH v3 25/31] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16

Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 remove superfluous helpers --- target/arm/helper-a64.c| 13 + target/arm/helper-a64.h| 1 + target/arm/translate-a64.c | 5 + 3 files changed, 19

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 34/67] target/arm: Implement SVE vector splice (predicated)

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/helper-sve.h| 2 ++ > target/arm/sve_helper.c| 37 + > target/arm/translate-sve.c

Re: [Qemu-devel] [PATCH v2 21/36] rbd: Pass BlockdevOptionsRbd to qemu_rbd_connect()

Am 23.02.2018 um 00:25 hat Max Reitz geschrieben: > On 2018-02-21 14:53, Kevin Wolf wrote: > > With the conversion to a QAPI options object, the function is now > > prepared to be used in a .bdrv_co_create implementation. > > > > Signed-off-by: Kevin Wolf > > -*s_snap =

Re: [Qemu-devel] [PATCH] log-for-trace.h: Split out parts of log.h used by trace.h

On Tue, Feb 13, 2018 at 02:00:29PM +, Peter Maydell wrote: > A persistent build problem we see is where a source file > accidentally omits the #include of log.h. This slips through > local developer testing because if you configure with the > default (log) trace backend trace.h will pull in

Re: [Qemu-devel] [PATCH v1 4/8] new contrib/generate_all.sh: batch risugen script

On 23 February 2018 at 16:17, Daniel P. Berrangé wrote: > On Fri, Feb 23, 2018 at 03:46:09PM +, Alex Bennée wrote: >> This is a simple script for generating all instructions in a given >> RISU file. You can split up the batch size by passing a -n N command >> line

Re: [Qemu-devel] [PATCH v8 09/21] null: Switch to .bdrv_co_block_status()

On 02/14/2018 06:05 AM, Kevin Wolf wrote: +static int coroutine_fn null_co_block_status(BlockDriverState *bs, if (s->read_zeroes) { -return BDRV_BLOCK_OFFSET_VALID | start | BDRV_BLOCK_ZERO; -} else { -return BDRV_BLOCK_OFFSET_VALID | start; +ret |=

[Qemu-devel] [PATCH v6 5/5] usb-mtp: Advertise SendObjectInfo for write support

This patch implements a dummy ObjectInfo structure so that it's easy to typecast the incoming data. If the metadata is valid, write_pending is set. Also, the incoming filename is utf-16, so, instead of depending on external libraries, just implement a simple function to get the filename

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 30/67] target/arm: Implement SVE compress active elements

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/helper-sve.h| 3 +++ > target/arm/sve_helper.c| 34 ++ > target/arm/translate-sve.c |

[Qemu-devel] [PATCH 5/5] ide: introduce ide_transfer_start_norecurse

For the case where the end_transfer_func is also the caller of ide_transfer_start, the mutual recursion can lead to unlimited stack usage. Introduce a new version that can be used to change tail recursion into a loop, and use it in trace_ide_atapi_cmd_reply_end. Signed-off-by: Paolo Bonzini

[Qemu-devel] [PATCH v3 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit

Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8c839faa8f..267a9d7e2f 100644 ---

[Qemu-devel] [PATCH v3 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)

This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Signed-off-by: Alex Bennée Reviewed-by: Richard

[Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions

Now that the softfloat re-factoring has been merged I re-based this directly from master. Alternatively you can grab the full tree from: https://github.com/stsquad/qemu/tree/arm-fp16-v3 I've tested with the following RISU test binaries:

[Qemu-devel] [PATCH v3 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16

This covers the encoding group: Advanced SIMD scalar three same FP16 As all the helpers are already there it is simply a case of calling the existing helpers in the scalar context. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes v3 - check for FP16 feature

[Qemu-devel] [PATCH v3 17/31] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16

This adds the full range of half-precision floating point to integral instructions. Signed-off-by: Alex Bennée --- v3 - fix re-base conflicts - move comment to previous commit - don't double test is_scalar in unallocated checks --- target/arm/helper-a64.c| 22

[Qemu-devel] [PATCH v3 29/31] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise

I only needed to do a little light re-factoring to support the half-precision helpers. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 80 +++--- 1 file

[Qemu-devel] [PATCH v3 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16

Much like recpe the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final

[Qemu-devel] [PATCH v9 05/13] s390-ccw: move auxiliary IPL data to separate location

The s390-ccw firmware needs some information in support of the boot process which is not available on the native machine. Examples are the netboot firmware load address and now the boot menu parameters. While storing that data in unused fields of the IPL parameter block works, that approach could

[Qemu-devel] [PATCH v9 00/13] Interactive Boot Menu for DASD and SCSI Guests on s390x

--- [v9] --- - only set boot menu opts if a bootindex was specified on cmd - Menus for guests with an IPL device that chooses to use the SCSI scheme are only enabled explicitly for -boot menu=on options (i.e. it will appropriately and cleanly ignore the zipl flag) --- [Summary] ---

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 31/67] target/arm: Implement SVE conditionally broadcast/extract element

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/helper-sve.h| 2 + > target/arm/sve_helper.c| 11 ++ > target/arm/translate-sve.c | 299 >

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 32/67] target/arm: Implement SVE copy to vector (predicated)

On 17 February 2018 at 18:22, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/translate-sve.c | 13 + > target/arm/sve.decode | 6 ++ > 2 files changed, 19 insertions(+) > > diff

[Qemu-devel] [PATCH v9 12/13] s390-ccw: use zipl values when no boot menu options are present

If no boot menu options are present, then flag the boot menu to use the zipl options that were set in the zipl configuration file (and stored on disk by zipl). These options are found at some offset prior to the start of the zipl boot menu banner. The zipl timeout value is limited to a 16-bit

[Qemu-devel] [PATCH v3 19/31] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16

I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Signed-off-by: Alex Bennée --- v3 - use size directly wuth read/write_vec_element - drop unneeded break - WIP: mess with calculating maxpasses ---

[Qemu-devel] [PATCH v2] tcg: Add choose_vector_size

This unifies 5 copies of checks for supported vector size, and in the process fixes a missing check in tcg_gen_gvec_2s. This lead to an assertion failure for 64-bit vector multiply, which is not available in the AVX instruction set. Suggested-by: Peter Maydell

Re: [Qemu-devel] [PATCH v4 4/7] qdev: add hotpluggable to DeviceState

On Fri, 23 Feb 2018 09:53:22 +0100 Gerd Hoffmann wrote: > Hi, > > > > What type of device is only sometimes hotpluggable ? > > > The commit message says "display devices" and "consoles", > > > but I would expect those to both be types of device which > > > have a class

<    1   2   3   4   >