[This is for New World Machines: there is a follow-up patch for Old World
Machines]
This patchset is a combination of uninorth fixes/cleanup with the final aim
of removing the remaining custom init functions and switching IRQ arrays over
to qdev GPIOs.
The first couple of patches apply some styl
After QOMification this is clearly no longer needed (and possibly hasn't been
for some time).
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac_newworld.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 1eba79d54b..3410bb13ad 100644
--- a/hw/pp
Commit 593c181160: "PPC: Newworld: Add second uninorth control register set"
added a second set of uninorth registers at 0xf300.
Testing MacOS 9.2 to MacOS X 10.4 reveals no accesses to this address and I
can't find any reference to it in Apple's Core99.cpp source so I'm assuming
that this was
This is in preparation for moving the PCI bus wiring inside the uninorth
host bridge devices. In the future it will be possible to remove this once the
PICs have been switched to use qdev GPIOs.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 25 +++--
in
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 79 --
1 file changed, 32 insertions(+), 47 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 710818e355..1d4d3f5705 100644
--- a/hw/pci-host/uninorth.c
+++
Somewhere in the history of time, the initialisation of the PCI buses for the
AGP and PCI host bridges got mixed up in that the PCI host bridge was
creating an instance of the AGP PCI bus, and the AGP PCI bus was missing.
Swap the PCI host bridge over to use the correct PCI bus (including setting
Whilst we are here, rename the memory regions to better reflect whether they
belong to either a PCI or an AGP bus.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/hw/pci-host/uninorth.c
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 1f6752c294..ccde332fa9 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 22 +--
include/hw/pci-host/uninorth.h | 49 ++
2 files changed, 50 insertions(+), 21 deletions(-)
create mode 100644 include/hw/pci-host/uninorth.h
diff --git a/hw/pci-h
Instead wire up the PCI/AGP host bridges in mac_newworld.c. Now this is complete
it is possible to move the initialisation of the PCI hole alias into
pci_unin_main_init().
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 46 +-
hw/ppc/mac_n
This is in preparation for moving the device wiring into the New World machine.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 16
hw/ppc/mac.h | 10 ++
hw/ppc/mac_newworld.c | 10 --
3 files changed, 22 insertions(+), 14 deletions(-)
di
Instead wire up the PCI/AGP host bridges in mac_newworld.c. Now this is complete
it is possible to move the initialisation of the PCI hole alias into
pci_u3_agp_init().
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 30 +-
hw/ppc/mac_newworld.c | 13 +++
Introduce constants for the pre-defined New World IRQs to help keep things
readable.
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac.h | 8
hw/ppc/mac_newworld.c | 29 +++--
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/mac.h b/
Since the IO address space is fixed to use the standard system IO address
space then we can also use the opportunity to remove the address_space_io
parameter from pci_pmac_init() and pci_pmac_u3_init().
Note we also move the default mac99 PCI bus to the end of the initialisation
list so that it be
The existing UNINState actually represents the PCI/AGP host bridge stage so
rename it accordingly.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 32
hw/ppc/mac.h | 8
hw/ppc/mac_newworld.c | 2 +-
inclu
Do this for both the uninorth main and uninorth u3 AGP buses, using the main
PCI bus for each machine (this ensures the IO addresses still match those
used by OpenBIOS).
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 14 ++
hw/ppc/mac_newworld.c | 12 ++
Pointless indirection. Other ports use EM_ constants directly.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 2 +-
hw/riscv/virt.c | 2 +-
target/riscv/cpu.h | 1 -
5 files changed, 4 insertions(
This is the series of spec conformance bug fixes and code cleanups.
We would like to get this series in after our core changes in v8.2.
- Implements WARL behavior for CSRs that don't support writes
- Improves specification conformance of the page table walker
- Change access checks from ternary
Since the macio device has a link to the PIC device, we can now wire up the
IRQs directly via qdev GPIOs rather than having to use an intermediate array.
Signed-off-by: Mark Cave-Ayland
---
hw/misc/macio/macio.c | 37 ++---
hw/ppc/mac_newworld.c |
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index dd3e417..f79716a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_hel
Another case of replaceing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 4 ++--
include/hw/riscv/virt.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
Now that the OpenPIC is wired up via the board, we can now remove our temporary
PIC qdev pointer property and replace it with an object link instead.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 73 +-
hw/ppc/mac_newworld.c
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7c4482b..f47fc9c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,8 +24,8 @@
#de
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 7 +--
hw/riscv/sifive_u.c
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unne
Commit 2019ba0a0197 ("block: Add AioContextNotifier functions to BB")
added blk_add/remove_aio_context_notifier() and implemented them by
passing through the bdrv_*() equivalent.
This doesn't work across bdrv_append(), which detaches child->bs and
re-attaches it to a new BlockDriverState. When
bl
The sifive_u machine already marks its ROM readonly. This fixes
the remaining boards.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 9 +
hw/riscv/spike.c | 18 ++
hw/riscv/virt.c | 7 ---
include/hw/riscv
Commit 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" added a TODO
which was to convert the uninorth registers hack to a proper device. Move
these registers to a new uninorth device, removing the old hacks from
mac_newworld.c.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/trace-events
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d22f184..dcb697f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@
Remove a potential buffer overflow (not seen in practice).
Perhaps cpu_physical_memory_write already has bound checks.
This change however makes space for the maximum device tree
size and adds an explicit bounds check and error message.
It doesn't trigger, but it may help in the future if the
devic
After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/helper.c | 2 +-
1 file changed, 1 insertio
create_fdt sets the fdt variable on RISCVVirtState and this is
used to access the fdt. This reverts a change introduced in
https://github.com/riscv/riscv-qemu/pull/109 which introduced
a redundant return value, overlooking the RISCVVirtState
structure member that made create_fdt inconsistent with t
>From reading other code that accesses memory regions directly,
it appears that the rcu_read_lock needs to be held. Note: the
original code for accessing RAM directly was added because
there is no other way to use atomic_cmpxchg easily.
Signed-off-by: Michael Clark
Signed-off-by: Stefan O'Rear
S
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_clint.c | 9 +++--
hw/riscv/sifive_u.c | 6 --
hw/riscv/spike.c
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_clint.c | 9 +++--
hw/riscv/sifive_u.c | 6 --
hw/riscv/spike.c
- Inline PTE_TABLE check for better readability
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Change access checks from ternary operator to if statements
- Improves page
Another case of replaceing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 4 ++--
include/hw/riscv/virt.h | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index 179b6cf..ed9d1db 100644
--- a/include/hw/r
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a402856..0055439 100644
---
The sifive_u machine already marks its ROM readonly. This fixes
the remaining boards.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 9 +
hw/riscv/spike.c | 18 ++
hw/riscv/virt.c | 7 ---
include/hw/riscv
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 14 ++
1 file ch
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 39 ---
1
- Inline PTE_TABLE check for better readability
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Change access checks from ternary operator to if statements
- Improves page
The blockdev-snapshot-sync command uses bdrv_append() to update all parents to
point at the external snapshot node. This breaks BlockBackend's
blk_add/remove_aio_context_notifier(), which doesn't expect a BDS change.
Patch 1 fixes this by tracking AioContext notifiers in BlockBackend.
See the te
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
defines the canonical order for extensions in the ISA string. It is
silent on the position of the E extension however E is a substitute
for I so it must come early in the extension list order. A comment
is added to state E and I
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
defines the canonical order for extensions in the ISA string. It is
silent on the position of the E extension however E is a substitute
for I so it must come early in the extension list order. A comment
is added to state E and I
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d22f184..dcb697f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@
Pointless indirection. Other ports use EM_ constants directly.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 2 +-
hw/riscv/virt.c | 2 +-
target/riscv/cpu.h | 1 -
5 files changed, 4 insertions(
This test case adds an NBD server export and then invokes
blockdev-snapshot-sync, which changes the BlockDriverState node that the
NBD server's BlockBackend points to. This is an interesting scenario to
test and exercises the code path fixed by the previous commit.
Signed-off-by: Stefan Hajnoczi
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.
It seems the RISC-V WARL behaviour is preferred to having to
bear trap overhead, versus simply reading back the value and
checking if the write took (saves hundreds of cycle
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 14 ++
1 file ch
Hello Thomas,
thanks for report but I at this time I am and
can be some time in condition which does not allow
me to access e-mail and normal work
On Tuesday 06 of March 2018 16:29:19 Thomas Huth wrote:
> On 14.01.2018 21:14, p...@cmp.felk.cvut.cz wrote:
> > From: Pavel Pisa
> >
> > Signed-off-b
On 06/03/18 20:59, no-re...@patchew.org wrote:
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180306203103.25563-1-mark.cave-ayl...@ilande.co.uk
Subject: [Qemu-devel] [PATCH 00/19] uninorth fixes/mac_newworld board wi
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unne
This is essentially dead-code elimination. Support for more
local interrupts will be added in a future revision, as they
will be defined in a future version of the Privileged ISA
specification.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 1 -
target
Remove a potential buffer overflow (not seen in practice).
Perhaps cpu_physical_memory_write already has bound checks.
This change however makes space for the maximum device tree
size and adds an explicit bounds check and error message.
It doesn't trigger, but it may help in the future if the
devic
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180306203103.25563-1-mark.cave-ayl...@ilande.co.uk
Subject: [Qemu-devel] [PATCH 00/19] uninorth fixes/mac_newworld board wiring
improvements
=== TEST SCRIPT BEGIN ===
#!/b
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 39 ---
1
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a402856..0055439 100644
---
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index 179b6cf..ed9d1db 100644
--- a/include/hw/r
On Mon, Mar 05, 2018 at 07:50:23AM -0800, Andrey Smirnov wrote:
> On Mon, Mar 5, 2018 at 7:31 AM, Peter Maydell
> wrote:
> > On 5 March 2018 at 06:12, Andrey Smirnov wrote:
> >> RESEND due to botched original v7 submission (patch 1/3 broken)
> >>
> >> Hi everyone,
> >>
> >> This v7 of the patch
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 7 +--
hw/riscv/sifive_u.c
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index dd3e417..f79716a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_hel
Followup on #1: The relevant upstream commit is 4c8777892e80b ("ARM:
dts: imx6qdl-sabrelite: remove erratum ERR006687 workaround").
Test results with various kernel versions:
4.14+: Both versions of qemu (as-is and interrupts reverted) work fine
4.9.y: Requires cherry-pick of 4c8777892e80b for bot
>From reading other code that accesses memory regions directly,
it appears that the rcu_read_lock needs to be held. Note: the
original code for accessing RAM directly was added because
there is no other way to use atomic_cmpxchg easily.
Signed-off-by: Michael Clark
Signed-off-by: Stefan O'Rear
S
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7c4482b..f47fc9c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,8 +24,8 @@
#de
After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/helper.c | 2 +-
1 file changed, 1 insertio
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20180305211928.466-1-f4...@amsat.org
Subject: [Qemu-devel] [RFC PATCH v2 00/22] remove i38
These fields are marked WARL in the specification so illegal
writes are silently dropped.
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/op_help
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.
It seems the RISC-V WARL behaviour is preferred to having to
bear trap overhead, versus simply reading back the value and
checking if the write took (saves hundreds of cycle
Le 06/03/2018 à 20:34, Max Filippov a écrit :
> In linux-user QEMU that runs for a target with TARGET_ABI_BITS bigger
> than L1_MAP_ADDR_SPACE_BITS an assertion in page_set_flags fires when
> mmap, munmap, mprotect, mremap or shmat is called for an address outside
> the guest address space. mmap an
On 02/05/2018 03:22 PM, Max Reitz wrote:
> This series implements .bdrv_refresh_filename() for the ssh block
> driver, along with an appropriate .bdrv_dirname() so we don't chop off
> query strings for backing files with relative filenames.
>
> This series depends on my “block: Fix some filename
"4.14+: Both versions of qemu (as-is and interrupts reverted) work fine"
Hm. I really wonder how it can be possible that Linux works with the
interrupt vectors reversed, though to be fair I have not looked at the
Linux i.MX6 ENET driver code. I suppose it's possible that the driver is
binding the
Instead wire up heathrow to the CPU and grackle PCI host using qdev GPIOs.
Signed-off-by: Mark Cave-Ayland
---
hw/intc/heathrow_pic.c | 23 +--
hw/ppc/mac.h | 4
hw/ppc/mac_oldworld.c | 20
include/hw/intc/heathrow
Since the macio device has a link to the PIC device, we can now wire up the
IRQs directly via qdev GPIOs rather than having to use an intermediate array.
Signed-off-by: Mark Cave-Ayland
---
hw/misc/macio/macio.c | 37 ++---
hw/ppc/mac_oldworld.c |
Instead wire up the grackle device inside the Mac Old World machine.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/grackle.c | 28 +---
hw/ppc/mac.h | 3 ---
hw/ppc/mac_oldworld.c | 21 ++---
3 files changed, 19 insertions(+), 33 deletions(-)
[This is for Old World Machines: there is a corresponding patch for New World
Machines]
This patchset is a combination of heathrow/grackle/mac_oldworld cleanup with
the final
aim of removing the remaining custom init functions and switching IRQ arrays
over
to qdev GPIOs.
Patch 1 removes the he
This is the first step towards removing the old-style pci_grackle_init()
function. Following on from the previous commit we can now pass the heathrow
device as an object link and wire up the heathrow IRQs via qdev GPIOs.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/grackle.c | 96
Introduce constants for the pre-defined Old World IRQs to help keep things
readable.
Signed-off-by: Mark Cave-Ayland
---
hw/ppc/mac.h | 8
hw/ppc/mac_oldworld.c | 27 ++-
2 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/mac.h b/hw
This simplifies the Old World machine to simply mapping the ISA memory region
into the main address space.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/grackle.c | 7 ++-
hw/ppc/mac_oldworld.c | 9 +++--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/pci-host/grackl
On 03/06/2018 05:30 PM, Mark Cave-Ayland wrote:
> This makes sure we keep patchew/checkpatch happy during the remainder of this
> patchset.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/uninorth.c | 29 +++--
> 1 file chang
On 03/06/2018 05:30 PM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/pci-host/uninorth.c | 22 +--
> include/hw/pci-host/uninorth.h | 49
> ++
> 2 files changed, 50 insertions(+), 21 deletions(-)
> create mo
On 03/06/2018 05:31 PM, Mark Cave-Ayland wrote:
> The existing UNINState actually represents the PCI/AGP host bridge stage so
> rename it accordingly.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/pci-host/uninorth.c | 32 --
On 03/06/2018 05:43 PM, Michael Clark wrote:
> The RISC-V device-tree code has a number of hard-coded
> constants and this change moves them into header enums.
>
> Signed-off-by: Michael Clark
> Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/riscv/sifive_clint.c
On 03/06/2018 05:43 PM, Michael Clark wrote:
> When load_elf is called with NULL as an argument to the
> address translate callback, it does an identity translation.
> This commit removes the redundant identity_translate callback.
>
> Signed-off-by: Michael Clark
> Signed-off-by: Palmer Dabbelt
On Wed, Mar 7, 2018 at 9:43 AM, Michael Clark wrote:
> This is the series of spec conformance bug fixes and code cleanups.
> We would like to get this series in after our core changes in v8.2.
>
> - Implements WARL behavior for CSRs that don't support writes
> - Improves specification conformance
On 03/06/2018 05:43 PM, Michael Clark wrote:
> This was added to help debug issues using -d in_asm. It is
> useful to see the instruction bytes, as one can detect if
> one is trying to execute ASCII or device-tree magic.
clean :)
>
> Signed-off-by: Michael Clark
> Signed-off-by: Palmer Dabbelt
On 03/06/2018 05:43 PM, Michael Clark wrote:
> Signed-off-by: Michael Clark
> Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/riscv/op_helper.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/
#3: Correct, Linux version 4.14 and older registers two interrupt lines,
both the correct and the wrong one. With qemu version, the kernel
receives interrupts on irq 151, with the other on 150. So, yes, I guess
it works by accident. My question is what to do with older (pre-4.14)
kernels. Presumabl
On 03/06/2018 01:49 PM, Paolo Bonzini wrote:
> Unify half a dozen copies of very similar code (the only difference being
> whether comparisons were case-sensitive) and use it also in Tricore,
> which did not do any sorting of CPU model names.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Philipp
On 03/06/2018 01:49 PM, Paolo Bonzini wrote:
> Remove the hard-coded list of PCI NIC names; instead, fill an array
> using all PCI devices listed under DEVICE_CATEGORY_NETWORK. Keep
> the old shortcut "virtio" for virtio-net-pci.
>
> Suggested-by: Thomas Huth
> Cc: Jason Wang
> Signed-off-by: Pa
On 03/06/2018 02:09 PM, Marc-André Lureau wrote:
> Spotted thanks to ASAN:
> QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 tests/migration-test -p
> /x86_64/migration/bad_dest
>
> ==30302==ERROR: LeakSanitizer: detected memory leaks
>
> Direct leak of 48 byte(s) in 1 object(s) allocated fr
On 03/05/2018 11:43 PM, Fam Zheng wrote:
> Reported-by: Alberto Garcia
> Signed-off-by: Fam Zheng
Reviewed-by: Philippe Mathieu-Daudé
> ---
> README | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/README b/README
> index 7833b97365..49a9fd09cd 100644
> --- a/README
>
On Tue, Mar 6, 2018 at 1:40 PM, Laurent Vivier wrote:
> Le 06/03/2018 à 20:34, Max Filippov a écrit :
>> In linux-user QEMU that runs for a target with TARGET_ABI_BITS bigger
>> than L1_MAP_ADDR_SPACE_BITS an assertion in page_set_flags fires when
>> mmap, munmap, mprotect, mremap or shmat is call
An exit function was mistakenly left here but it's not needed because
the PCI bars are organised differently in this device. Calling this
exit function during device_del was causing an abort with
memory_region_del_subregion: `Assertion subregion->container == mr' failed.
Reported-by: Thomas Huth
On Tue, 6 Mar 2018, Thomas Huth wrote:
On 11.01.2018 05:59, David Gibson wrote:
From: BALATON Zoltan
This is a common generic PCI SATA controller that is also used in PCs
but more importantly guests running on the Sam460ex board prefer this
card and have a driver for it (unlike for other SATA
On Tue, Mar 6, 2018 at 2:40 PM, Cornelia Huck wrote:
> On Tue, 6 Mar 2018 10:07:21 +
> Nia Alarie wrote:
>
>> Allows a branch to be removed - this function always returns 0.
>>
>> Signed-off-by: Nia Alarie
>> Reviewed-by: Christian Borntraeger
>> ---
>> hw/s390x/virtio-ccw.c | 6 +++---
>>
On Tue, 6 Mar 2018, Mark Cave-Ayland wrote:
Whilst we are here, rename the memory regions to better reflect whether they
belong to either a PCI or an AGP bus.
Signed-off-by: Mark Cave-Ayland
---
hw/pci-host/uninorth.c | 28 ++--
1 file changed, 18 insertions(+), 10 deleti
On Wed, Mar 07, 2018 at 12:07:18 +1300, Michael Clark wrote:
> BTW Apologies for the duplicate emails. I'm still getting to grips with the
> git-sendemail workflow and was using a sed script to Add Cc's which munged
> the headers as it didn't take into account Subject lines flowing to two
> lines.
On Wed, Mar 7, 2018 at 12:47 PM, Emilio G. Cota wrote:
> On Wed, Mar 07, 2018 at 12:07:18 +1300, Michael Clark wrote:
> > BTW Apologies for the duplicate emails. I'm still getting to grips with
> the
> > git-sendemail workflow and was using a sed script to Add Cc's which
> munged
> > the headers
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