Re: [Qemu-devel] [Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size

I think this patch is slightly incorrect. If the PMP region is valid for the size of the access, but not the rest of the page then a few lines down in this function the entire page should not be placed into the TLB. Instead only the portion of the page that passed the access check should be

Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes

On 6/27/19 7:51 PM, Richard Henderson wrote: > Please try the following patch on top and if it works I'll split it back into > the patch set properly. Dangit. I generated the patch on the wrong machine. Let's try that again. r~ diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c

Re: [Qemu-devel] [PATCH v14 0/5] linux-user: A set of miscellaneous patches

Patchew URL: https://patchew.org/QEMU/1561649510-21183-1-git-send-email-aleksandar.marko...@rt-rk.com/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 1561649510-21183-1-git-send-email-aleksandar.marko...@rt-rk.com Type: series

Re: [Qemu-devel] [PATCH v13 0/5] linux-user: A set of miscellaneous patches

Patchew URL: https://patchew.org/QEMU/1561648298-18100-1-git-send-email-aleksandar.marko...@rt-rk.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH v13 0/5] linux-user: A set of miscellaneous patches Message-id:

Re: [Qemu-devel] balloon config change seems to break live migration from 3.0.1 to 4.0

Patchew URL: https://patchew.org/QEMU/20190627131252.ga14...@olga.proxmox.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20190627131252.ga14...@olga.proxmox.com Subject: [Qemu-devel] balloon config change seems to

Re: [Qemu-devel] [Qemu-block] [PATCH v2] block/rbd: implement .bdrv_get_allocated_file_size callback

On 6/27/19 3:43 PM, Jason Dillaman wrote: > On Thu, Jun 27, 2019 at 1:24 PM John Snow wrote: >> >> >> >> On 6/27/19 4:48 AM, Stefano Garzarella wrote: >>> On Wed, Jun 26, 2019 at 05:04:25PM -0400, John Snow wrote: It looks like this has hit a 30 day expiration without any reviews or

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

On Wed, Jun 26, 2019 at 1:25 AM Palmer Dabbelt wrote: > > On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote: > > On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote: > >> > >> I just did some testing on a HiFive Unleashed board and can confirm what > >> you are saying. The

[Qemu-devel] [PATCH v5 07/28] hw/block/pflash_cfi02: Simplify a statement using fall through

Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMD: Extracted from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 6 +++--- 1 file

[Qemu-devel] [PATCH v5 19/28] hw/block/pflash_cfi02: Extract pflash_regions_count()

Extract the pflash_regions_count() function, the code will be easier to review. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index

[Qemu-devel] [PATCH v5 09/28] hw/block/pflash_cfi02: Use the ldst API in pflash_read()

The load/store API eases code review. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMD: Extracted from bigger patch, simplified tracing] Signed-off-by: Philippe

[Qemu-devel] [PATCH v5 15/28] hw/block/pflash_cfi02: Document the current CFI values

Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu> [PMD: Extracted from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git

Re: [Qemu-devel] [RFC PATCH] tests/acceptance: Handle machine type for ARM target

On 06/21/2019 07:07 PM, Cleber Rosa wrote: On Fri, Jun 21, 2019 at 11:38:06AM -0400, Wainer dos Santos Moschetta wrote: Hi all, I'm still unsure this is the best solution. I tend to think that any arch-independent test case (i.e. not tagged 'arch') should be skipped on all arches except for

[Qemu-devel] [RFC PATCH v2 3/3] QEMUMachine: Don't suppress stack traces on close

We do need to run cleanup, but we should re-raise the error. Rename _post_shutdown to _shutdown_cleanup, then use the _post_shutdown name for the routine that will always run at the conclusion of the shutdown() method. Signed-off-by: John Snow --- python/qemu/machine.py | 41

[Qemu-devel] [RFC PATCH v2 0/3] python: refactor qemu/__init__.py

There's a lot of code hiding in what is ostensibly a package configuration file. Let's break that out into something more visible. V2: - Retain python 2.7+ compatibility :( - Refactor shutdown a little more aggressively John Snow (3): python/qemu: split QEMUMachine out from underneath

Re: [Qemu-devel] [PATCH v5 02/28] hw/block/pflash: Simplify trace_pflash_io_read/write()

Hi Phil, Thanks for pushing this forward! I'll try to get to the rest of these early next week. > On Jun 27, 2019, at 16:26, Philippe Mathieu-Daudé wrote: > > Call the read() trace function after the value is set, so we can > log the returned value. > Rename the I/O trace functions with

[Qemu-devel] [PATCH v5 01/28] tests/pflash-cfi02: Add test for supported CFI commands

From: Stephen Checkoway Test the AMD command set for parallel flash chips. This test uses an ARM musicpal board with a pflash drive to test the following list of currently-supported commands. - Autoselect - CFI - Sector erase - Chip erase - Program - Unlock bypass - Reset Signed-off-by: Stephen

[Qemu-devel] [PATCH v5 16/28] hw/block/pflash_cfi02: Hold the PRI table offset in a variable

Manufacturers are allowed to move the PRI table, this is why the offset is queryable via fixed offsets 0x15/0x16. Add a variable to hold the offset, so it will be easier to later move the PRI table. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 31

[Qemu-devel] [PATCH v5 12/28] hw/block/pflash_cfi02: Fix command address comparison

From: Stephen Checkoway Most AMD commands only examine 11 bits of the address. This masks the addresses used in the comparison to 11 bits. The exceptions are word or sector addresses which use offset directly rather than the shifted offset, boff. Signed-off-by: Stephen Checkoway Acked-by:

[Qemu-devel] [PATCH v5 24/28] hw/block/pflash_cfi02: Implement erase suspend/resume

From: Stephen Checkoway During a sector erase (but not a chip erase), the embeded erase program can be suspended. Once suspended, the sectors not selected for erasure may be read and programmed. Autoselect mode is allowed during erase suspend mode. Presumably, CFI queries are similarly allowed

[Qemu-devel] [PATCH v5 25/28] hw/block/pflash_cfi02: Use chip erase time specified in the CFI table

From: Stephen Checkoway When erasing the chip, use the typical time specified in the CFI table rather than arbitrarily selecting 5 seconds. Since the currently unconfigurable value set in the table is 12, this means a chip erase takes 4096 ms so this isn't a big change in behavior.

[Qemu-devel] [RFC PATCH v2 1/3] python/qemu: split QEMUMachine out from underneath __init__.py

It's not obvious that something named __init__.py actually houses important code that isn't relevant to python packaging glue. Move the QEMUMachine and related error classes out into their own module. Adjust users to the new import location. Signed-off-by: John Snow --- python/qemu/__init__.py

Re: [Qemu-devel] [RFC PATCH v2 0/3] python: refactor qemu/__init__.py

I didn't actually mean to retain the RFC tag, but oh well. On 6/27/19 5:28 PM, John Snow wrote: > There's a lot of code hiding in what is ostensibly a package > configuration file. Let's break that out into something more visible. > > V2: > - Retain python 2.7+ compatibility :( > - Refactor

[Qemu-devel] [RFC PATCH v2 2/3] machine.py: minor delinting

Since we're out in a new module, do a quick cursory pass of some of the more obvious style issues. Signed-off-by: John Snow --- python/qemu/machine.py | 33 ++--- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/python/qemu/machine.py

[Qemu-devel] [PATCH v13 0/5] linux-user: A set of miscellaneous patches

From: Aleksandar Markovic This is a collection of misc patches for Linux user that I recently accumulated from variuous sources. All of them originate from problems observed on mips target. However, most of these changes actually affect and fix linux-user problems on multiple targets. There are

[Qemu-devel] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e

Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(), where a pair of recently added MemoryRegion instances would not be freed if there were errors elsewhere in the function. The fix here is to simply not use dynamic allocation for these instances: there's always one of each in

[Qemu-devel] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware

From: Alistair Francis If the user hasn't specified a firmware to load (with -bios) or specified no bios (with -bios none) then load OpenSBI by default. This allows users to boot a RISC-V kernel with just -kernel. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng

[Qemu-devel] [PULL 21/34] RISC-V: Add support for the Zifencei extension

fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h

[Qemu-devel] [PULL 31/34] hw/riscv: Add support for loading a firmware

From: Alistair Francis Add support for loading a firmware file for the virt machine and the SiFive U. This can be run with the following command: qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng

Re: [Qemu-devel] [PATCH v4 1/5] 9p: unsigned type for type, version, path

On Wed, 26 Jun 2019 20:25:55 +0200 Christian Schoenebeck via Qemu-devel wrote: > There is no need for signedness on these QID fields for 9p. > > Signed-off-by: Antonios Motakis You should mention here the changes you made on top of Antonios original patch. Something like: [CS: - also convert

Re: [Qemu-devel] [RFC] Re-evaluating subcluster allocation for qcow2 images

On 6/27/19 6:38 PM, Alberto Garcia wrote: > On Thu 27 Jun 2019 04:19:25 PM CEST, Denis Lunev wrote: > >> Right now QCOW2 is not very efficient with default cluster size (64k) >> for fast performance with big disks. Nowadays ppl uses really BIG >> images and 1-2-3-8 Tb disks are really common.

Re: [Qemu-devel] [PATCH v2 07/14] target/arm/cpu64: max cpu: Introduce sve properties

On 6/21/19 6:34 PM, Andrew Jones wrote: > +/* > + * In sve_vq_map each set bit is a supported vector length of > + * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector > + * length in quadwords. We need a map size twice the maximum > + * quadword length though

Re: [Qemu-devel] [PATCH v23 1/7] target/avr: Add outward facing interfaces and core CPU logic

Hi Igor, if I run `make check` it fails with qemu-system-rx: unable to find CPU model 'rx62n' or qemu-system-avr: unable to find CPU model 'avr6' On Thu, Jun 27, 2019 at 2:28 PM Igor Mammedov wrote: > On Thu, 27 Jun 2019 08:27:44 +0300 > Michael Rolnik wrote: > > > From: Sarah Harris > > > >

Re: [Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks

On 6/27/19 2:18 PM, Hesham Almatary wrote: > @@ -392,19 +392,27 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, > int size, > int prot; > bool pmp_violation = false; > int ret = TRANSLATE_FAIL; > +int mode = mmu_idx; > > qemu_log_mask(CPU_LOG_MMU, "%s ad %"

Re: [Qemu-devel] [PATCH v14 5/5] linux-user: Handle EXCP_FPE properly for MIPS

Le 27/06/2019 à 17:31, Aleksandar Markovic a écrit : > From: Aleksandar Markovic > > Handle EXCP_FPE properly for MIPS in cpu loop. > > Note that a vast majority of FP instructions are not affected by > the absence of the code in this patch, as they use alternative code > paths for handling

Re: [Qemu-devel] [Qemu-block] [PATCH v2] block/rbd: implement .bdrv_get_allocated_file_size callback

On Thu, Jun 27, 2019 at 1:24 PM John Snow wrote: > > > > On 6/27/19 4:48 AM, Stefano Garzarella wrote: > > On Wed, Jun 26, 2019 at 05:04:25PM -0400, John Snow wrote: > >> It looks like this has hit a 30 day expiration without any reviews or > >> being merged; do we still want this? If so, can you

[Qemu-devel] [PATCH v5 03/28] hw/block/pflash: Simplify trace_pflash_data_read/write()

Use a field width format to have a single function to log the different width accesses. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 6 ++ hw/block/pflash_cfi02.c | 6 ++ hw/block/trace-events | 6 ++ 3 files changed, 6 insertions(+), 12 deletions(-) diff

[Qemu-devel] [PATCH v5 04/28] hw/block/pflash_cfi02: Fix debug format string

Always compile the debug code to prevent format string to bitrot. Delete dead code. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMD: Extracted from bigger patch, use

[Qemu-devel] [PATCH v5 10/28] hw/block/pflash_cfi02: Extract the pflash_data_read() function

Extract the code block in a new function, remove a goto statement. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMD: Extracted from bigger patch, remove the XXX tracing

[Qemu-devel] [PATCH v5 27/28] hw/block/pflash_cfi02: Document commands

Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 40 +++- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index e9519cbae8..db9dc7d8fb 100644 --- a/hw/block/pflash_cfi02.c +++

[Qemu-devel] [PATCH v5 14/28] hw/block/pflash_cfi02: Remove pointless local variable

We can directly use pfl->total_len, remove the local 'chip_len' variable. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu> [PMD: Extracted from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 14 ++

[Qemu-devel] [PATCH v5 23/28] hw/block/pflash_cfi02: Implement multi-sector erase

From: Stephen Checkoway After two unlock cycles and a sector erase command, the AMD flash chips start a 50 us erase time out. Any additional sector erase commands add a sector to be erased and restart the 50 us timeout. During the timeout, status bit DQ3 is cleared. After the time out, DQ3 is

[Qemu-devel] [PATCH v5 22/28] hw/block/pflash_cfi02: Fix reset command not ignored during erase

From: Stephen Checkoway When the flash device is performing a chip erase, all commands are ignored. When it is performing a sector erase, only the erase suspend command is valid, which is currently not supported. In particular, the reset command should not cause the device to reset to read

Re: [Qemu-devel] [Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size

On 6/27/19 7:44 PM, Jonathan Behrens wrote: > I think this patch is slightly incorrect. If the PMP region is valid for > the size of the access, but not the rest of the page then a few lines down > in this function the entire page should not be placed into the TLB. Instead > only the portion of

Re: [Qemu-devel] [PATCH v14 0/5] linux-user: A set of miscellaneous patches

Patchew URL: https://patchew.org/QEMU/1561649510-21183-1-git-send-email-aleksandar.marko...@rt-rk.com/ Hi, This series failed build test on s390x host. Please find the details below. === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under the git checkout with # HEAD

Re: [Qemu-devel] [PATCH v13 0/5] linux-user: A set of miscellaneous patches

Patchew URL: https://patchew.org/QEMU/1561648298-18100-1-git-send-email-aleksandar.marko...@rt-rk.com/ Hi, This series failed build test on s390x host. Please find the details below. === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be invoked under the git checkout with # HEAD

[Qemu-devel] [PATCH v5 18/28] hw/block/pflash_cfi02: Implement nonuniform sector sizes

From: Stephen Checkoway Some flash chips support sectors of different sizes. For example, the AMD AM29LV160DT has 31 64 kB sectors, one 32 kB sector, two 8 kB sectors, and a 16 kB sector, in that order. The AM29LV160DB has those in the reverse order. The `num-blocks` and `sector-length`

[Qemu-devel] [PATCH v5 11/28] hw/block/pflash_cfi02: Unify the MemoryRegionOps

The pflash_read()/pflash_write() can check the device endianess via the pfl->be variable, so remove the 'int be' argument. Since the big/little MemoryRegionOps are now identical, it is pointless to declare them both. Unify them. Signed-off-by: Stephen Checkoway Message-Id:

[Qemu-devel] [PATCH v5 02/28] hw/block/pflash: Simplify trace_pflash_io_read/write()

Call the read() trace function after the value is set, so we can log the returned value. Rename the I/O trace functions with '_io_' in their name. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 5 +++-- hw/block/pflash_cfi02.c | 6 ++ hw/block/trace-events | 4 ++-- 3

[Qemu-devel] [PATCH v5 13/28] tests/pflash-cfi02: Refactor to support testing multiple configurations

Introduce the FlashConfig structure, to be able to run the same set of tests on different flash models/configurations. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu> [PMD: Extracted from bigger patch] Signed-off-by: Philippe Mathieu-Daudé ---

[Qemu-devel] [PATCH v5 06/28] hw/block/pflash_cfi02: Add helpers to manipulate the status bits

Pull out all of the code to modify the status into simple helper functions. Status handling becomes more complex once multiple chips are interleaved to produce a single device. No change in functionality is intended with this commit. Signed-off-by: Stephen Checkoway Message-Id:

Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes

On 6/27/19 7:24 PM, Mark Cave-Ayland wrote: > For the TCG_TYPE_V128 case we have ret = TCG_REG_V2 but (ret & 31) masks > off the top bit which converts this to TCG_REG_R2 and that's why > tcg_out_mem_long() starts using r2 to calculate offsets. Oh geez. Ok, I see it now. > case

Re: [Qemu-devel] [PATCH v23 1/7] target/avr: Add outward facing interfaces and core CPU logic

I meant that if I take the proposed code it fails in the mentioned way Sent from my cell phone, please ignore typos On Thu, Jun 27, 2019, 7:02 PM Michael Rolnik wrote: > Hi Igor, > > if I run `make check` it fails with > qemu-system-rx: unable to find CPU model 'rx62n' > or > qemu-system-avr:

Re: [Qemu-devel] [Qemu-arm] [RFC v2 PATCH] hw/arm/virt: makes virt a default machine type

On 06/24/2019 05:37 AM, Andrea Bolognani wrote: On Sat, 2019-06-22 at 16:58 +0100, Peter Maydell wrote: On Fri, 21 Jun 2019 at 20:04, Cleber Rosa wrote: You can consider me biased (I do consider myself), but trying to wear the hat of a user first interacting with QEMU, I would expect a

Re: [Qemu-devel] [PATCH v4 00/13] target/ppc, tcg, tcg/i386: Optimize emulation of some Altivec instructions

On Thu, Jun 27, 2019 at 12:56 PM Stefan Brankovic < stefan.branko...@rt-rk.com> wrote: > > V4: > > Addressed Richard's Henderson's suggestions. > Removed vpkpx's optimization for further investigation on graphical > distortions > it caused on OSX 10.2-4 guests. > Added opcodes for vector

[Qemu-devel] [PATCH v5 05/28] hw/block/pflash_cfi02: Add an enum to define the write cycles

No change in functionality is intended with this commit. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMD: Extracted from bigger patch] Signed-off-by: Philippe

[Qemu-devel] [PATCH v5 08/28] hw/block/pflash_cfi02: Use the ldst API in pflash_write()

The load/store API eases code review. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-3-stephen.checko...@oberlin.edu> Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMD: Extracted from bigger patch] Signed-off-by: Philippe Mathieu-Daudé ---

[Qemu-devel] [PATCH v5 20/28] hw/block/pflash_cfi02: Split if() condition

Split the if() condition check and arrange the indentation to ease the review of the next patches. No logical change. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/block/pflash_cfi02.c

[Qemu-devel] [PATCH v5 28/28] hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit

Parallel NOR flashes are limited to 16-bit bus accesses. Remove the 32-bit dead code. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index

[Qemu-devel] [PATCH v5 21/28] hw/block/pflash_cfi02: Fix CFI in autoselect mode

From: Stephen Checkoway After a flash device enters CFI mode from autoselect mode, the reset command returns the device to autoselect mode. An additional reset command is necessary to return to read array mode. Signed-off-by: Stephen Checkoway Acked-by: Thomas Huth Message-Id:

Re: [Qemu-devel] [PATCH for-4.1 00/24] Fix record/replay and add reverse debugging

Paolo, what about merging reviewed and acked patches before the soft freeze? Pavel Dovgalyuk Pavel Dovgalyuk писал 2019-06-21 11:20: GDB remote protocol supports reverse debugging of the targets. It includes 'reverse step' and 'reverse continue' operations. The first one finds the previous

Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes

On 27/06/2019 18:54, Richard Henderson wrote: > On 6/27/19 7:51 PM, Richard Henderson wrote: >> Please try the following patch on top and if it works I'll split it back into >> the patch set properly. > > Dangit. I generated the patch on the wrong machine. > Let's try that again. Yes it works!

[Qemu-devel] [PATCH v5 00/28] block/pflash_cfi02: Implement missing AMD pflash functionality

Hi, This series is based on Stephen Checkoway work (v4): https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg04595.html Stephen work is a great improvement of the actual code, however while reviewing his patches, I found them quite dense, so I started to split each logical change to be able

[Qemu-devel] [PATCH v5 17/28] hw/block/pflash_cfi02: Document 'Page Mode' operations are not supported

The 'page mode' feature entry was implicitly set as zero (not supported). Document it exists, so we won't discard it if we squeeze the CFI table. Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-6-stephen.checko...@oberlin.edu> [PMD: Extracted from bigger patch] Signed-off-by:

[Qemu-devel] [PATCH v5 26/28] hw/block/pflash_cfi02: Reduce single byte/word write delay

Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-5-stephen.checko...@oberlin.edu> [PMD: Extracted from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- TODO: Why? To respect the datasheet? Which model is this? --- hw/block/pflash_cfi02.c | 4 ++-- 1 file changed, 2

Re: [Qemu-devel] [PATCH v12 3/5] linux-user: Add support for translation of statx() syscall

Le 27/06/2019 à 15:18, Aleksandar Markovic a écrit : >> From: Laurent Vivier >> >>> @@ -10173,6 +10225,88 @@ static abi_long do_syscall1(void *cpu_env, int >>> num, abi_long > arg1, >>> ret = host_to_target_stat64(cpu_env, arg3, ); >>> return ret; >>> #endif >>> +#if

Re: [Qemu-devel] [PATCH] block/qcow: Improve error when opening qcow2 files as qcow

On 6/27/19 3:34 AM, Kevin Wolf wrote: > Am 26.06.2019 um 23:53 hat John Snow geschrieben: >> Reported-by: radmehrsae...@gmail.com >> Fixes: https://bugs.launchpad.net/bugs/1832914 >> Signed-off-by: John Snow >> --- >> block/qcow.c | 7 ++- >> 1 file changed, 6 insertions(+), 1 deletion(-) >>

Re: [Qemu-devel] [PATCH v2 1/7] iotests: allow Valgrind checking all QEMU processes

On 13/06/2019 12:44, Vladimir Sementsov-Ogievskiy wrote: > 11.06.2019 21:02, Andrey Shinkevich wrote: >> With the '-valgrind' option, let all the QEMU processes be run under >> the Valgrind tool. The Valgrind own parameters may be set with its >> environment variable VALGRIND_OPTS, e.g. >>

[Qemu-devel] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0

From: Alistair Francis Add support for the ratified RISC-V privledge spec. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_privileged.inc.c | 2 +- 2 files

[Qemu-devel] [PULL 19/34] target/riscv: Remove user version information

From: Alistair Francis Remove the user version information. This was never used and never publically exposed in a release of QEMU, so let's just remove it. In future to manage versions we can extend the extension properties to specify version. Signed-off-by: Alistair Francis Reviewed-by:

[Qemu-devel] [PULL 30/34] hw/riscv: Split out the boot functions

From: Alistair Francis Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c |

[Qemu-devel] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default

From: Alistair Francis Set the priv spec version 1.11.0 as the default and allow selecting it via the command line. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-)

[Qemu-devel] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal

From: Michael Clark Due to the design of the disassembler, the immediate is not known during decoding of the opcode; so to handle compressed encodings with reserved immediate values (non-zero), we need to add an additional check during decompression to match reserved encodings with zero

[Qemu-devel] [PULL 08/34] RISC-V: Check PMP during Page Table Walks

From: Hesham Almatary The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Suggested-by: Jonathan Behrens Signed-off-by: Hesham Almatary Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt ---

[Qemu-devel] [PULL 24/34] RISC-V: Update syscall list for 32-bit support.

From: Jim Wilson 32-bit RISC-V uses _llseek instead of lseek as syscall number 62. Update syscall list from open-embedded build, primarily because 32-bit RISC-V requires statx support. Tested with cross gcc testsuite runs for rv32 and rv64, with the pending statx patch also applied.

Re: [Qemu-devel] [PATCH v6] qemu-io: add pattern file for write command

On 19.06.2019 13:09, Vladimir Sementsov-Ogievskiy wrote: > 10.06.2019 16:21, Denis Plotnikov wrote: >> The patch allows to provide a pattern file for write >> command. There was no similar ability before. >> >> Signed-off-by: Denis Plotnikov >> --- >> v6: >> * the pattern file is read once

[Qemu-devel] [PATCH v14 2/5] linux-user: Add support for strace for statx() syscall

From: Jim Wilson All of the flags need to be conditional as old systems don't have statx support. Otherwise it works the same as other stat family syscalls. This requires the pending patch to add statx support. Tested on Ubuntu 16.04 (no host statx) and Ubuntu 19.04 (with host statx) using a

[Qemu-devel] [PULL 03/34] target/riscv: Fix PMP range boundary address bug

From: Dayeol Lee A wrong address is passed to `pmp_is_in_range` while checking if a memory access is within a PMP range. Since the ending address of the pmp range (i.e., pmp_state.addr[i].ea) is set to the last address in the range (i.e., pmp base + pmp size - 1), memory accesses containg the

[Qemu-devel] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore

From: Bin Meng At present the PLIC is instantiated to support only one hart, while the machine allows at most 4 harts to be created. When more than 1 hart is configured, PLIC needs to instantiated to support multicore, otherwise an SMP OS does not work. Signed-off-by: Bin Meng Reviewed-by:

[Qemu-devel] [PATCH v14 5/5] linux-user: Handle EXCP_FPE properly for MIPS

From: Aleksandar Markovic Handle EXCP_FPE properly for MIPS in cpu loop. Note that a vast majority of FP instructions are not affected by the absence of the code in this patch, as they use alternative code paths for handling floating point exceptions (see, for example, invocations of

[Qemu-devel] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint

From: "Wladimir J. van der Laan" The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer

Re: [Qemu-devel] [RFC] Re-evaluating subcluster allocation for qcow2 images

On Thu 27 Jun 2019 05:38:56 PM CEST, Alberto Garcia wrote: >> I would consider 64k cluster/8k subcluster as too extreme for me. I forgot to add: this 64k/8k ratio is only with my current prototype. In practice if we go with the 128-bit L2 entries we would have 64 subclusters per cluster, or 32

Re: [Qemu-devel] [PATCH v0 1/3] qcow2: introduce compression type feature

Doc & QAPI schema review only. Denis Plotnikov writes: > The patch adds some preparation parts for incompatible compression type > feature to QCOW2 header that indicates that *all* compressed clusters > must be (de)compressed using a certain compression type. > > It is implied that the

[Qemu-devel] Should configure --enable-debug add -Og to CFLAGS?

The fine manual advises: '-O0' Reduce compilation time and make debugging produce the expected results. This is the default. [...] '-Og' Optimize debugging experience. '-Og' should be the optimization level of choice for the standard edit-compile-debug cycle, offering a

Re: [Qemu-devel] [PATCH v2 07/14] target/arm/cpu64: max cpu: Introduce sve properties

On 6/27/19 5:16 PM, Dave Martin wrote: > The architecture says: > > "For all purposes other than returning the result of a direct read of > ZCR_EL1 then this field behaves as if it is set to the minimum of the > stored value and the constrained length inherited from more privileged > Exception

[Qemu-devel] [Bug 1834496] Re: Regressions on arm target with some GCC tests

** Tags added: arm testcases ** Tags removed: testcases ** Tags added: testcase -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1834496 Title: Regressions on arm target with some GCC tests Status

Re: [Qemu-devel] [PATCH v4 2/5] 9p: Treat multiple devices on one export as an error

On Wed, 26 Jun 2019 20:30:41 +0200 Christian Schoenebeck via Qemu-devel wrote: > The QID path should uniquely identify a file. However, the > inode of a file is currently used as the QID path, which > on its own only uniquely identifies wiles within a device. s/wile/files > Here we track the

Re: [Qemu-devel] [Qemu-riscv] [RFC v1 0/5] RISC-V: Add firmware loading support and default

On Fri, 2019-06-21 at 14:35 +0200, Andrea Bolognani wrote: > On Thu, 2019-06-20 at 21:43 +0300, David Abdurachmanov wrote: > > On Thu, Jun 20, 2019 at 9:18 PM Alistair Francis > > wrote: > > > OE-Core already packages OpenSBI by default, Fedora and Debian are > > > moving to OpenSBI for RISC-V

[Qemu-devel] [RFC] Re-evaluating subcluster allocation for qcow2 images

Hi all, a couple of years ago I came to the mailing list with a proposal to extend the qcow2 format to add subcluster allocation. You can read the original message (and the discussion thread that came afterwards) here: https://lists.gnu.org/archive/html/qemu-block/2017-04/msg00178.html The

[Qemu-devel] Nothing to Boot Error

Hi All, I am trying to install macOS HighSierra using qemu-system-x86_64 . I am stuck at IPXE Error that says : *Nothing to boot: No such file or directory (http://ipxe.org/2d03e13b )* *Host System : macOS Mojave* *Command : **qemu-system-x86_64 -boot d -cdrom

Re: [Qemu-devel] [PATCH v4 04/13] vfio: Add migration region initialization and finalize function

On 6/24/2019 7:30 PM, Cornelia Huck wrote: > On Thu, 20 Jun 2019 20:07:32 +0530 > Kirti Wankhede wrote: > >> - Migration functions are implemented for VFIO_DEVICE_TYPE_PCI device in this >> patch series. >> - VFIO device supports migration or not is decided based of migration region >>

[Qemu-devel] [PATCH v13 1/5] linux-user: Add support for translation of statx() syscall

From: Aleksandar Rikalo Implement support for translation of system call statx(). The implementation is based on "best effort" approach: if host is capable of executing statx(), host statx() is used. If not, the implementation includes invoking a more mature system call fstatat() on the host

[Qemu-devel] [PATCH v13 5/5] linux-user: Handle EXCP_FPE properly for MIPS

From: Aleksandar Markovic Handle EXCP_FPE properly for MIPS in cpu loop. Note that a vast majority of FP instructions are not affected by the absence of the code in this patch, as they use alternative code paths for handling floating point exceptions (see, for example, invocations of

[Qemu-devel] [PATCH v13 3/5] linux-user: Fix flock structure for MIPS O64 ABI

From: Aleksandar Markovic Only MIPS O32 and N32 have special (different than other architectures) definition of structure flock in kernel. Bring flock definition for MIPS O64 ABI to the correct state. Reported-by: Dragan Mladjenovic Signed-off-by: Aleksandar Markovic ---

[Qemu-devel] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props

From: Alistair Francis This patch allows us to enable/disable the RISC-V ISA extensions from the QEMU command line. This works with the rv32 and rv64 machines. The idea is that in the future we can now add extensions and leave them disabled by default until enabled by the user. Signed-off-by:

[Qemu-devel] [PULL 15/34] target/riscv: Add the mcountinhibit CSR

From: Alistair Francis 1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec).

[Qemu-devel] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access

From: Michael Clark This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Signed-off-by: Michael Clark [Changes by AF: - Squash two patches and rewrite commit message - Set baddr to the access address ] Signed-off-by: Alistair Francis

[Qemu-devel] [PULL 13/34] target/riscv: Restructure deprecatd CPUs

From: Alistair Francis Restructure the deprecated CPUs to make it clear in the code that these are depreated. They are already marked as deprecated in qemu-deprecated.texi. There are no functional changes. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer

[Qemu-devel] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC

From: Joel Sing This prevents a load reservation from being placed in one context/process, then being used in another, resulting in an SC succeeding incorrectly and breaking atomics. Signed-off-by: Joel Sing Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Palmer

[Qemu-devel] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

From: Hesham Almatary The current implementation returns 1 (PMP check success) if the address is in range even if the PMP entry is off. This is a bug. For example, if there is a PMP check in S-Mode which is in range, but its PMP entry is off, this will succeed, which it should not. The patch

[Qemu-devel] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size

From: Hesham Almatary The PMP check should be of the memory access size rather than TARGET_PAGE_SIZE. Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git

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