On Wed, 9 Sep 2020 21:59:18 +0300
Vladimir Sementsov-Ogievskiy wrote:
> Now bdrv_append returns status and we can drop all the local_err things
> around it.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
Reviewed-by: Greg Kurz
Just one suggestion for a follow-up below...
> block.c
On 07.09.20 20:20, Kevin Wolf wrote:
> Signed-off-by: Kevin Wolf
> ---
> tests/qemu-iotests/iotests.py | 11 +++-
> tests/qemu-iotests/307| 117 ++
> tests/qemu-iotests/307.out| 111
> tests/qemu-iotests/group |
Le 10/09/2020 à 18:19, Petunia a écrit :
> can you reproduce the bug locally or is this a client problem?
>
I didn't try but I will as you describe it clearly.
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Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
sub-struct. We're going to want id_pfr1 for an isar_features
check, and moving both at the same time avoids an odd
inconsistency.
Changes other than the ones to cpu.h and kvm64.c made
automatically with:
perl -p -i -e
Awkwardly, M-profile uses a different ID register field from
A-profile to indicate presence of 16-bit floating point arithmetic.
This patchset corrects the feature test function. In order to
use the correct test, we need to be able to ask "is this M-profile?"
in the isar_feature function, and we
Give the Cortex-M0 ID register values corresponding to its
implemented behaviour. These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation. We use the same
values that the Cortex-M3 does.
Signed-off-by: Peter Maydell
---
target/arm/cpu_tcg.c | 24
-riscv-to-apply-20200910
for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19
-0700)
This PR includes multiple fixes and features
From: Bin Meng
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
From: Bin Meng
Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.
Normally reset vector address is a
From: Bin Meng
This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
For more details about Microchip PolarFire Soc, please see:
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
From: Bin Meng
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
From: Bin Meng
Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
From: Bin Meng
At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.
Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.
Signed-off-by: Bin
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
On Wed, Sep 02, 2020 at 06:42:10PM -0400, Eduardo Habkost wrote:
> This will make the TYPE_* constants consistent with the name of
> most type checking macros we have today.
>
> Signed-off-by: Eduardo Habkost
I will drop this and send a separate patch to rename the type
checking macros instead,
On 9/10/20 9:12 PM, Eduardo Habkost wrote:
> On Thu, Sep 10, 2020 at 07:29:03AM +0200, Philippe Mathieu-Daudé wrote:
>> On 9/9/20 8:15 PM, Eduardo Habkost wrote:
>>> Hi,
>>>
>>> Thanks for the patch, and sorry for taking so long to review
>>> this. I'm finally getting to the patches that were
Rename instance and class type checkers to match the
TYPE_CHARDEV_* constant names and the QOM type name strings
("chardev-*").
Signed-off-by: Eduardo Habkost
---
chardev/char-socket.c | 68 +--
1 file changed, 34 insertions(+), 34 deletions(-)
diff
Rename instance and class type checkers to match the
TYPE_CHARDEV_* constant names and the QOM type name strings
("chardev-*").
Signed-off-by: Eduardo Habkost
---
chardev/chardev-internal.h | 2 +-
chardev/char-fe.c | 4 ++--
chardev/char-mux.c | 22 +++---
Rename instance and class type checkers to match the
TYPE_CHARDEV_* constant names and the QOM type name strings
("chardev-*").
Signed-off-by: Eduardo Habkost
---
ui/console.c | 10 +-
ui/gtk.c | 8
ui/spice-app.c | 2 +-
3 files changed, 10 insertions(+), 10
Rename instance and class type checkers to match the
TYPE_CHARDEV_* constant names and the QOM type name strings
("chardev-*").
Signed-off-by: Eduardo Habkost
---
chardev/char-ringbuf.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/chardev/char-ringbuf.c
On 9/10/20 3:24 AM, Steven Price wrote:
> It is a shame, however I suspect this is because to use those instructions you
> need to know the block size held in GMID_EL1. And at least in theory that
> could
> vary between CPUs.
Which is no different from having to read DCZID_EL0 in order to
On 9/8/20 9:29 AM, Laszlo Ersek wrote:
> Refresh the "pc-bios/README" file with edk2 and OpenSSL release info,
> matching the edk2-stable202008 firmware images added in the previous
> patch.
>
> Cc: Philippe Mathieu-Daudé
> Ref: https://bugs.launchpad.net/qemu/+bug/1852196
> Signed-off-by:
On Thu, 10 Sep 2020 at 16:06, Derrick McKee wrote:
>
> Hi,
>
> As of commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a compiled with the
> default configuration, softmmu-aarch64 issues an illegal instruction fault
> when executing a memory tag instruction. Below is a minimal code example
> that
Thanks for the quick response!
I tried the whole day to get the PKGBUILD working...
Your patch doesnt fix the issue though - see attached log
** Attachment added: "log.txt"
https://bugs.launchpad.net/qemu/+bug/1895053/+attachment/5409429/+files/log.txt
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On Wed, 9 Sep 2020 21:59:21 +0300
Vladimir Sementsov-Ogievskiy wrote:
> bdrv_set_backing_hd now returns status, let's use it.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
Reviewed-by: Greg Kurz
> block.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff
* Chuan Zheng (zhengch...@huawei.com) wrote:
> Compare page hash results for recorded sampled page.
>
> Signed-off-by: Chuan Zheng
> Signed-off-by: YanYing Zhuang
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/dirtyrate.c | 63
> +++
>
On 01.09.20 14:51, Peter Lieven wrote:
> in case of large continous areas that share the same allocation status
> it happens that the value of s->sector_next_status is unaligned to the
> cluster size or even request alignment of the source. Avoid this by
> stripping down the s->sector_next_status
On Thu, Sep 10, 2020 at 10:18 PM Thomas Huth wrote:
> On 10/09/2020 12.37, Yonggang Luo wrote:
> > This reverts commit 45f7b7b9f38f5c4d1529a37c93dedfc26a231bba
> > ("cirrus.yml: Split FreeBSD job into two parts").
> >
> > freebsd 1 hour limit not hit anymore
> >
> > I think we going to a wrong
On 10/09/2020 11.36, Collin Walling wrote:
> The header contained within the SCCB passed to the SCLP service call
> contains the actual length of the SCCB. Instead of allocating a static
> 4K size for the work sccb, let's allow for a variable size determined
> by the value in the header. The
On Thu, 10 Sep 2020 at 18:43, Andrew Jones wrote:
>
> On Thu, Sep 10, 2020 at 05:17:17PM +0100, Peter Maydell wrote:
> > What QEMU command line are you using to run this?
> > In particular, MTE is not enabled by default, so you need
> > "-cpu max,mte=on" or similar, is not enabled for any
> >
On 9/10/20 1:50 PM, Thomas Huth wrote:
> On 10/09/2020 11.36, Collin Walling wrote:
>> The header contained within the SCCB passed to the SCLP service call
>> contains the actual length of the SCCB. Instead of allocating a static
>> 4K size for the work sccb, let's allow for a variable size
On Thu, Sep 10, 2020 at 04:18:10PM +0200, Thomas Huth wrote:
> On 10/09/2020 12.37, Yonggang Luo wrote:
> > This reverts commit 45f7b7b9f38f5c4d1529a37c93dedfc26a231bba
> > ("cirrus.yml: Split FreeBSD job into two parts").
> >
> > freebsd 1 hour limit not hit anymore
> >
> > I think we going to
From: Bin Meng
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <1598924352-89526-7-git-send-email-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
From: Bin Meng
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.
The 2nd stage bootloader (U-Boot) is using
From: Bin Meng
The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <1599129623-68957-12-git-send-email-bmeng...@gmail.com>
This will make the type name constant consistent with the name of
the type checking macro.
Signed-off-by: Eduardo Habkost
Reviewed-by: Thomas Huth
Message-Id: <20200902224311.1321159-9-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
hw/vfio/ap.c | 8
1 file changed, 4
From: Daniel P. Berrangé
The object_ref/unref methods are intended for use with any subclass of
the base Object. Using "Object *" in the signature is not adding any
meaningful level of type safety, since callers simply use "OBJECT(ptr)"
and this expands to an unchecked cast "(Object *)".
By
This started as a simple script that scanned for regular
expressions, but became more and more complex when exceptions to
the rules were found.
I don't know if this should be maintained in the QEMU source tree
long term (maybe it can be reused for other code transformations
that Coccinelle can't
Make the type checking macro name consistent with the TYPE_*
constant.
Signed-off-by: Eduardo Habkost
Reviewed-by: Hervé Poussineau
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200902224311.1321159-48-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
hw/ppc/rs6000_mc.c | 4 ++--
This makes the code consistent with the rest of QOM code in QEMU,
and will make automated conversion to type declaration macros
simpler.
Signed-off-by: Eduardo Habkost
Reviewed-by: Alistair Francis
Message-Id: <20200824215936.2961951-5-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
Separate run of the TypeCheckMacro converter using the --force
flag, for the cases where typedefs weren't found in the same
header nor in typedefs.h.
Generated initially using:
$ ./scripts/codeconverter/converter.py --force -i \
--pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Then
Make type checking function name consistent with the TYPE_TUSB6010
constant and QOM type name ("tusb6010").
Suggested-by: Philippe Mathieu-Daudé
Suggested-by: "Daniel P. Berrangé"
Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Bin Meng
At present the Kconfig file is in disorder. Let's sort the options.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <1599129623-68957-13-git-send-email-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
hw/riscv/Kconfig | 58
Rename instance and class type checkers to match the
TYPE_CHARDEV_* constant names and the QOM type name strings
("chardev-*").
Signed-off-by: Eduardo Habkost
---
chardev/testdev.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/chardev/testdev.c b/chardev/testdev.c
Rename instance and class type checkers to match the
TYPE_CHARDEV_* constant names and the QOM type name strings
("chardev-*").
Signed-off-by: Eduardo Habkost
---
chardev/wctablet.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/chardev/wctablet.c
On Wed, 9 Sep 2020 21:59:17 +0300
Vladimir Sementsov-Ogievskiy wrote:
> The recommended use of qemu error api assumes returning status together
> with setting errp and avoid void functions with errp parameter. Let's
> improve bdrv_append and some friends to reduce error-propagation
> overhead
+GitLab team & Gerd (for building firmwares)
On 9/8/20 9:29 AM, Laszlo Ersek wrote:
> Rebuild the pc-bios/edk2-*.fd.bz2 binaries, based on the edk2-stable202008
> release.
>
> Cc: Philippe Mathieu-Daudé
> Ref: https://bugs.launchpad.net/qemu/+bug/1852196
> Signed-off-by: Laszlo Ersek
> ---
>
can you reproduce the bug locally or is this a client problem?
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https://bugs.launchpad.net/bugs/1895053
Title:
Cannot nspawn raspbian 10 [FAILED] Failed to start Journal Service.
On Thu, Sep 10, 2020 at 05:17:17PM +0100, Peter Maydell wrote:
> On Thu, 10 Sep 2020 at 16:06, Derrick McKee wrote:
> >
> > Hi,
> >
> > As of commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a compiled with the
> > default configuration, softmmu-aarch64 issues an illegal instruction fault
> > when
From: Bin Meng
When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY
From: Yifei Jiang
When the cause number is equal to or greater than 23, print "(unknown)" in
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
excpetion "guest_store_page_fault" can not be printed.
In addition, the current check of cause is invalid for
From: Nathan Chancellor
When shutting down the machine running a mainline Linux kernel, the
following error happens:
$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
-display none -initrd rootfs.cpio -kernel Image -m 512m \
-nodefaults -serial mon:stdio
...
Requesting
Hopefully the last respin.
Changes v3 -> v4:
* Removed patch "chardev: Rename TYPE_CHARDEV_* to TYPE_*_CHARDEV"
* Removed all chardev/char-parallel.c changes
The following changes since commit 6779038537360e957dbded830f76b08ef5070161:
Merge remote-tracking branch
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
From: Bin Meng
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.
Let's connect a DMA controller to Microchip PolarFire SoC.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
The existing type check macros all unconditionally drop const
qualifiers from their arguments. Keep this behavior in the
macros generated by DECLARE_*CHECKER* by now.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Eduardo Habkost
Message-Id:
> Am 10.09.2020 um 18:58 schrieb Max Reitz :
>
> On 01.09.20 14:51, Peter Lieven wrote:
>> in case of large continous areas that share the same allocation status
>> it happens that the value of s->sector_next_status is unaligned to the
>> cluster size or even request alignment of the source.
On 07.09.20 20:20, Kevin Wolf wrote:
> These QMP commands are replaced by block-export-add/del.
>
> Signed-off-by: Kevin Wolf
> ---
> qapi/block-export.json | 11 +--
> docs/system/deprecated.rst | 8
> 2 files changed, 17 insertions(+), 2 deletions(-)
OK, but:
> diff
On Wed, 9 Sep 2020 21:59:22 +0300
Vladimir Sementsov-Ogievskiy wrote:
> Let's check return value of mirror_start_job to check for failure
> instead of local_err.
>
> Rename ret to job, as ret is usually integer variable.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
Reviewed-by:
On Sep 5, 2020, 16:05 +0530, Ani Sinha , wrote:
> This change adds a new unit test for the global flag
> 'acpi-pci-hotplug-with-bridge-support' which is available for cold plugged pci
> bridges in i440fx. The flag can be used to turn off acpi based hotplug support
> for all the slots of the pci
The M-profile definition of the MVFR1 ID register differs slightly
from the A-profile one, and in particular the check for "does the CPU
support fp16 arithmetic" is not the same.
We don't currently implement any M-profile CPUs with fp16 arithmetic,
so this is not yet a visible bug, but correcting
Perhaps the problem is triggered by the host systemd version as I have:
$ systemd-nspawn --version
systemd 245 (v245.7-1.fc32)
+PAM +AUDIT +SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP
+GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only
Generated using:
$ ./scripts/codeconverter/converter.py -i \
--pattern=ObjectDeclareType $(git grep -l '' -- '*.[ch]')
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Eduardo Habkost
Message-Id: <20200831210740.126168-19-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
This looks like a copy/paste mistake: the instance type checking
macro for TYPE_GPEX_ROOT_DEVICE was named MCH_PCI_DEVICE.
Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200902224311.1321159-2-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
This makes the code consistent with the rest of QOM code in QEMU,
and will make automated conversion to type declaration macros
simpler.
Signed-off-by: Eduardo Habkost
Message-Id: <20200824215936.2961951-4-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
hw/isa/lpc_ich9.c | 2 +-
1 file
This will make the type name constant consistent with the name of
the type checking macro.
Signed-off-by: Eduardo Habkost
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200902224311.1321159-7-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
hw/usb/dev-smartcard-reader.c | 8
Make the type checking macro name consistent with the TYPE_*
constant.
Signed-off-by: Eduardo Habkost
Reviewed-by: Zhang Chen
Message-Id: <20200902224311.1321159-41-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
net/filter-rewriter.c | 18 +-
1 file changed, 9
Rename instance and class type checkers to match the
TYPE_CHARDEV_* constant names and the QOM type name strings
("chardev-*").
Signed-off-by: Eduardo Habkost
---
chardev/char-parallel.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/chardev/char-parallel.c
Use DECLARE_INSTANCE_CHECKER instead of manually defining the
instance type checking macro.
Signed-off-by: Eduardo Habkost
---
chardev/char-parallel.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/chardev/char-parallel.c b/chardev/char-parallel.c
index
On 9/8/20 2:08 PM, Laszlo Ersek wrote:
> On 09/08/20 10:22, Philippe Mathieu-Daudé wrote:
>> Hi Laszlo,
>>
>> On 9/8/20 9:29 AM, Laszlo Ersek wrote:
>>> Update the edk2 submodule from release edk2-stable201905 to
>>> edk2-stable202008. The release notes can be read at
>> [...]
>>>
>>> Cc: Philippe
On 09/10/20 18:00, Philippe Mathieu-Daudé wrote:
> On 9/10/20 5:44 PM, Laszlo Ersek wrote:
>> On 09/10/20 17:32, Philippe Mathieu-Daudé wrote:
>>> On 9/8/20 2:08 PM, Laszlo Ersek wrote:
On 09/08/20 10:22, Philippe Mathieu-Daudé wrote:
> Hi Laszlo,
>
> On 9/8/20 9:29 AM, Laszlo
On Wed, 9 Sep 2020 21:59:19 +0300
Vladimir Sementsov-Ogievskiy wrote:
> This patch is generated by cocci script:
>
> @@
> symbol bdrv_open_child, errp, local_err;
> expression file;
> @@
>
> file = bdrv_open_child(...,
> -_err
> +errp
>
On Thu, Sep 10, 2020 at 09:53:03AM +0800, Jason Wang wrote:
> > Maybe it would be good too that vhost provides real 4k-aligned addresses (in
> > vhost_iotlb_miss)? My understanding is that PCI_ATS_CAP_PAGE_ALIGNED will
> > be
> > more compatible than without the bit set.
>
>
> Yes, I've
On 200910 1645, Darren Kenny wrote:
> Hi Alex,
>
> I'm certainly not an expert in meson, but have some questions below...
>
> On Wednesday, 2020-09-09 at 18:05:16 -04, Alexander Bulekov wrote:
> > The order of the add_project_link_arguments calls impacts which
> > arguments are placed between
On 9/10/20 12:43 AM, Kele Huang wrote:
> Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since
> MIPS64r1, and MIPS32 since MIPS32r2.
>
> Signed-off-by: Kele Huang
> ---
> accel/tcg/user-exec.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git
* Chuan Zheng (zhengch...@huawei.com) wrote:
> Implement calculate_dirtyrate() function.
>
> Signed-off-by: Chuan Zheng
> Signed-off-by: YanYing Zhuang
Reviewed-by: Dr. David Alan Gilbert
> ---
> migration/dirtyrate.c | 45 +++--
> 1 file changed, 43
Here's the new version, there are two patches this time.
Berto
v3:
- Add a new patch to improve the reporting of BDRV_BLOCK_ZERO [Vladimir]
- Rename function to bdrv_co_is_zero_fast() [Vladimir, Kevin]
- Don't call bdrv_common_block_status_above() if bytes == 0
v2:
From: Bin Meng
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin
From: Bin Meng
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.
This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model.
From: Bin Meng
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
Thanks for the help. The virt,mte=on did it!
On Thu, Sep 10, 2020 at 1:49 PM Peter Maydell
wrote:
> On Thu, 10 Sep 2020 at 18:43, Andrew Jones wrote:
> >
> > On Thu, Sep 10, 2020 at 05:17:17PM +0100, Peter Maydell wrote:
> > > What QEMU command line are you using to run this?
> > > In
This makes the code consistent with the rest of QOM code in QEMU,
and will make automated conversion to type declaration macros
simpler.
Signed-off-by: Eduardo Habkost
Message-Id: <20200824215936.2961951-3-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
hw/intc/omap_intc.c | 2 +-
1
On 9/8/20 9:29 AM, Laszlo Ersek wrote:
> Ref:https://bugs.launchpad.net/qemu/+bug/1852196
> Repo: https://github.com/lersek/qemu.git
> Branch: edk2stable202008_lp_1852196
>
> This series consumes the following upstream edk2 releases:
>
>
Some chardev QOM cleanup patches had to be dropped from my queue
due to build erros introduced by code movements across ifdef
boundaries at char-parallel.c. This series redo the changes from
those patches, but the macro renames are now a little different:
In this version I have decided to rename
Rename instance and class type checkers to match the
TYPE_CHARDEV_MSMOUSE constant name and the QOM type name string
("chardev-msmouse").
Signed-off-by: Eduardo Habkost
---
chardev/msmouse.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/chardev/msmouse.c
The macro is exactly the same for both Linux and BSD, so move its
definition outside the host OS #ifdef blocks.
Signed-off-by: Eduardo Habkost
---
chardev/char-parallel.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/chardev/char-parallel.c
The struct itself may have a different definition on each OS, but
we can define the typedef in common code, outside the host OS #ifdefs.
Signed-off-by: Eduardo Habkost
---
chardev/char-parallel.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
On Fri, 4 Sep 2020 at 14:38, Philippe Mathieu-Daudé wrote:
>
> On 9/3/20 10:20 PM, Peter Maydell wrote:
> > Implement a model of the MPS2 with the AN500 firmware. This is
> > similar to the AN385, with the following differences:
> > * Cortex-M7 CPU
> > * PSRAM is at 0x6000_
> > * Ethernet
Some machines don't have much differences a part from the flash model
being used. Introduce new machine properties to change them from the
command line.
Cc: 郁雷
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 45 +++--
1 file changed, 43
On 9/8/20 2:14 PM, Laszlo Ersek wrote:
> On 09/08/20 10:27, Philippe Mathieu-Daudé wrote:
>> On 9/8/20 9:29 AM, Laszlo Ersek wrote:
>>> The NVDIMM_ACPI_MEM_ADDR dword in "virt/SSDT.memhp" needs an update due to
>>> the firmware now allocating NVDIMM_DSM_MEM_FILE at a lower address.
>>>
On 9/10/20 5:44 PM, Laszlo Ersek wrote:
> On 09/10/20 17:32, Philippe Mathieu-Daudé wrote:
>> On 9/8/20 2:08 PM, Laszlo Ersek wrote:
>>> On 09/08/20 10:22, Philippe Mathieu-Daudé wrote:
Hi Laszlo,
On 9/8/20 9:29 AM, Laszlo Ersek wrote:
> Update the edk2 submodule from release
On 07.08.20 12:03, Swapnil Ingle wrote:
> block/vhdx uses qemu block layer where sector size is always 512 bytes.
> This may have issues with 4K logical sector sized vhdx image.
>
> For e.g qemu-img convert on such images fails with following assert:
>
> $qemu-img convert -f vhdx -O raw
From: Marc-André Lureau
Hi,
Among the QEMU developers, there is a desire to use Rust. (see previous
thread from Stefan "Why QEMU should move from C to Rust", the rust-vmm
related projects and other experiments).
Thanks to our QAPI type system and the associate code generator, it is
relatively
Quoting Michael Roth (2020-09-03 15:58:18)
> Hi everyone,
>
> The following new patches are queued for QEMU stable v5.0.1:
>
> https://github.com/mdroth/qemu/commits/stable-5.0-staging
>
> Patch freeze is 2020-09-10, and the release is planned for 2020-09-15:
>
>
From: Bin Meng
Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
which is actually an IP reused from the SiFive FU540 chip.
This creates a model to support
From: Bin Meng
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id:
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