On 15/02/2022 23.10, Eric Blake wrote:
On Tue, Feb 15, 2022 at 02:20:31PM +0100, Thomas Huth wrote:
Instead of failing the iotests if GNU sed is not available (or skipping
them completely in the check-block.sh script), it would be better to
simply skip the bash-based tests that rely on GNU sed,
Excerpts from Cédric Le Goater's message of February 16, 2022 8:52 pm:
> On 2/16/22 11:25, Nicholas Piggin wrote:
>> This implements the Nested KVM HV hcall API for spapr under TCG.
>>
>> The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
>> L1 is switched back in returned from
Am Mittwoch, 16. Februar 2022, 01:09:04 CET schrieb Atish Patra:
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse
We need a newer compiler to build upcoming tests that test for z15
features with -march=z15. So let's do it similar to arm64 and powerpc,
using an environment based on debian11 to build tests only.
Cc: Thomas Huth
Cc: Cornelia Huck
Cc: Richard Henderson
Cc: "Alex Bennée"
Cc: "Philippe
On 2/16/22 08:19, Gerd Hoffmann wrote:
> On Tue, Feb 15, 2022 at 07:37:40PM +, Joao Martins wrote:
>> On 2/15/22 09:53, Gerd Hoffmann wrote:
>>> What is missing:
>>>
>>> * Some way for the firmware to get a phys-bits value it can actually
>>>use. One possible way would be to have a
Queued
* Vivek Goyal (vgo...@redhat.com) wrote:
> Hi,
>
> This is V6 of the patches. I posted V5 here.
>
> https://listman.redhat.com/archives/virtio-fs/2022-February/msg00012.html
>
> This patch series basically allows client to send a security context
> (which is expected to be xattr
ping
https://patchew.org/QEMU/20220113152836.60398-1-yaroshchuk2...@gmail.com/
чт, 13 янв. 2022 г. в 18:28, Vladislav Yaroshchuk :
> On Apple hosts we can read AppleSMC OSK key directly from host's
> SMC and forward this value to QEMU Guest.
>
> New 'hostosk' property is added:
> * `-device
* Vivek Goyal (vgo...@redhat.com) wrote:
> On Tue, Feb 15, 2022 at 07:15:29PM +0100, Greg Kurz wrote:
> > Honor the expected behavior of syncfs() to synchronously flush all data
> > and metadata to disk on linux systems.
> >
> > If virtiofsd is started with '-o announce_submounts', the client is
Looks straight forward to me.
[...]
>
> +int kvm_set_ioregionfd(struct kvm_ioregion *ioregionfd)
> +{
> +KVMState *s = kvm_state;
> +int ret = -1;
> +
> +ret = kvm_vm_ioctl(s, KVM_SET_IOREGION, ioregionfd);
> +if (ret < 0) {
> +error_report("Failed SET_IOREGION syscall
On 16/02/2022, Emanuele Giuseppe Esposito wrote:
On 04/02/2022 11:07, Jon Doron wrote:
SynIc can be enabled regardless of the SControl mechanisim which can
register a GSI for a given SintRoute.
This behaviour can achived by setting enabling SIMP and then the guest
will poll on the message
On 2/16/22 11:25, Nicholas Piggin wrote:
Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).
HV exceptions can now be raised in the
On Dienstag, 15. Februar 2022 08:01:37 CET Greg Kurz wrote:
> On Mon, 14 Feb 2022 17:43:51 +0300
>
> Vitaly Chikunov wrote:
> > Why g_new0 and not just g_malloc0? This is smallest code change, which
> > seems appropriate for a bug fix.
>
> I prefer g_new0() for the exact reasons that are
On 16/02/2022, Emanuele Giuseppe Esposito wrote:
+
+static uint16_t handle_recv_msg(HvSynDbg *syndbg, uint64_t outgpa,
+uint32_t count, bool is_raw, uint32_t options,
+uint64_t timeout, uint32_t *retrieved_count)
+{
+uint16_t
On 16/02/2022, Emanuele Giuseppe Esposito wrote:
On 04/02/2022 11:07, Jon Doron wrote:
Add all required definitions for hyperv synthetic debugger interface.
Signed-off-by: Jon Doron
---
include/hw/hyperv/hyperv-proto.h | 52
target/i386/kvm/hyperv-proto.h
> +static DisasJumpType op_sel(DisasContext *s, DisasOps *o)
> +{
> +DisasCompare c;
> +disas_jcc(s, , get_field(s, m4));
> +tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
> +o->in1, o->in2);
> +free_compare();
> +return DISAS_NEXT;
> +}
I
On 2/16/22 11:25, Nicholas Piggin wrote:
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and
bdrv_refresh_limits() recurses down to the node's children. That does
not seem necessary: When we refresh limits on some node, and then
recurse down and were to change one of its children's BlockLimits, then
that would mean we noticed the changed limits by pure chance. The fact
that we refresh
Add a parameter to optionally open a QMP connection when creating a
QemuStorageDaemon instance.
Signed-off-by: Hanna Reitz
---
tests/qemu-iotests/iotests.py | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/iotests.py
Hi,
v1 with detailed reasoning:
https://lists.nongnu.org/archive/html/qemu-block/2022-02/msg00508.html
This series makes bdrv_refresh_limits() non-recursive so that it is
sufficient for callers to ensure that the node on which they call it
will not receive concurrent I/O requests (instead of
Test the following scenario:
1. Some block node (null-co) attached to a user (here: NBD server) that
performs I/O and keeps the node in an I/O thread
2. Repeatedly run blockdev-add/blockdev-del to add/remove an overlay
to/from that node
Each blockdev-add triggers bdrv_refresh_limits(), and
Hi,
> Given the semantic differences from 'i440fx', changing the default
> machine type has effects that are equivalent to breaking command
> line syntax compatibility, which is something we've always tried
> to avoid.
And if we are fine breaking backward compatibility I'd rather *not* pick
a
On 2/15/22 4:32 PM, Andrew Jones wrote:
On Tue, Feb 15, 2022 at 04:19:01PM +0800, Gavin Shan wrote:
The issue isn't related to CPU topology directly. It's actually related
to the fact: the default NUMA node ID will be picked for one particular
CPU if the associated NUMA node ID isn't provided
On 16.02.22 11:31, David Hildenbrand wrote:
>> +static DisasJumpType op_sel(DisasContext *s, DisasOps *o)
>> +{
>> +DisasCompare c;
>> +disas_jcc(s, , get_field(s, m4));
>> +tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
>> +o->in1, o->in2);
>> +
On 15.02.22 21:27, David Miller wrote:
> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>
(I know, a lot of mails from my side :) )
1. I think we usually use the prefix in the subject
On 16.02.22 10:57, David Hildenbrand wrote:
> On 15.02.22 21:27, David Miller wrote:
>> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
>> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
>> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>>
>> Signed-off-by: David Miller
>> ---
>>
* Gerd Hoffmann (kra...@redhat.com) wrote:
> Hi,
>
> > Given the semantic differences from 'i440fx', changing the default
> > machine type has effects that are equivalent to breaking command
> > line syntax compatibility, which is something we've always tried
> > to avoid.
>
> And if we are
On Tue, Feb 15, 2022 at 10:18:12AM -0800, Elena wrote:
> On Mon, Feb 14, 2022 at 02:37:21PM +, Stefan Hajnoczi wrote:
> > On Mon, Feb 07, 2022 at 11:22:18PM -0800, Elena Ufimtseva wrote:
> > > Signed-off-by: Elena Ufimtseva
> > > ---
> > > meson.build| 15 ++-
> > >
> /* Really format SS_b, but we pack both lengths into one argument
> @@ -735,6 +753,9 @@
> /* PACK UNICODE */
> C(0xe100, PKU, SS_f, E2, la1, a2, 0, 0, pku, 0)
> +/* POPULATION COUNT */
> +C(0xb9e1, POPCNT, RRE, PC, 0, r2_o, r1, 0, popcnt, nz64)
You actually need
On Tue, Feb 15, 2022 at 10:16:04AM -0800, Elena wrote:
> On Mon, Feb 14, 2022 at 02:52:29PM +, Stefan Hajnoczi wrote:
> > On Mon, Feb 07, 2022 at 11:22:14PM -0800, Elena Ufimtseva wrote:
> > > This patchset is an RFC version for the ioregionfd implementation
> > > in QEMU. The kernel patches
On Wed, Feb 16, 2022 at 11:01:24AM +, Dr. David Alan Gilbert wrote:
> * Gerd Hoffmann (kra...@redhat.com) wrote:
> > Hi,
> >
> > > Given the semantic differences from 'i440fx', changing the default
> > > machine type has effects that are equivalent to breaking command
> > > line syntax
From: Anup Patel
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank
From: Guo Ren
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit
On Wed, Feb 16, 2022 at 4:23 PM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
> base addresses. Also adds these as unimplemented devices.
>
> The address references can be found [1].
>
> [1]
>
From: Anup Patel
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Frank
In the first generation of Arch LBR, the max support
Arch LBR depth is 32, both host and guest use the value
to set depth MSR. This can simplify the implementation
of patch given the side-effect of mismatch of host/guest
depth MSR: XRSTORS will reset all recording MSRs to 0s
if the saved depth
From: Yu Li
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li
Reviewed-by: Alistair Francis
Message-Id:
Qemu might crash when provided incomplete '-global' option.
For example:
qemu-system-x86_64 -global driver=isa-fdc
qemu-system-x86_64: ../../devel/qemu/qapi/string-input-visitor.c:394:
string_input_visitor_new: Assertion `str' failed.
Aborted (core dumped)
Fixes:
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
Signed-off-by: Yang Weijiang
---
On Fri, Feb 11, 2022 at 05:13:09PM +0100, Laurent Vivier wrote:
vhost_vdpa_host_notifiers_init() initializes queue notifiers
for queues "dev->vq_index" to queue "dev->vq_index + dev->nvqs",
whereas vhost_vdpa_host_notifiers_uninit() uninitializes the
same notifiers for queue "0" to queue
This is useful to analyze changes in the U-Boot RAM driver when SDRAM
training is performed.
Signed-off-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 2 ++
hw/misc/trace-events | 4
2 files changed, 6 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index
Only a limited set of bits are used for decoding the Start and End
addresses of the mapping window of a flash device.
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 1 +
hw/ssi/aspeed_smc.c | 11 +++
2 files changed, 12 insertions(+)
diff --git
On 04/02/2022 11:07, Jon Doron wrote:
> Add all required definitions for hyperv synthetic debugger interface.
>
> Signed-off-by: Jon Doron
> ---
> include/hw/hyperv/hyperv-proto.h | 52
> target/i386/kvm/hyperv-proto.h | 37 +++
> 2
On Wed, Feb 16, 2022 at 02:27:49PM +0800, Peter Xu wrote:
> The new patch layout:
>
> Patch 1-3: Three leftover patches from patchset "[PATCH v3 0/8] migration:
> Postcopy cleanup on ram disgard" that I picked up here too.
>
>
On 04/02/2022 11:07, Jon Doron wrote:
> SynDbg commands can come from two different flows:
> 1. Hypercalls, in this mode the data being sent is fully
>encapsulated network packets.
> 2. SynDbg specific MSRs, in this mode only the data that needs to be
>transfered is passed.
>
>
On Mon, Feb 14, 2022 at 08:34:15PM +0100, Eugenio Pérez wrote:
Simplifying memory management.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Stefano Garzarella
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index
Michael Roth writes:
> On Mon, Feb 14, 2022 at 03:14:37PM +0100, Markus Armbruster wrote:
>> Cc: the qemu-ga maintainer
>>
>> John Snow writes:
>>
>> > [Moving our discussion upstream, because it stopped being brief and
>> > simple.]
>
> Hi John, Markus,
>
>>
>> Motivation: qemu-ga doesn't
Architectural LBR (Arch LBR) is the enhancement for previous
non-Architectural LBR (Legacy LBR). This feature is introduced
in Intel Architecture Instruction Set Extensions and Future
Features Programming Reference[0]. The advantages of Arch LBR
can be referred to in native patch series[1].
Since
From: Joel Stanley
When time permits, we should introduce defines for the HW strapping
registers to cleanly decode the values.
SCU500 = 0x00422016
Disable ARM JTAG trusted world debug: 0x1
Disable ARM JTAG debug: 0x1
VGA Memory Size: 0x1 [16MB]
Cortex M3: 0x1 [Disabled]
Boot device:
On 15.02.22 23:22, Eric Blake wrote:
On Tue, Feb 15, 2022 at 02:57:27PM +0100, Hanna Reitz wrote:
Test the following scenario:
1. Some block node (null-co) attached to a user (here: NBD server) that
performs I/O and keeps the node in an I/O thread
2. Repeatedly run blockdev-add/blockdev-del
> +
> +static uint16_t handle_recv_msg(HvSynDbg *syndbg, uint64_t outgpa,
> +uint32_t count, bool is_raw, uint32_t
> options,
> +uint64_t timeout, uint32_t *retrieved_count)
> +{
> +uint16_t ret;
> +uint8_t
On 2/16/22 07:56, Alexander Kanavin wrote:
Lack of AVX/AVX2 support in the i386 TCG has been a significant gap
for a long while; I've started work to close this gap.
This is of course nowhere near complete, or even buildable, I'm
just requesting initial feedback from the qemu gurus - am I on
On 16.02.22 10:43, Thomas Huth wrote:
> On 16/02/2022 10.17, David Hildenbrand wrote:
>> On 15.02.22 21:27, David Miller wrote:
> ...
>>> diff --git a/tests/tcg/s390x/Makefile.target
>>> b/tests/tcg/s390x/Makefile.target
>>> index 1a7238b4eb..16b9d45307 100644
>>> ---
Reviewed-by: David Gibson
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index fcc83a7701..bbc75afbc0 100644
--- a/target/ppc/excp_helper.c
+++
On Wed, 16 Feb 2022 at 10:24, Richard Henderson
wrote:
> > There's an enormous amount of legacy SSE instructions to adjust
> > for VEX-128 and VEX-256 flavours, so I would want to know that this
> > way would be acceptable.
> >
> > Signed-off-by: Alexander Kanavin
> > ---
>
> Have a look at
Hi,
This new version adds a new patch (patch 2) that fixes --disable-tcg
--disable-linux-user compilation.
The series was based on upstream master.
Changes from v12:
- patch 2 (new):
* make power8-pmu.c compile only with CONFIG_TCG available
- patch 4 (former 3):
* added Cedric's r-b
- v11
On Tue, Feb 15, 2022 at 05:24:14PM -0600, Eric Blake wrote:
> Oh. The QMP command (which is immediately visible through
> nbd-server-add/block-storage-add to qemu and qemu-storage-daemon)
> gains "multi-conn":"on", but you may be right that qemu-nbd would want
> a command line option (either that,
This patchset adds support for the synthetic debugging device.
HyperV supports a special transport layer for the kernel debugger when
running in HyperV.
This patchset add supports for this device so you could have a setup
fast windows kernel debugging.
At this point of time, DHCP is not
The spapr virtual hypervisor does not require the hdecr timer.
Remove it.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/ppc.c| 2 +-
hw/ppc/spapr_cpu_core.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
The radix on vhyp MMU uses a single-level radix table walk, with the
partition scope mapping provided by the flat QEMU machine memory.
A subsequent change will use the two-level radix walk on vhyp in some
situations, so provide a helper which can abstract that logic.
Reviewed-by: Cédric Le
On 16/02/2022 12.01, Dr. David Alan Gilbert wrote:
* Gerd Hoffmann (kra...@redhat.com) wrote:
Hi,
Given the semantic differences from 'i440fx', changing the default
machine type has effects that are equivalent to breaking command
line syntax compatibility, which is something we've always
To allow postcopy recovery, the ram fast load (preempt-only) dest QEMU thread
needs similar handling on fault tolerance. When ram_load_postcopy() fails,
instead of stopping the thread it halts with a semaphore, preparing to be
kicked again when recovery is detected.
A mutex is introduced to make
From: Anup Patel
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-id:
Two tests are added: a normal postcopy preempt test, and a recovery test.
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 39 ++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/migration-test.c
From: Anup Patel
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by
The POWER9 DD2.0 PVR is incorrect. It doesn't cause problems because
the pvr check is masking it and matching against the base.
Correct it, add a PVR for DD2.1.
Signed-off-by: Nicholas Piggin
---
Since v1: new patch
target/ppc/cpu-models.h | 3 ++-
1 file changed, 2 insertions(+), 1
The Last Branch Recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors which records a running trace of the most
recent branches taken by the processor in the LBR stack. This option
indicates the LBR format to enable for guest perf.
The LBR feature is enabled if below
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
---
v2: also remove from docs/about/deprecated.rst
docs/about/deprecated.rst | 7 -
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c| 53 --
3 files changed, 61 deletions(-)
On Tue, Feb 15, 2022 at 08:34:23PM +0100, Eugenio Pérez wrote:
> This iova tree function allows it to look for a hole in allocated
> regions and return a totally new translation for a given translated
> address.
>
> It's usage is mainly to allow devices to access qemu address space,
> remapping
On Wed, Feb 16, 2022 at 2:23 PM Alistair Francis
wrote:
>
> From: Wilfred Mallawa
>
> This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
> base addresses. Also adds these as unimplemented devices.
>
> The address references can be found [1].
>
> [1]
>
If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, the processor
supports Architectural LBRs. In this case, CPUID leaf 01CH
indicates details of the Architectural LBRs capabilities.
XSAVE support for Architectural LBRs is enumerated in
CPUID.(EAX=0DH, ECX=0FH).
Signed-off-by: Yang Weijiang
---
There're some new features, including Arch LBR, depending
on XSAVES/XRSTORS support, the new instructions will
save/restore data based on feature bits enabled in XCR0 | XSS.
This patch adds the basic support for related CPUID enumeration
and meanwhile changes the name from FEAT_XSAVE_COMP_{LO|HI}
From: Joel Stanley
This helps quieten booting the current Rainier kernel.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 9789a489047b..0e5e5c31d59c
On 15.02.22 23:19, Eric Blake wrote:
On Tue, Feb 15, 2022 at 02:57:26PM +0100, Hanna Reitz wrote:
Add a parameter to optionally open a QMP connection when creating a
QemuStorageDaemon instance.
Signed-off-by: Hanna Reitz
---
tests/qemu-iotests/iotests.py | 29 -
On 15.02.22 21:27, David Miller wrote:
> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>
> Signed-off-by: David Miller
> ---
> tests/tcg/s390x/Makefile.target | 2 +-
>
From: Joel Stanley
Just a stub that indicates the system has booted in secure boot mode.
Used for testing the driver:
https://lore.kernel.org/all/20211019080608.283324-1-j...@jms.id.au/
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 3 +
Define Arch LBR bit in XSS and save/restore structure
for XSAVE area size calculation.
Signed-off-by: Yang Weijiang
---
target/i386/cpu.c | 6 +-
target/i386/cpu.h | 23 +++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c
From: Joel Stanley
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Message-Id: <20220216080947.65955-1-j...@jms.id.au>
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst | 7 -
docs/system/arm/aspeed.rst | 1 -
hw/arm/aspeed.c| 53
On Wed, Feb 16, 2022 at 06:39:47PM +1030, Joel Stanley wrote:
> It was scheduled for removal in 7.0.
>
> Signed-off-by: Joel Stanley
> ---
> v2: also remove from docs/about/deprecated.rst
>
> docs/about/deprecated.rst | 7 -
> docs/system/arm/aspeed.rst | 1 -
> hw/arm/aspeed.c
On Tue, 15 Feb 2022 at 09:35, Paolo Bonzini wrote:
>
> The following changes since commit 2d88a3a595f1094e3ecc6cd2fd1e804634c84b0f:
>
> Merge remote-tracking branch 'remotes/kwolf-gitlab/tags/for-upstream' into
> staging (2022-02-14 19:54:00 +)
>
> are available in the Git repository at:
>
> -Original Message-
> From: John Johnson
> Sent: 16 February 2022 02:10
> To: Thanos Makatos
> Cc: qemu-devel@nongnu.org
> Subject: Re: [RFC v4 08/21] vfio-user: define socket receive functions
>
>
>
> > On Feb 15, 2022, at 6:50 AM, Thanos Makatos
> wrote:
> >
> >>>
> >
> > On
On Tue, Feb 15, 2022 at 10:53:58AM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > I don't know what behavior should be if firmware tries to program
> > PCI64 hole beyond supported phys-bits.
>
> Well, you are basically f*cked.
>
> Unfortunately there is no reliable way to figure what phys-bits
On 16/02/2022 10.17, David Hildenbrand wrote:
On 15.02.22 21:27, David Miller wrote:
...
diff --git a/tests/tcg/s390x/Makefile.target
b/tests/tcg/s390x/Makefile.target
index 1a7238b4eb..16b9d45307 100644
--- a/tests/tcg/s390x/Makefile.target
+++ b/tests/tcg/s390x/Makefile.target
@@ -1,6 +1,6
On 15.02.22 21:27, David Miller wrote:
> tests/tcg/s390x/mie3-compl.c: [N]*K instructions
> tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
> tests/tcg/s390x/mie3-sel.c: SELECT instruction
>
> Signed-off-by: David Miller
> ---
> tests/tcg/s390x/Makefile.target | 2 +-
>
On 2/16/22 04:01, Philippe Mathieu-Daudé via wrote:
GCC 10.1 introduced the -moutline-atomics option on Aarch64.
This options is enabled by default, and triggers a link failure:
Undefined symbols for architecture arm64:
"___aarch64_cas1_acq_rel", referenced from:
On 2/16/22 02:16, Nicholas Piggin wrote:
Excerpts from Cédric Le Goater's message of February 16, 2022 4:21 am:
On 2/15/22 04:16, Nicholas Piggin wrote:
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is
Add all required definitions for hyperv synthetic debugger interface.
Signed-off-by: Jon Doron
---
include/hw/hyperv/hyperv-proto.h | 52
target/i386/kvm/hyperv-proto.h | 37 +++
2 files changed, 89 insertions(+)
diff --git
Signed-off-by: Jon Doron
---
hw/hyperv/Kconfig | 5 +
hw/hyperv/meson.build | 1 +
hw/hyperv/syndbg.c| 402 ++
3 files changed, 408 insertions(+)
create mode 100644 hw/hyperv/syndbg.c
diff --git a/hw/hyperv/Kconfig b/hw/hyperv/Kconfig
index
SynIc can be enabled regardless of the SControl mechanisim which can
register a GSI for a given SintRoute.
This behaviour can achived by setting enabling SIMP and then the guest
will poll on the message slot.
Once there is another message pending the host will set the message slot
with the
In prepartion for implementing a full partition table option for
vhyp, update the get_pate method to take an lpid and return a
success/fail indicator.
The spapr implementation currently just asserts lpid is always 0
and always return success.
Reviewed-by: Cédric Le Goater
Signed-off-by:
Invalid or missing partition table entry exceptions should cause HV
interrupts. HDSISR is set to bad MMU config, which is consistent with
the ISA and experimentally matches what POWER9 generates.
Reviewed-by: Fabiano Rosas
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Nicholas Piggin
---
Machines which don't emulate the HDEC facility are able to use the
timer for something else. Provide functions to start and stop the
hdecr timer.
Signed-off-by: Nicholas Piggin
---
hw/ppc/ppc.c | 21 +
include/hw/ppc/ppc.h | 3 +++
2 files changed, 24 insertions(+)
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and out according to
the nested KVM HV hcall
The virtual hypervisor currently always intercepts and handles
hypercalls but with a future change this will not always be the case.
Add a helper for the test so the logic is abstracted from the mechanism.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
On 2/16/22 09:09, Joel Stanley wrote:
It was scheduled for removal in 7.0.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
v2: also remove from docs/about/deprecated.rst
docs/about/deprecated.rst | 7 -
docs/system/arm/aspeed.rst | 1 -
From: Anup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled
On Fri, Feb 11, 2022 at 06:02:59PM +0100, Laurent Vivier wrote:
If call virtio_queue_set_host_notifier_mr fails, should free
host-notifier memory-region.
This problem can trigger a coredump with some vDPA drivers (mlx5,
but not with the vdpasim), if we unplug the virtio-net card from
the guest
From: Weiwei Li
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
Message-Id:
From: Anup Patel
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Message-id:
The DEFINE_PROP_UINT64_CHECKMASK maro applies certain mask check agaist
user-supplied property value, reject the value if it violates the bitmask.
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Yang Weijiang
---
hw/core/qdev-properties.c| 19 +++
On Mon, 14 Feb 2022 10:30:18 +
Daniel P. Berrangé wrote:
> On Mon, Feb 14, 2022 at 09:21:07AM +0100, Igor Mammedov wrote:
> > On Mon, 14 Feb 2022 14:58:57 +0800
> > Yang Zhong wrote:
> >
> > > On Mon, Feb 07, 2022 at 09:37:52AM +0100, Igor Mammedov wrote:
> > > > On Sat, 5 Feb 2022
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