On Wed, Jul 27, 2022 at 11:26:15AM +0100, Peter Maydell wrote:
> On Tue, 26 Jul 2022 at 23:30, Richard Henderson
> wrote:
> >
> > On 7/26/22 09:32, Peter Maydell wrote:
> > > Coverity complains that in functions like pci_set_word_by_mask()
> > > we might end up shifting by more than 31 bits. This
Am 17/08/2022 um 10:34 schrieb Kevin Wolf:
> Am 16.08.2022 um 17:09 hat Emanuele Giuseppe Esposito geschrieben:
>>
>>
>> Am 05/08/2022 um 10:37 schrieb Kevin Wolf:
>>> Am 25.07.2022 um 09:38 hat Emanuele Giuseppe Esposito geschrieben:
From: Paolo Bonzini
We want to make sure
On Mon, 8 Aug 2022 13:20:49 +0100
Jonathan Cameron wrote:
> Peter Maydell reported both these issues, having looked into Coverity
> identified issues. The memory leak was straight forward, but testing the
> second patch identified a bug in the Linux kernel.
>
> This bug has been fixed in the
On 8/17/22 08:27, Ilya Leoshkevich wrote:
On Wed, 2022-08-17 at 08:15 -0500, Richard Henderson wrote:
On 8/17/22 06:08, Ilya Leoshkevich wrote:
@@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start,
target_ulong end, int flags)
(flags & PAGE_WRITE) &&
On 8/17/22 06:08, Ilya Leoshkevich wrote:
+static void cpu_tb_jmp_cache_remove(TranslationBlock *tb)
+{
+CPUState *cpu;
+uint32_t h;
+
+/* remove the TB from the hash list */
+if (TARGET_TB_PCREL) {
+/* Any TB may be at any virtual address */
+CPU_FOREACH(cpu) {
+
On 15/08/2022 17:02, Cédric Le Goater wrote:
[ Adding Fabiano who reworked all exception models for 7.0 and Nick
who rewrote the Linux side sometime ago ]
On 8/15/22 18:20, Matheus Ferst wrote:
Currently, PowerPC interrupts are handled as follows:
1) The CPU_INTERRUPT_HARD bit of
On 15/08/2022 18:23, Fabiano Rosas wrote:
Matheus Ferst writes:
Critical Input, Watchdog Timer, and Fixed Interval Timer are only
defined for embedded CPUs. The Programmable Interval Timer is 40x-only.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 18 --
1
On Wed, Aug 17, 2022 at 10:39:40AM +0200, Gerd Hoffmann wrote:
> Causes regressions when doing direct kernel boots with OVMF.
>
> At this point in the release cycle the only sensible action
> is to just disable this for 7.1 and sort it properly in the
> 7.2 devel cycle.
>
> Cc: Jason A.
Commit 5f76a7aac156ca75680dad5df4a385fd0b58f6b1 is looking harmless from
the first glance, but it has changed things a lot. 'libvirt' uses it to
detect that it should follow new initialization way and this changes
things considerably. With this procedure followed, blockdev_init() is
not called
Am 17/08/2022 um 10:46 schrieb Kevin Wolf:
@@ -475,13 +477,15 @@ void *block_job_create(const char *job_id, const
BlockJobDriver *driver,
job->ready_notifier.notify = block_job_event_ready;
job->idle_notifier.notify = block_job_on_idle;
-
On Fri, Jul 29, 2022 at 11:04:47PM +0530, Jay Khandkar wrote:
> On Fri, Jul 29, 2022 at 06:09:01PM +0100, Peter Maydell wrote:
> > On Tue, 12 Jul 2022 at 19:38, Jay Khandkar
> > wrote:
> > >
> > > When the local APIC is in a software disabled state, all local interrupt
> > > sources must be
virtio level reset should not affect pci express
registers such as PM, error or link.
Fixes: 27ce0f3afc ("hw/virtio: fix Power Management Control Register for PCI
Express virtio devices")
Fixes: d584f1b9ca ("hw/virtio: fix Link Control Register for PCI Express virtio
devices")
Fixes: c2cabb3422
On Tue, 2022-08-16 at 20:42 -0500, Richard Henderson wrote:
> On 8/16/22 18:43, Ilya Leoshkevich wrote:
> > On Fri, 2022-08-12 at 11:07 -0700, Richard Henderson wrote:
> > > We will want to re-use the result of get_page_addr_code
> > > beyond the scope of tb_lookup.
> > >
> > > Signed-off-by:
Am 17/08/2022 um 10:04 schrieb Emanuele Giuseppe Esposito:
>>> +/* protect against read in job_do_yield_locked */
>>> +JOB_LOCK_GUARD();
>>> +/* ensure the coroutine is quiescent while the AioContext is changed */
>>> +assert(job->pause_count > 0);
>> job->pause_count only shows
On 8/17/22 04:10, WANG Xuerui wrote:
From my own experiences, different use cases care about different aspects of the CPU, and
that IMO is an argument in favor of providing both (high-fidelity models named after
actual product model names, and virtual models named after ISA levels). But before
On Thu, Jul 28, 2022 at 02:55:00PM +0100, Alex Bennée wrote:
> There are some extra bits used over a vhost-user connection which are
> hidden from the device itself. We need to set them here to ensure we
> enable things like the protocol extensions.
>
> Currently net/vhost-user.c has it's own
On Thu, Jul 28, 2022 at 02:55:01PM +0100, Alex Bennée wrote:
> I've noticed asserts firing because we query the status of vdev after
> a vhost connection is closed down. Rather than faulting on the NULL
> indirect just quietly reply false.
>
> Signed-off-by: Alex Bennée
> Message-Id:
On Mon, 15 Aug 2022 15:55:15 -0700
Dan Williams wrote:
> Jonathan Cameron wrote:
> > On Fri, 12 Aug 2022 16:44:03 +0100
> > Jonathan Cameron wrote:
> >
> > > On Thu, 11 Aug 2022 18:08:57 +0100
> > > Jonathan Cameron via wrote:
> > >
> > > > On Tue, 9 Aug 2022 17:08:25 +0100
> > > >
On Wed, 17 Aug 2022 at 11:48, Michael S. Tsirkin wrote:
>
> On Wed, Jul 27, 2022 at 11:26:15AM +0100, Peter Maydell wrote:
> > On Tue, 26 Jul 2022 at 23:30, Richard Henderson
> > wrote:
> > >
> > > On 7/26/22 09:32, Peter Maydell wrote:
> > > > Coverity complains that in functions like
Linux kernel does this in fpregs_store() and fpregs_load(), so
qemu-user should do this as well.
Found by running valgrind's none/tests/s390x/test_sig.
Signed-off-by: Ilya Leoshkevich
---
linux-user/s390x/signal.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/s390x/signal.c
On Wed, 2022-08-17 at 08:15 -0500, Richard Henderson wrote:
> On 8/17/22 06:08, Ilya Leoshkevich wrote:
> > @@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start,
> > target_ulong end, int flags)
> > (flags & PAGE_WRITE) &&
> > p->first_tb) {
> >
On 8/17/22 07:39, Ilya Leoshkevich wrote:
Linux kernel does this in fpregs_store() and fpregs_load(), so
qemu-user should do this as well.
Found by running valgrind's none/tests/s390x/test_sig.
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Richard Henderson
r~
On 15/08/2022 17:09, Fabiano Rosas wrote:
Matheus Ferst writes:
Move the interrupt masking logic to a new method, ppc_pending_interrupt,
and only handle the interrupt processing in ppc_hw_interrupt.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 228
Hi,
On Tue, Jul 05, 2022 at 08:45:06AM -0700, Andrea Bolognani wrote:
> Sorry it took me a while to find the time to look into this!
(1.5 month later.. what can I say!) :)
> Overall this second iteration is a significant improvement over the
> initial one. There are still a few things that I
On Tue, 2022-08-16 at 15:33 -0500, Richard Henderson wrote:
> We're about to start validating PAGE_EXEC, which means that we've
> got to the vsyscall page executable. We had been special casing
> this entirely within translate.
>
> Signed-off-by: Richard Henderson
> ---
> linux-user/elfload.c
Am 05/08/2022 um 15:01 schrieb Kevin Wolf:
> Am 25.07.2022 um 09:38 hat Emanuele Giuseppe Esposito geschrieben:
>> Change the job_{lock/unlock} and macros to use job_mutex.
>>
>> Now that they are not nop anymore, remove the aiocontext
>> to avoid deadlocks.
>
> Okay, so this is the big bad
On 8/17/22 06:08, Ilya Leoshkevich wrote:
@@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start,
target_ulong end, int flags)
(flags & PAGE_WRITE) &&
p->first_tb) {
tb_invalidate_phys_page(addr, 0);
+} else {
+TranslationBlock
On 15/08/2022 19:39, Fabiano Rosas wrote:
Matheus Ferst writes:
Create an interrupt masking method for the POWER9 and POWER10
processors. The new method is based on cpu_has_work_POWER{9,10} and
ppc_pending_interrupt_legacy.
Signed-off-by: Matheus Ferst
---
target/ppc/excp_helper.c | 160
On 15/08/2022 17:25, Fabiano Rosas wrote:
Matheus Ferst writes:
Rename the method to ppc_interrupt_pending_legacy and create a new
ppc_interrupt_pending that will call the appropriate interrupt masking
method based on env->excp_model.
Signed-off-by: Matheus Ferst
---
Hi! Are there any updates? I have not received any comments since the last
email.
On Mon, Aug 8, 2022 at 9:03 PM Nikita Ivanov wrote:
> And summing up the discussion about TEMP_FAILURE_RETRY() usage examples,
> I've come up with a new patch for TFR() to TEMP_FAILURE_RETRY()
> refactoring. I've
On Wed, 2022-08-17 at 08:38 -0500, Richard Henderson wrote:
> On 8/17/22 08:27, Ilya Leoshkevich wrote:
> > On Wed, 2022-08-17 at 08:15 -0500, Richard Henderson wrote:
> > > On 8/17/22 06:08, Ilya Leoshkevich wrote:
> > > > @@ -2243,6 +2250,13 @@ void page_set_flags(target_ulong start,
> > > >
On Wed, 17 Aug 2022 at 15:24, Anton Kochkov wrote:
>
> For consistency, function "update_rx_fifo()" should use
> the RX FIFO register names, not the TX FIFO ones even if
"register field names"
> they refer to the same memory region.
"same bit positions in the register".
(No need to spin a v3
A placeholder of ~0 is used to indicate variable payload size.
Whilst the checks for output payload correctly took this into
account, those for input payload did not.
This results in failure of the Set LSA command.
Fixes: 464e14ac43 ("hw/cxl/device: Implement basic mailbox (8.2.8.4)")
There is no checking on the availability of a write callback.
Hence QEMU crashes if a write does occur to one of these regions.
Discovered whilst chasing a Linux kernel bug that incorrectly
wrote into one of these regions.
Fixes: 6364adacdf ("hw/cxl/device: Implement the CAP array (8.2.8.1-2)")
Right now translator stops right *after* the end of a page, which
breaks reporting of fault locations when the last instruction of a
multi-insn translation block crosses a page boundary.
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Richard Henderson
---
target/s390x/tcg/translate.c | 15
Hi,
I noticed that when we get a SEGV due to jumping to non-readable
memory, sometimes si_addr and program counter in siginfo_t are slightly
off. I tracked this down to the assumption that translators stop before
the end of a page, while in reality they may stop right after it.
Patch 1 fixes an
This device is shared between different 4xx socs.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc4xx_devs.c| 12 ++--
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 6 +++---
5 files changed, 12
From: Cédric Le Goater
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Signed-off-by: Cédric Le Goater
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 21 +++
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10 --
hw/ppc/ppc405_uc.c | 11
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_uc.c | 49 +-
The PLB is shared between 405 and 440 so move it to the shared file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 11 -
hw/ppc/ppc405_uc.c | 93
hw/ppc/ppc4xx_devs.c| 94 +
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no
need to clear its elements. In the bamboo machine init memset can be
replaced with array initialiser which is shorter.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 6 ++
hw/ppc/ppc4xx_devs.c | 8 ++--
2
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 2aac8a3fe9..2bd5e41140 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -51,7 +51,7 @@
#define
From: Alex Bennée
The assert() protecting against leakage is a little aggressive and
causes needless crashes if a device is shutdown without having been
configured. In this case no descriptors are lost because none have
been assigned.
Signed-off-by: Alex Bennée
Message-Id:
On Wed, 17 Aug 2022 at 15:49, Nikita Ivanov wrote:
>
> Well...
>
> What exactly is still under discussion? In my perspective, the main pitfalls
> have been resolved:
>
> 0. All possible places where TFR() macro could be applied are covered.
> 1. Macro has been renamed in order to be more
If a guest sets up bad descriptors, it could force QEMU to access
non-existing memory regions. Thus we should check the return value
of dma_memory_read/write() to make sure that these errors don't go
unnoticed.
Signed-off-by: Thomas Huth
---
hw/usb/hcd-xhci.c | 64
On Wed, Aug 17, 2022 at 12:12:03PM -0400, Michael S. Tsirkin wrote:
> The following changes since commit c7208a6e0d049f9e8af15df908168a79b1f99685:
>
> Update version for v7.1.0-rc3 release (2022-08-16 20:45:19 -0500)
>
> are available in the Git repository at:
>
>
Hi,
On Tue, Jul 05, 2022 at 08:46:34AM -0700, Andrea Bolognani wrote:
> I've commented in detail to the single patches, just a couple of
> additional points.
>
> On Fri, Jun 17, 2022 at 02:19:24PM +0200, Victor Toso wrote:
> > * 7) Flat structs by removing embed types. Discussion with Andrea
> >
On 17/08/2022 05.46, Bin Meng wrote:
Current project timeout is 1 hour, but the check-gprof-gcov job never
completes within 1 hour. Increase the job timeout to 90 minutes.
Signed-off-by: Bin Meng
---
.gitlab-ci.d/buildtest.yml | 1 +
1 file changed, 1 insertion(+)
diff --git
The recent addition of CXL Region setup to the 6.0-rc1 Linux kernel
has allowed us to test a few paths that weren't exercised fully until
now. That threw up a mixture of bugs in QEMU emulation and the kernel
(kernel fixes already posted).
The first patch is down to a wrong assumption about RO
Get LSA needs 4 byte offset and 4 byte length arguments.
CXL rev 2.0 Table 178.
Fixes: 3ebe676a34 ("hw/cxl/device: Implement get/set Label Storage Area (LSA)")
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add x86_64 and s390x tests to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/multiarch/noexec.h | 114
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/noexec.c | 145 +++
This device is shared between different 4xx socs.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 2 +-
hw/ppc/ppc405_uc.c | 2 +-
hw/ppc/ppc4xx_devs.c| 12 ++--
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 6 +++---
5 files changed, 12
From: Cédric Le Goater
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 12 +++
hw/ppc/ppc405_uc.c | 49
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 4 +---
hw/ppc/ppc405_uc.c | 10
This helper will be reused in the next patch for duplications check.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 83 ++-
1 file changed, 53 insertions(+), 30 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index
Fill the image with a pattern to generate entries in the BAT,
set the first BAT entry outside the image, try to read the corrupted image,
repair and check for zeroes in the first cluster.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/tests/parallels-checks | 78 +++
The following changes since commit c7208a6e0d049f9e8af15df908168a79b1f99685:
Update version for v7.1.0-rc3 release (2022-08-16 20:45:19 -0500)
are available in the Git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
for you to fetch changes up to
From: Alex Bennée
As reads happen in the callback we were never seeing them. We only
really care about the header so move the tracepoint to when the header
is complete.
Fixes: 6ca6d8ee9d (hw/virtio: add vhost_user_[read|write] trace points)
Signed-off-by: Alex Bennée
Acked-by: Jason Wang
From: Stefan Hajnoczi
As soon as virtio_scsi_data_plane_start() attaches host notifiers the
IOThread may start virtqueue processing. There is a race between
IOThread virtqueue processing and virtio_scsi_data_plane_start() because
it only assigns s->dataplane_started after attaching host
For consistency, function "update_rx_fifo()" should use
the RX FIFO register names, not the TX FIFO ones even if
they refer to the same memory region.
Signed-off-by: Anton Kochkov
Reviewed-by: Francisco Iglesias
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1123
---
Well...
What exactly is still under discussion? In my perspective, the main
pitfalls have been resolved:
0. All possible places where TFR() macro could be applied are covered.
1. Macro has been renamed in order to be more transparent. The name has
been chosen in comparison with a similar glibc
Currently it's possible to execute pages that do not have PAGE_EXEC if
there is an existing translation block. Fix by clearing tb_jmp_cache,
which forces HELPER(lookup_tb_ptr)() to recheck permission bits the
next time.
Signed-off-by: Ilya Leoshkevich
---
linux-user/mmap.c | 14 ++
From: Cédric Le Goater
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model
From: Cédric Le Goater
POB is currently modeled as a simple DCR device.
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 12 ++
hw/ppc/ppc405_uc.c | 56 ++
2 files
Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed
to vf[w]redusum_vs. The distinction between ordered and unordered is also
more consistent with other instructions, although there is no difference
in implementation between the two for QEMU.
Signed-off-by: Yang Liu
---
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405_uc.c | 5 +++--
hw/ppc/ppc440_bamboo.c | 27 ++--
hw/ppc/ppc440_uc.c | 3 ++-
hw/ppc/ppc4xx_devs.c | 48 +++---
hw/ppc/ppc4xx_pci.c| 31 +--
5 files
On Tue, 16 Aug 2022, Cédric Le Goater wrote:
On 8/13/22 17:34, BALATON Zoltan wrote:
Hello,
This is mased on gitlab.com/danielhb/qemu/tree/ppc-7.2
This series contains the rest of Cédric's patches modified according
my review comments and some other small clean ups I've noticed along
the way.
Hi Dan,
Responding on behalf of Shivi.
>> "So what does the "PCIe RC support" means? the BMC will be the PCIe RC?"
Yes, BMC will be the PCIe RC to control downstream PCIe devices (end-points).
- Amit
-Original Message-
From: Dan Zhang
Sent: 15 August 2022 11:18
To: Cédric Le Goater
Remove duplicate code by wrapping vfwredsum_vs's OP function.
Signed-off-by: Yang Liu
---
target/riscv/vector_helper.c | 56 +++-
1 file changed, 10 insertions(+), 46 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
Deduplicate code by using highest_offset() helper.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index bd129f44fa..93d21804f2 100644
--- a/block/parallels.c
+++
Fill the image with a pattern and write another pattern
in the second cluster. Corrupt the image and check if the pattern
changes. Repair the image and check the patterns on guest
and host sides.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/tests/parallels-checks | 31
Replace hardcoded numbers by variables.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/131 | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/tests/qemu-iotests/131 b/tests/qemu-iotests/131
index a847692b4c..601546c84c 100755
---
Hi,
On Wed, Jul 06, 2022 at 04:28:16AM -0500, Andrea Bolognani wrote:
> On Tue, Jul 05, 2022 at 05:35:26PM +0100, Daniel P. Berrangé wrote:
> > On Tue, Jul 05, 2022 at 08:45:30AM -0700, Andrea Bolognani wrote:
> > > All this string manipulation looks sketchy. Is there some reason that
> > > I'm
On 8/17/22 09:07, Ilya Leoshkevich wrote:
Oh my. Well, we could
(1) revert that patch because the premise is wrong,
(2) go with your per-tb clearing,
(3) clear the whole thing with cpu_tb_jmp_cache_clear
Ideally we'd have some benchmark numbers to inform the choice...
FWIW 6f1653180f570
From: Gerd Hoffmann
Causes regressions when doing direct kernel boots with OVMF.
At this point in the release cycle the only sensible action
is to just disable this for 7.1 and sort it properly in the
7.2 devel cycle.
Cc: Jason A. Donenfeld
Cc: Marcel Apfelbaum
Cc: Paolo Bonzini
Cc: Richard
I2 is 16 bits, not 32.
Found by running valgrind's none/tests/s390x/traps.
Fixes: 1c2687518235 ("target-s390: Implement COMPARE AND TRAP")
Signed-off-by: Ilya Leoshkevich
---
target/s390x/tcg/insn-data.def | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Alex Bennée
I've noticed asserts firing because we query the status of vdev after
a vhost connection is closed down. Rather than faulting on the NULL
indirect just quietly reply false.
Signed-off-by: Alex Bennée
Message-Id: <20220728135503.1060062-3-alex.ben...@linaro.org>
Reviewed-by:
Hi,
On Tue, Jul 05, 2022 at 05:49:22PM +0100, Daniel P. Berrangé wrote:
> On Tue, Jul 05, 2022 at 08:46:21AM -0700, Andrea Bolognani wrote:
> > On Fri, Jun 17, 2022 at 02:19:31PM +0200, Victor Toso wrote:
> > > +type EmptyCommandReturn struct {
> > > +CommandId string
From: Cédric Le Goater
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes, add finalize method]
Signed-off-by:
Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu
link and make it uniform with the other PPC4xx devices.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
hw/intc/ppc-uic.c | 26 ++
hw/ppc/ppc405_uc.c| 6 ++
From: Cédric Le Goater
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 16 ++
hw/ppc/ppc405_uc.c | 77
From: Cédric Le Goater
EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 17 -
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. This is needed when booting a kernel directly from -kernel
without a firmware. Do this from board code accesing normal SDRAM
controller registers
From: Cédric Le Goater
The DMA controller is currently modeled as a DCR device with a couple
of IRQs.
Signed-off-by: Cédric Le Goater
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 19 ++
hw/ppc/ppc405_uc.c | 141
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 37e3b87c2e..27ebbb2ffc 100644
--- a/hw/ppc/ppc4xx_devs.c
+++
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
[balaton: Simplify sysbus device casts for readability]
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 3 ++-
hw/ppc/ppc405_uc.c | 28 ++--
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git
Cluster offsets must be unique among all BAT entries.
Find duplicate offsets in the BAT.
If a duplicated offset is found fix it by copying the content
of the relevant cluster to a new allocated cluster and
set the new cluster offset to the duplicated entry.
Add host_cluster_index() helper to
The BDRVParallelsState structure contains data_end field that
is measured in sectors.
In parallels_open() initially this field is set by data_off field from
parallels image header.
According to the parallels format documentation,
data_off field contains an offset, in sectors, from the start of
All the offsets in the BAT must be at least one cluster away from
the end of the data area.
Fix the check condition for correct check.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/parallels.c b/block/parallels.c
This patchset depends on the patchset
[PATCH v3 0/8] parallels: Refactor the code of images checks and fix a bug
Fix an incorrect condition in out-of-image check and
incorrect data end calculation in parallels_open().
Add parallels_handle_leak() and highest_offset() helpers.
Add checking and
In this test cluster size is 64k, but modern tools generate images
with cluster size 1M.
Calculate cluster size using track field from image header.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/131 | 5 -
tests/qemu-iotests/131.out | 44 +++---
From: Jonathan Cameron
Get LSA needs 4 byte offset and 4 byte length arguments.
CXL rev 2.0 Table 178.
Fixes: 3ebe676a34 ("hw/cxl/device: Implement get/set Label Storage Area (LSA)")
Signed-off-by: Jonathan Cameron
Message-Id: <20220817145759.32603-3-jonathan.came...@huawei.com>
Reviewed-by:
virtio level reset should not affect pci express
registers such as PM, error or link.
Fixes: 27ce0f3afc ("hw/virtio: fix Power Management Control Register for PCI
Express virtio devices")
Fixes: d584f1b9ca ("hw/virtio: fix Link Control Register for PCI Express virtio
devices")
Fixes: c2cabb3422
From: Igor Mammedov
OSK value is irrelevant for ACPI test case.
Supply fake OSK explicitly to prevent QEMU complaining about
invalid key when it fallbacks to default_osk.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Igor Mammedov
Message-Id: <20220728133713.1369596-1-imamm...@redhat.com>
On 8/17/22 10:05, Ilya Leoshkevich wrote:
Hi,
I noticed that when we get a SEGV due to jumping to non-readable
memory, sometimes si_addr and program counter in siginfo_t are slightly
off. I tracked this down to the assumption that translators stop before
the end of a page, while in reality they
On Thu, 11 Aug 2022 17:46:55 -0700
Dan Williams wrote:
> Dan Williams wrote:
> > Bobo WL wrote:
> > > Hi Dan,
> > >
> > > Thanks for your reply!
> > >
> > > On Mon, Aug 8, 2022 at 11:58 PM Dan Williams
> > > wrote:
> > > >
> > > > What is the output of:
> > > >
> > > > cxl list -MDTu
From: Jonathan Cameron
A placeholder of ~0 is used to indicate variable payload size.
Whilst the checks for output payload correctly took this into
account, those for input payload did not.
This results in failure of the Set LSA command.
Fixes: 464e14ac43 ("hw/cxl/device: Implement basic
On Wed, 17 Aug 2022 at 15:06, Nikita Ivanov wrote:
>
> Hi! Are there any updates? I have not received any comments since the last
> email.
Looking at the thread, I don't think we (yet) have consensus on the
right thing to do here...
thanks
-- PMM
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