On Tue, 20 Sept 2022 at 19:46, Jian Zhang wrote:
>
> Implement a simple latching switch device.
>
> The latching switch is a switch that can be turned on and off.
> When the input new state and match the trigger edge, the switch
> state will be toggled.
>
> This device privide 2 properties
Add support for saving/restoring extended save states when signals
are delivered. This allows using AVX, MPX or PKRU registers in
signal handlers. The patch follows the Linux ABI.
Signed-off-by: Paolo Bonzini
---
linux-user/i386/signal.c | 115 +--
These three patches add support for x86 XSAVE/XRSTOR signal frames in
linux-user emulation. This ensures that signals save and restore the
extended save states as well.
For 32-bit emulation not even FXSAVE was used, even though the
signal frame supports it. Therefore, patch 2 extends 32-bit
Linux can use FXSAVE to save/restore XMM registers even on 32-bit
systems. This requires some care in order to keep the FXSAVE area
aligned to 16 bytes; for this reason, get_sigframe is changed to
pass the offset into the FXSAVE area rather than the full frame
size.
Signed-off-by: Paolo Bonzini
Recent versions of Linux moved the 32-bit fpstate towards the end of the
frame, so that the variable-sized xsave data does not overwrite the
(ABI-defined) extramask[] field. Follow suit in QEMU.
Signed-off-by: Paolo Bonzini
---
linux-user/i386/signal.c | 11 +--
1 file changed, 9
On 9/17/22 00:43, Song Gao wrote:
We can use alternate stack, so that we can use sp register as intput/ouput
register.
I had tested aarch64/LoongArch architecture.
Signed-off-by: Song Gao
---
risu.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
Good idea.
On 10/10/22 06:16, Peter Maydell wrote:
The doc also says that we (as fake EL3) should be setting
SMCR_EL3.LEN to the same value for all CPUs. Currently we do
do that, but it's always the reset value of 0. Richard: does
that have any odd effects (I have a feeling it clamps the
VL to the minimum
On 10/10/22 02:49, Peter Maydell wrote:
On Sat, 8 Oct 2022 at 16:38, Richard Henderson
wrote:
Intel has now given guarantees about the atomicity of SSE read
and write instructions on cpus supporting AVX. We can use these
instead of the much slower cmpxchg16b.
Derived from
On Thu, Oct 6, 2022 at 10:35 PM Stefan Hajnoczi wrote:
> Avoid bounce buffers when QEMUIOVector elements are within previously
> registered bdrv_register_buf() buffers.
>
> The idea is that emulated storage controllers will register guest RAM
> using bdrv_register_buf() and set the
Daniel P. Berrangé writes:
> On Tue, Oct 04, 2022 at 02:01:12PM +0100, Alex Bennée wrote:
>> From: Paolo Bonzini
>>
>> s390-ccw remains a bit more complex, because the -march=z900 test is done
>> only for the native cross compiler. Otherwise, all that is needed is
>> to pass the (now
To facilitate easier implementaiton of the 'fixed-ram' migration restore
factor out the code responsible for parsing the ramblocks headers. This
also makes ram_load_precopy easier to comprehend.
Signed-off-by: Nikolay Borisov
---
migration/ram.c | 142
This commit introduces the minimum code necessary to support parsing
migration strems with 'fixed-ram' capability set. The only thing really
missing is the implementation of write_or_dump_fixed_ram() which deals
with '-x'/'-m' options.
Signed-off-by: Nikolay Borisov
---
Add a bunch of auxiliarry methods and a feature flag to work with
SEEKABLE channels. Currently the only channel considered seekable is
QIOChannelFile. Also add a bunch of helper functions to QEMUFile that
can make use of this channel feature. All of this is in prepration for
supporting
preadv is going to be needed when 'fixed-ram'-enabled stream are to be
restored. Simply add a wrapper around preadv that's specific to
QIOChannelFile.
Signed-off-by: Nikolay Borisov
---
include/io/channel-file.h | 5 +
io/channel-file.c | 26 ++
2 files
Here's a slightly updated version of the patchset. In its core it remains
however I have addressed a couple of issue, namely :
* Don't initialize the shadow bitmap as all set - this was causing the full ram
to be copied always.
* Fixed a memory leak in parse_ramblocks_fixed_ram by making the
This is a counterpart to the 'file:' uri support for source migration,
now a file can also serve as the source of an incoming migration.
Signed-off-by: Nikolay Borisov
---
migration/file.c | 15 +++
migration/file.h | 1 +
migration/migration.c | 2 ++
3 files changed,
The upcoming 'fixed-ram' feature would require qemu to write data at
specific offsets of the file. This is currently missing so this patch
adds it. I've chosen to implement it as a type-specific function rather
than plumb it through the generic channel interface as it relies on
being able to do
Implement 'fixed-ram' feature. The core of the feature is to ensure that
each ram page of the migration stream has a specific offset in the
resulting migration stream. The reason why we'd want such behavior are
two fold:
- When doing a 'fixed-ram' migration the resulting file will have a
This is required so that migration stream configuration is written
to the migration stream. This would allow analyze-migration to
parse enabled capabilities for the migration and adjust its behavior
accordingly. This is in preparation for analyze-migration.py to support
'fixed-ram' capability
Restoring a 'fixed-ram' enabled migration stream would require reading
from specific offsets in the file so add a helper to QEMUFile that uses
the newly introduced qio_channel_file_preadv.
Signed-off-by: Nikolay Borisov
---
migration/qemu-file.c | 23 +++
Add the necessary code to parse the format changes for 'fixed-ram'
capability. One of the more notable changes in behavior is that in the
'fixed-ram' case ram pages are restored in one go rather than constantly
looping through the migration stream. Also due to idiosyncrasies of the
format I have
Implement support for a "file:" uri so that a migration can be initiated
directly to a file from QEMU.
Signed-off-by: Nikolay Borisov
---
migration/file.c | 23 +++
migration/file.h | 9 +
migration/meson.build | 1 +
migration/migration.c | 3 +++
4
Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI
specification adding the field "Hypervisor Vendor Identity" that was missing.
This field's description states the following: "64-bit identifier of hypervisor
vendor. All bytes in this field are considered part of the
Step 6 & 7 of the bios-tables-test.c documented procedure.
Differences between disassembled ASL files for MADT:
@@ -11,9 +11,9 @@
*/
[000h 4]Signature : "APIC"[Multiple APIC
Description Table (MADT)]
-[004h 0004 4] Table Length : 00A8
The MADT table structure has been updated in commit 37f33084ed2e
("acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MADT
table")
to include the 5.2.12.18 GIC ITS Structure and so table's revision also needs
to
be updated. MADT and the FADT tables from the
MADT has been updated with the GIC Structures from ACPI 6.0 Errata A
and so MADT revision and GICC Structure must be updated also.
Fixes: 37f33084ed2e ("acpi: arm/virt: madt: use build_append_int_noprefix() API
to compose MADT table")
Signed-off-by: Miguel Luis
Reviewed-by: Ani Sinha
---
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis
---
tests/qtest/bios-tables-test-allowed-diff.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index
On Mon, 10 Oct 2022 at 14:16, Peter Maydell wrote:
>
> On Mon, 3 Oct 2022 at 15:57, Jerome Forissier
> wrote:
> >
> > According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
> > SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
> > is advertised. This has to be
On Mon, 3 Oct 2022 at 15:57, Jerome Forissier
wrote:
>
> According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
> SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
> is advertised. This has to be taken care of when QEMU boots directly
> into the kernel (i.e., "-M
On Sat, 1 Oct 2022 at 17:24, Richard Henderson
wrote:
>
> This is a major reorg to arm page table walking. While the result
> here is "merely" Hardware-assited Access Flag and Dirty Bit Setting
> (HAFDBS), the ultimate goal is the Realm Management Extension (RME).
> RME "recommends" that HAFDBS
On Mon, Oct 10, 2022 at 01:54:16PM +0100, Daniel P. Berrangé wrote:
> On Tue, Oct 04, 2022 at 02:01:12PM +0100, Alex Bennée wrote:
> > From: Paolo Bonzini
> >
> > s390-ccw remains a bit more complex, because the -march=z900 test is done
> > only for the native cross compiler. Otherwise, all
Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben:
> No functional change intended.
>
> Signed-off-by: Emanuele Giuseppe Esposito
Reviewed-by: Kevin Wolf
Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben:
> No functional changes intended.
>
> Signed-off-by: Emanuele Giuseppe Esposito
Reviewed-by: Kevin Wolf
Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben:
> Together with all _can_set_ and _set_ APIs, as they are not needed
> anymore.
>
> Signed-off-by: Emanuele Giuseppe Esposito
Reviewed-by: Kevin Wolf
Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben:
> Replace all direct usage of ->can_set_aio_ctx and ->set_aio_ctx,
> and call bdrv_child_try_change_aio_context() in
> bdrv_try_set_aio_context(), the main function called through
> the whole block layer.
>
> From this point
On Tue, Oct 04, 2022 at 02:01:12PM +0100, Alex Bennée wrote:
> From: Paolo Bonzini
>
> s390-ccw remains a bit more complex, because the -march=z900 test is done
> only for the native cross compiler. Otherwise, all that is needed is
> to pass the (now mandatory) target argument to
Hi,
> > > > Given newer processors have more than 40 and for older ones we know
> > > > the possible values for the two relevant x86 vendors we could do
> > > > something along the lines of:
> > > >
> > > >phys-bits >= 41 -> valid
> > > >phys-bits == 40+
On Fri, 7 Oct 2022 at 17:53, Richard Henderson
wrote:
>
> On 10/7/22 09:20, Peter Maydell wrote:
> >> -/* Check if IPA translates to secure or non-secure PA space.
> >> */
> >> -if (is_secure) {
> >> -if (ipa_secure) {
> >> -
On 06.10.22 23:35, Stefan Hajnoczi wrote:
Make list traversal work when a callback removes a notifier
mid-traversal. This is a cleanup to prevent bugs in the future.
Signed-off-by: Stefan Hajnoczi
---
hw/core/numa.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
On 10.10.22 12:40, Dr. David Alan Gilbert wrote:
* David Hildenbrand (da...@redhat.com) wrote:
This is a follow-up on "util: NUMA aware memory preallocation" [1] by
Michal.
Setting the CPU affinity of threads from inside QEMU usually isn't
easily possible, because we don't want QEMU -- once
On Mon, 10 Oct 2022 at 11:54, Peter Maydell wrote:
>
> On Thu, 6 Oct 2022 at 14:16, Peter Maydell wrote:
> >
> > On Fri, 30 Sept 2022 at 00:23, Jason A. Donenfeld wrote:
> > >
> > > When the system reboots, the rng-seed that the FDT has should be
> > > re-randomized, so that the new boot gets a
>-Original Message-
>From: Dr. David Alan Gilbert
>Sent: Monday, October 10, 2022 6:35 PM
>To: Duan, Zhenzhong
>Cc: qemu-devel@nongnu.org; quint...@redhat.com
>Subject: Re: [PATCH] migration: Fix the minus value for compressed_size
>
>* Zhenzhong Duan (zhenzhong.d...@intel.com) wrote:
On Thu, 6 Oct 2022 at 14:16, Peter Maydell wrote:
>
> On Fri, 30 Sept 2022 at 00:23, Jason A. Donenfeld wrote:
> >
> > When the system reboots, the rng-seed that the FDT has should be
> > re-randomized, so that the new boot gets a new seed. Several
> > architectures require this functionality,
Hi Cedric,
On [2022 Oct 10] Mon 11:58:40, Michael Walle wrote:
> Am 2022-10-10 08:23, schrieb Cédric Le Goater:
> > On 10/7/22 16:44, Francisco Iglesias wrote:
>
> > > > --- a/hw/block/m25p80.c
> > > > +++ b/hw/block/m25p80.c
> > > > @@ -234,6 +234,8 @@ static const FlashPartInfo
Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben:
> bdrv_child_cb_change_aio_ctx() is identical to
> bdrv_child_cb_can_set_aio_ctx(), as we only need
> to recursively go on the parent bs.
>
> Note: bdrv_child_try_change_aio_context() is not called by
> anyone at this point.
>
>
Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben:
> blk_root_change_aio_ctx() is very similar to blk_root_can_set_aio_ctx(),
> but implements a new transaction so that if all check pass, the new
> transaction's .commit will take care of changing the BlockBackend
> AioContext.
Am 25.07.2022 um 14:21 hat Emanuele Giuseppe Esposito geschrieben:
> child_job_change_aio_ctx() is very similar to
> child_job_can_set_aio_ctx(), but it implements a new transaction
> so that if all check pass, the new transaction's .commit()
> will take care of changin the BlockJob AioContext.
>
* David Hildenbrand (da...@redhat.com) wrote:
> This is a follow-up on "util: NUMA aware memory preallocation" [1] by
> Michal.
>
> Setting the CPU affinity of threads from inside QEMU usually isn't
> easily possible, because we don't want QEMU -- once started and running
> guest code -- to be
* Zhenzhong Duan (zhenzhong.d...@intel.com) wrote:
> When update_compress_thread_counts() is called first time, there is
> no data stream yet. We see compression_counters.compressed_size
> becomes minus value shortly.
>
> Signed-off-by: Zhenzhong Duan
> ---
> migration/ram.c | 4
> 1 file
On Fri, 7 Oct 2022 16:21:51 +0100
Jonathan Cameron wrote:
> Whilst I have carried on Huai-Cheng Kuo's series version numbering and
> naming, there have been very substantial changes since v6 so I would
> suggest fresh review makes sense for anyone who has looked at this before.
> In particularly
Am 2022-10-10 08:23, schrieb Cédric Le Goater:
On 10/7/22 16:44, Francisco Iglesias wrote:
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -234,6 +234,8 @@ static const FlashPartInfo known_devices[] = {
{ INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
{
On Mon, 10 Oct 2022 at 09:34, Nikita Ivanov wrote:
>
> Hi! Thanks for your notes. I'll try to send updated patches by the end of the
> day.
>
> On Fri, Oct 7, 2022 at 6:32 PM Peter Maydell wrote:
>> I'm not sure why you've put the TEMP_FAILURE_RETRY on the outside here
>> rather than just on
On Thu, Oct 6, 2022 at 10:35 PM Stefan Hajnoczi wrote:
> v6:
> - Add untested nvme-io_uring driver. Please test in your nested NVMe
> environment, Alberto. [Alberto]
I did some I/O verification using fio [1] and it seems to be working fine.
Alberto
[1]
On Sat, 8 Oct 2022 at 16:38, Richard Henderson
wrote:
>
> Intel has now given guarantees about the atomicity of SSE read
> and write instructions on cpus supporting AVX. We can use these
> instead of the much slower cmpxchg16b.
>
> Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
On Mon, Oct 10, 2022 at 01:43:21PM +0530, Ani Sinha wrote:
> On Mon, Oct 10, 2022 at 1:24 PM Ani Sinha wrote:
> >
> > Please see the README file added in patch 10 for more details.
> > Sample runs are as follows:
> >
> > $ ./tests/venv/bin/avocado run -t acpi tests/avocado --tap -
> > ERROR:
When update_compress_thread_counts() is called first time, there is
no data stream yet. We see compression_counters.compressed_size
becomes minus value shortly.
Signed-off-by: Zhenzhong Duan
---
migration/ram.c | 4
1 file changed, 4 insertions(+)
diff --git a/migration/ram.c
On Mon, Oct 10, 2022 at 2:50 PM Daniel P. Berrangé wrote:
>
> On Mon, Oct 10, 2022 at 01:43:21PM +0530, Ani Sinha wrote:
> > On Mon, Oct 10, 2022 at 1:24 PM Ani Sinha wrote:
> > >
> > > Please see the README file added in patch 10 for more details.
> > > Sample runs are as follows:
> > >
> > > $
On Sun, Sep 25, 2022 at 10:45 PM Mauro Matteo Cascella
wrote:
>
> Extended ClientCutText messages start with a 4-byte header. If len < 4,
> an integer underflow occurs in vnc_client_cut_text_ext. The result is
> used to decompress data in a while loop in inflate_buffer, leading to
> CPU
在 2022/9/30 10:45, Song Gao 写道:
Hi,
This series fix some bugs find from RISU test.
V3:
-drop patch set some instruction result high 32bit 1.
-follow some change from Richard's suggestion.
v2:
-remove patch5 div if x/0 set dividend to 0.
Song Gao (3):
target/loongarch:
On 10/10/2022 11.13, Ani Sinha wrote:
On Mon, Oct 10, 2022 at 2:26 PM Thomas Huth wrote:
On 10/10/2022 10.13, Ani Sinha wrote:
On Mon, Oct 10, 2022 at 1:24 PM Ani Sinha wrote:
Please see the README file added in patch 10 for more details.
Sample runs are as follows:
$
Let's make it easier to pin threads created via a ThreadContext to
all CPUs currently belonging to a given set of NUMA nodes -- which is the
common case.
"node-affinity" is simply a shortcut for setting "cpu-affinity" manually
to the list of CPUs belonging to the set of nodes. This property can
Usually, we let upper layers handle CPU pinning, because
pthread_setaffinity_np() (-> sched_setaffinity()) is blocked via
seccomp when starting QEMU with
-sandbox enable=on,resourcecontrol=deny
However, we want to configure and observe the CPU affinity of threads
from QEMU directly in some
Currently, there is no way to configure a CPU affinity inside QEMU when
the sandbox option disables it for QEMU as a whole, for example, via:
-sandbox enable=on,resourcecontrol=deny
While ThreadContext objects can be created on the QEMU commandline and
the CPU affinity can be configured
... and implement it under POSIX. When a ThreadContext is provided,
create new threads via the context such that these new threads obtain a
porperly configured CPU affinity.
Reviewed-by: Michal Privoznik
Signed-off-by: David Hildenbrand
---
backends/hostmem.c | 5 +++--
Setting the CPU affinity of QEMU threads is a bit problematic, because
QEMU doesn't always have permissions to set the CPU affinity itself,
for example, with seccomp after initialized by QEMU:
-sandbox enable=on,resourcecontrol=deny
General information about CPU affinities can be found in the
This is a follow-up on "util: NUMA aware memory preallocation" [1] by
Michal.
Setting the CPU affinity of threads from inside QEMU usually isn't
easily possible, because we don't want QEMU -- once started and running
guest code -- to be able to mess up the system. QEMU disallows relevant
syscalls
Let's
* give the function a "qemu_*" style name
* make sure the parameters in the implementation match the prototype
* rename smp_cpus to max_threads, which makes the semantics of that
parameter clearer
... and add a function documentation.
Reviewed-by: Michal Privoznik
Signed-off-by: David
在 2022/10/6 19:11, Philippe Mathieu-Daudé 写道:
On 6/10/22 12:07, WANG Xuerui wrote:
Previously the 32-bit version was incorrectly chosen, leading to funny
but incorrect output from e.g. df(1). Simply select the version
corresponding to the 64-bit asm-generic definition.
For reference, this
On Mon, Oct 10, 2022 at 2:26 PM Thomas Huth wrote:
>
> On 10/10/2022 10.13, Ani Sinha wrote:
> > On Mon, Oct 10, 2022 at 1:24 PM Ani Sinha wrote:
> >>
> >> Please see the README file added in patch 10 for more details.
> >> Sample runs are as follows:
> >>
> >> $ ./tests/venv/bin/avocado run -t
在 2022/9/30 17:51, Xiaojuan Yang 写道:
This series add memmap table and fix extioi, ipi device
emulation for LoongArch virt machine.
Changes for v4:
Add 'reviewed-by' tag in fixing ipi patch, and other changes
are the same as v3.
1. Remove the memmap table patch in this series, it
will
Let's allow for specifying a thread context via the "prealloc-context"
property. When set, preallcoation threads will be crated via the
thread context -- inheriting the same CPU affinity as the thread
context.
Pinning preallcoation threads to CPUs can heavily increase performance
in NUMA setups,
On 10/10/2022 10.13, Ani Sinha wrote:
On Mon, Oct 10, 2022 at 1:24 PM Ani Sinha wrote:
Please see the README file added in patch 10 for more details.
Sample runs are as follows:
$ ./tests/venv/bin/avocado run -t acpi tests/avocado --tap -
ERROR: Missing parentheses in call to 'print'. Did
On Mon, Oct 10, 2022 at 06:56:51AM +, Dennis Clarke wrote:
>
> re: https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg01249.html
>
> Using GCC 12 is even worse :
>
> [2040/6841] Compiling C object qemu-system-aarch64.p/softmmu_main.c.o
> [2041/6841] Linking target
On Fri, Oct 07, 2022 at 06:27:29PM -0400, Brad Smith wrote:
> On 10/7/2022 4:33 PM, Warner Losh wrote:
> >
> >
> > On Fri, Oct 7, 2022 at 1:21 AM Brad Smith wrote:
> >
> > tests: Add sndio to the FreeBSD CI containers / VM
> >
> > ---
> > .gitlab-ci.d/cirrus/freebsd-12.vars
Always use the native CHS device parameters for the ATA commands READ
NATIVE MAX ADDRESS and READ NATIVE MAX ADDRESS EXT, not those limited
by the ATA command INITIALIZE_DEVICE_PARAMETERS (introduced in patch
176e4961, hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS
command, 2022-07-07.)
On 10/9/22 08:08, WANG Xuerui wrote:
User space has been preferring this syscall for a while, due to its
closer match with C semantics, and newer platforms such as LoongArch
apparently have libc implementations that don't fallback to faccessat
so normal access checks are failing without the
Verify that the ATA command READ NATIVE MAX ADDRESS returns the last
valid CHS tuple for the native device rather than any limit
established by INITIALIZE DEVICE PARAMETERS.
Signed-off-by: Lev Kujawski
---
tests/qtest/ide-test.c | 47 +-
1 file changed,
On Sat, Sep 24, 2022 at 10:48:15PM +0800, Sam Li wrote:
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1193
The commit "Use io_uring_register_ring_fd() to skip fd operations" broke
when booting a guest with iothread and io_uring. That is because the
io_uring_register_ring_fd() call is
On Sat, Oct 08, 2022 at 08:35:47PM +0300, Jarkko Sakkinen wrote:
> On Sat, Oct 08, 2022 at 07:15:17PM +0300, Jarkko Sakkinen wrote:
> > On Sat, Oct 08, 2022 at 12:54:32AM +0300, Jarkko Sakkinen wrote:
> > > On Fri, Oct 07, 2022 at 02:58:54PM +, Sean Christopherson wrote:
> > > > On Fri, Oct
On Thu, Oct 06, 2022 at 09:55:31AM +0100, Fuad Tabba wrote:
> Hi,
>
> On Thu, Sep 15, 2022 at 3:37 PM Chao Peng wrote:
> >
> > Expose KVM_MEM_PRIVATE and memslot fields private_fd/offset to
> > userspace. KVM will register/unregister private memslot to fd-based
> > memory backing store and
On Tue, Oct 04, 2022 at 05:55:28PM +0300, Jarkko Sakkinen wrote:
> On Thu, Sep 15, 2022 at 10:29:13PM +0800, Chao Peng wrote:
> > Expose KVM_MEM_PRIVATE and memslot fields private_fd/offset to
> > userspace. KVM will register/unregister private memslot to fd-based
> > memory backing store and
Hi! Thanks for your notes. I'll try to send updated patches by the end of
the day.
On Fri, Oct 7, 2022 at 6:32 PM Peter Maydell
wrote:
> I think this patch is doing things in the wrong order. Instead of
> converting code to use the old macro that we don't like and then
> updating it again in
Add a README file that describes the purpose of the various test files and gives
guidance to developers on where and how to make changes.
Cc: Daniel P. BerrangÃ"
Cc: Paolo Bonzini
Cc: Maydell Peter
Cc: John Snow
Cc: Thomas Huth
Signed-off-by: Ani Sinha
---
tests/avocado/acpi-bits/README |
On Mon, Oct 10, 2022 at 1:24 PM Ani Sinha wrote:
>
> Please see the README file added in patch 10 for more details.
> Sample runs are as follows:
>
> $ ./tests/venv/bin/avocado run -t acpi tests/avocado --tap -
> ERROR: Missing parentheses in call to 'print'. Did you mean print(...)?
>
I wrote the biosbits avocado tests for testing QEMU's ACPI/SMBIOS implementation
with biosbits and all the related changes. Making myself as the maintainer for
biosbits related files and test scripts.
Cc: Daniel P. Berrangé
Cc: Paolo Bonzini
Cc: Maydell Peter
Cc: John Snow
Cc: Thomas Huth
This is initial commit of cpuid, acpi and smbios python test scripts for
biosbits to execute. No change has been made to them from the original code
written by the biosbits author Josh Triplett. They are required to be installed
into the bits iso file and then run from within the virtual machine
smilatency test is latency sensitive and does not pass deterministically when
run in QEMU environment under biosbits. Disable the test suite for now.
Example failure:
SMI latency test
Warning: touching the keyboard can affect the results of this test.
Starting test. Wait here, I will
smilatency tests does not reliably pass every time it is run from QEMU. This
change adds the test file unchanged from bits so that the next change can
disable the test.
Cc: Daniel P. Berrangé
Cc: Paolo Bonzini
Cc: Maydell Peter
Cc: John Snow
Cc: Thomas Huth
Signed-off-by: Ani Sinha
---
Added the SPDX license identifier for smilatency tests.
Also added a comment indicating that smilatency test is run from within the
biosbits environment/VM and hence is not subjected to QEMU build/test
environment dependency fulfilments or QEMU maintanance activities.
Cc: Daniel P. Berrangé
Cc:
PSS tests in acpi test suite seems to be failing in biosbits. This is because
the test is unable to find PSS support in QEMU bios. Let us disable
them for now so that make check does not fail. We can fix the tests and
re-enable them later.
Example failure:
ACPI _PSS (Pstate) table
Added the SPDX license identifiers for biosbits tests.
Also added a comment on each of the test scripts to indicate that they run
from within the biosbits environment and hence are not subjected to the regular
maintanance acivities for QEMU and is excluded from the dependency management
challenges
This change adds initial biosbits config file that instructs biosbits to run
bios test suits in batch mode. Additionally acpi and smbios structures are also
dumped.
Cc: Daniel P. Berrangé
Cc: Paolo Bonzini
Cc: Maydell Peter
Cc: John Snow
Cc: Thomas Huth
Signed-off-by: Ani Sinha
---
Please see the README file added in patch 10 for more details.
Sample runs are as follows:
$ ./tests/venv/bin/avocado run -t acpi tests/avocado --tap -
ERROR: Missing parentheses in call to 'print'. Did you mean print(...)?
(smbios.py, line 92)
ERROR: Missing parentheses in call to 'print'.
On Wed, Sep 28, 2022 at 3:19 PM Yang Liu wrote:
>
> Tested with https://github.com/ksco/rvv-decoder-tests
>
> Expected checkpatch errors for consistency and brevity reasons:
>
> ERROR: line over 90 characters
> ERROR: trailing statements should be on next line
> ERROR: braces {} are necessary for
On 10/10/22 07:21, Thomas Huth wrote:
On 10/10/2022 08.56, Dennis Clarke wrote:
re:
https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg01249.html
Using GCC 12 is even worse :
[2040/6841] Compiling C object qemu-system-aarch64.p/softmmu_main.c.o
[2041/6841] Linking target
On 10/10/2022 08.56, Dennis Clarke wrote:
re: https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg01249.html
Using GCC 12 is even worse :
[2040/6841] Compiling C object qemu-system-aarch64.p/softmmu_main.c.o
[2041/6841] Linking target qemu-system-aarch64
FAILED: qemu-system-aarch64
On 10/10/2022 08.18, Dennis Clarke wrote:
On FreeBSD 14.0 CURRENT amd64 everything seems to go swimmingly until :
[5679/6848] Compiling C object libqemu-arm-bsd-user.fa.p/bsd-user_mmap.c.o
[5680/6848] Compiling C object libqemu-arm-bsd-user.fa.p/bsd-user_signal.c.o
FAILED:
Hannes Reinecke 于2022年10月10日周一 14:19写道：
>
> On 10/10/22 04:21, Sam Li wrote:
> > Add the documentation about the zoned device support to virtio-blk
> > emulation.
> >
> > Signed-off-by: Sam Li
> > Reviewed-by: Stefan Hajnoczi
> > ---
> > docs/devel/zoned-storage.rst | 40
re: https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg01249.html
Using GCC 12 is even worse :
[2040/6841] Compiling C object qemu-system-aarch64.p/softmmu_main.c.o
[2041/6841] Linking target qemu-system-aarch64
FAILED: qemu-system-aarch64
/usr/local/bin/g++12 -m64 -mcx16
On 10/7/22 16:44, Francisco Iglesias wrote:
On [2022 Jul 22] Fri 08:35:58, Cédric Le Goater wrote:
The mx25l25635e and mx25l25635f chips have the same JEDEC id but the
mx25l25635f has more capabilities reported in the SFDP table. Support
for 4B opcodes is of interest because it is exploited by
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