From: Mostafa Saleh
Allow TLB to be tagged with VMID.
If stage-1 is only supported, VMID is set to -1 and ignored from STE
and CMD_TLBI_NH* cmds.
Update smmu_iotlb_insert trace event to have vmid.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
Tested-by: Eric Auger
Tested-by:
No nead to store return value and break from loop when we can return
directly.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index a84bc7de88..ff7f987546
From: Marcin Juszkiewicz
Let add GIC information into DeviceTree as part of SBSA-REF versioning.
Trusted Firmware will read it and provide to next firmware level.
Bumps platform version to 0.1 one so we can check is node is present.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Peter
The CTRL register is able to write bit zero, and that is reflected in a
bit field in the register that reflects the state of all threads in the
core.
TCG does not implement SMT, so this just requires mirroring that bit into
the first bit of the thread state field.
Signed-off-by: Nicholas Piggin
From: Mostafa Saleh
Right now, either stage-1 or stage-2 are supported, this simplifies
how we can deal with TLBs.
This patch makes TLB lookup work if stage-2 is enabled instead of
stage-1.
TLB lookup is done before a PTW, if a valid entry is found we won't
do the PTW.
To be able to do TLB
This function is the only reason why ppcemb_tlb_check() is not static
to mmu_common.c but it also better fits in mmu_common.c so move it
there.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h| 4 +---
target/ppc/mmu_common.c | 22 +-
target/ppc/mmu_helper.c | 21
From: Enze Li
I noticed that in the latest version, the copyright string is still
2022, even though 2023 is halfway through. This patch fixes that and
fixes the documentation along with it.
Signed-off-by: Enze Li
Reviewed-by: Peter Maydell
Message-id:
This is only used by one caller so simplify function by removing this
parameter and move the operation to the single place where it's used.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h| 3 +--
target/ppc/mmu_common.c | 21 +
target/ppc/mmu_helper.c | 2 +-
3
Hi Steve,
On 7/2/23 19:44, Steven Sistare wrote:
To make forward progress on this series and reduce its size, I will be posting
those of its patches that can be independently integrated and have some value
on their own, to a reduced distribution of reviewers for each. This is what
I plan to
From: Ira Weiny
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
commands. Enable those commands to control interrupts for each of the
event log types.
Skip the standard input mailbox length on the Set command due to DCD
being optional. Perform the checks separately.
On 5/30/23 03:20, Thomas Huth wrote:
The PowerMacs have an OHCI controller soldered on the motherboard,
so this should always be enabled for the "mac99" machine.
This fixes the problem that QEMU aborts when the user tries to run
the "mac99" machine with a build that has been compiled with the
From: Ira Weiny
To facilitate testing provide a QMP command to inject a general media
event. The event can be added to the log specified.
Signed-off-by: Ira Weiny
Reviewed-by: Fan Ni
Acked-by: Markus Armbruster
Signed-off-by: Jonathan Cameron
---
v9: Double space after . for consistency.
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
Analysis of the MacOS toolbox ROM code shows that on startup it attempts 2
separate reads of the seconds registers with commands 0x9d...0x91 followed by
0x8d..0x81 without resetting the command to its initial value. The PRAM seconds
value is only
From: Ira Weiny
CXL testing is benefited from an artificial event log injection
mechanism.
Add an event log infrastructure to insert, get, and clear events from
the various logs available on a device.
Replace the stubbed out CXL Get/Clear Event mailbox commands with
commands that operate on
Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
provides information related to DRAM devices.
Example injection command in QMP:
{ "execute": "cxl-inject-dram-event",
"arguments": {
"path": "/machine/peripheral/cxl-mem0",
"log": "informational",
"flags":
On 5/30/2023 9:38 AM, Philippe Mathieu-Daudé wrote:
> Hi Steve,
>
> On 7/2/23 19:44, Steven Sistare wrote:
>> To make forward progress on this series and reduce its size, I will be
>> posting
>> those of its patches that can be independently integrated and have some value
>> on their own, to a
On 5/30/23 06:44, Peter Maydell wrote:
On Fri, 26 May 2023 at 01:24, Richard Henderson
wrote:
PAGE_WRITE is current writability, as modified by TB protection;
PAGE_WRITE_ORG is the original page writability.
Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads")
Signed-off-by: Richard
On Fri, 26 May 2023 at 01:24, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> .../generic/host/load-extract-al16-al8.h | 45 +++
> accel/tcg/ldst_atomicity.c.inc| 36 +--
> 2 files changed, 47 insertions(+), 34 deletions(-)
On Fri, 26 May 2023 at 01:24, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
Add a new VFIO device property x-allow-pre-copy to keep migration
compatibility to/from older QEMU versions that don't have VFIO pre-copy
support.
Signed-off-by: Avihai Horon
Reviewed-by: Cédric Le Goater
---
include/hw/vfio/vfio-common.h | 1 +
hw/core/machine.c | 1 +
Refactor vfio_save_block() to return the size of saved data on success
and -errno on error.
This will be used in next patch to implement VFIO migration pre-copy
support.
Signed-off-by: Avihai Horon
Reviewed-by: Cédric Le Goater
Reviewed-by: Juan Quintela
---
hw/vfio/migration.c | 17
On Tue, 30 May 2023 at 15:29, Richard Henderson
wrote:
>
> On 5/30/23 07:06, Peter Maydell wrote:
> >> This is about falling through to the cmpxchg below: if !PAGE_WRITE_ORG,
> >> then the page is
> >> really not writable, we will SIGSEGV, and handle_sigsegv_accerr_write will
> >> kill the
Add migration switchover ack capability test. The test runs without
devices that support this capability, but is still useful to make sure
it didn't break anything.
Signed-off-by: Avihai Horon
Reviewed-by: Juan Quintela
Reviewed-by: Peter Xu
---
tests/qtest/migration-test.c | 26
Now that switchover ack logic has been implemented, enable the
capability.
Signed-off-by: Avihai Horon
Reviewed-by: Juan Quintela
Reviewed-by: Peter Xu
---
migration/options.c | 4
1 file changed, 4 deletions(-)
diff --git a/migration/options.c b/migration/options.c
index
On 5/30/23 04:02, Akihiko Odaki wrote:
On 2023/05/30 0:07, Cédric Le Goater wrote:
On 5/29/23 09:45, Akihiko Odaki wrote:
On 2023/05/29 16:01, Cédric Le Goater wrote:
On 5/29/23 04:45, Akihiko Odaki wrote:
On 2023/05/28 19:50, Sriram Yagnaraman wrote:
-Original Message-
From:
Queued, thanks.
Paolo
Ping.
On 5/25/23 10:00, Richard Henderson wrote:
Hi guys,
https://gitlab.com/qemu-project/qemu/-/jobs/4352476431
https://gitlab.com/qemu-project/qemu/-/jobs/4352476434
This test ERRORs on the azure k8s runners with
qemu-system-x86_64: egl: no drm render node available
qemu-system-x86_64:
Hello,
On 5/8/23 09:58, Cédric Le Goater wrote:
Hello,
This series fixes issues spotted by Coverity and adds a couple of
improvements for the machine definition.
The first is to offer the capability to define all CS of all SPI
controllers without introducing new machine types, using a
On Fri, 26 May 2023 at 00:27, Richard Henderson
wrote:
>
> Let finalize_memop_atom be the new basic function, with
> finalize_memop and finalize_memop_pair testing FEAT_LSE2
> to apply the appropriate atomicity.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 2023-05-26 at 17:22 +0200, Mickaël Salaün wrote:
> > > Can the guest kernel ask the host VMM's emulated devices to DMA
> > > into
> > > the protected data? It should go through the host userspace
> > > mappings I
> > > think, which don't care about EPT permissions. Or did I miss
> > >
From: Christoph Müllner
In order to enable vendor disassembler support, we need to
move types and constants into a header file so that other
compilation units can use them as well.
This patch does not introduce any functional changes.
Signed-off-by: Christoph Müllner
---
disas/riscv.c | 270
From: Christoph Müllner
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei
Signed-off-by: Christoph Müllner
---
disas/meson.build | 5 -
disas/riscv-xventana.c | 41 +
disas/riscv-xventana.h | 18
From: Christoph Müllner
This patch adds a reference to a struct rv_opcode_data object
into struct rv_decode. This further allows to remove all references
to the global variable opcode_data (which is renamed to rvi_opcode_data).
This patch does not introduce any functional change, but prepares
From: Christoph Müllner
This series adds vendor extension support to the QEMU disassembler
for RISC-V. The following vendor extensions are covered:
* XThead{Ba,Bb,Bs,Cmo,CondMov,FMemIdx,Fmv,Mac,MemIdx,MemPair,Sync}
* XVentanaCondOps
So far, there have been two attempts to add vendor extension
On Tue, May 30, 2023 at 2:57 PM Daniel P. Berrangé wrote:
> > > I'm not sure what's the best way to proceed for roms/SLOF. Some
> > > possibilities, in no particular order, include:
> > >
> > > * doing nothing
> > >
> > > * merging --with-git-submodules with --enable-download, and
> > >
/juan.quintela/qemu.git
tags/migration-20230530-pull-request
for you to fetch changes up to d83da4626ebc1462e8f0065d446f97aece681d90:
migration/rdma: Check sooner if we are in postcopy for save_page()
(2023-05-30 13:27:54 +0200
From: Mostafa Saleh
As everything is in place, we can use a new system property to
advertise which stage is supported and remove bad_ste from STE
stage2 config.
The property added arm-smmuv3.stage can have 3 values:
- "1": Stage-1 only is advertised.
- "2": Stage-2 only is advertised.
If not
...
> > +#
> > +# @corrected-persistent-error-count: Total number correctable errors
>
> Total number of correctable errors
Gah. I've now seen these too often so read that a good 5 times before
working out what was wrong!
>
> > +# in persistent memory
> > +#
> > +# Since: 8.1
> > +##
(Sorry Juan - I do have a question)
We do have a question, about using Instruction abort in HVF/KVM - we’re like to
explain, and ask if a patch would be acceptable.
Cheers
Mark.
> On 28 May 2023, at 19:50, juan.quint...@gmail.com wrote:
>
> WARNING: This email originated from outside of
Juan Quintela writes:
> If we pass a NULL error is the same that returning dirrectly the value.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Fabiano Rosas
On 30.05.23 15:11, David Hildenbrand wrote:
On 30.05.23 15:07, Michael S. Tsirkin wrote:
On Tue, May 30, 2023 at 01:38:36PM +0200, David Hildenbrand wrote:
There are no remaining users in the tree, so let's remove it.
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: "Michael
On Fri, 26 May 2023 at 01:26, Richard Henderson
wrote:
>
> Older versions of clang have missing runtime functions for arithmetic
> with -fsanitize=undefined (see 464e3671f9d5c), so we cannot use
> __int128_t for implementing Int128. But __int128_t is present,
> data movement works, and can be
ARM intrinsics for AES deviate from the x86 ones in the way they cover
the different stages of each round, and so mapping one to the other is
not entirely straight-forward. However, with a bit of care, we can still
use the x86 ones to emulate the ARM ones, which makes them constant time
(which is
On Fri, 26 May 2023 at 01:26, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c.inc | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 30 May 2023 at 14:58, Richard Henderson
wrote:
>
> On 5/30/23 06:44, Peter Maydell wrote:
> > On Fri, 26 May 2023 at 01:24, Richard Henderson
> > wrote:
> >>
> >> PAGE_WRITE is current writability, as modified by TB protection;
> >> PAGE_WRITE_ORG is the original page writability.
> >>
>
Juan Quintela writes:
> This was the only caller for read only files. So change the test for
> an assert in qemu_fflush().
>
> Signed-off-by: Juan Quintela
Reviewed-by: Fabiano Rosas
' of https://gitlab.com/danielhb/qemu into
staging (2023-05-29 14:31:52 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230530
for you to fetch changes up to b03d0d4f531a8b867e0aac1fab0b876903015680:
docs: sbsa: correct
Pre-copy support allows the VFIO device data to be transferred while the
VM is running. This helps to accommodate VFIO devices that have a large
amount of data that needs to be transferred, and it can reduce migration
downtime.
Pre-copy support is optional in VFIO migration protocol v2.
Implement
Loading of a VFIO device's data can take a substantial amount of time as
the device may need to allocate resources, prepare internal data
structures, etc. This can increase migration downtime, especially for
VFIO devices with a lot of resources.
To solve this, VFIO migration uAPI defines "initial
Hello everyone,
This is v5 of the switchover ack series.
Changes from v4 [6]:
* Removed superfluous '"' in vfio_save_iterate() trace. (Cedric)
* Removed VFIOMigration->switchover_ack_needed and computed it locally
when needed. (Cedric)
* Added R-bs.
Changes from v3 [5]:
* Rebased on latest
Implement switchover ack logic. This prevents the source from stopping
the VM and completing the migration until an ACK is received from the
destination that it's OK to do so.
To achieve this, a new SaveVMHandlers handler switchover_ack_needed()
and a new return path message
On 5/30/23 06:52, Ard Biesheuvel wrote:
ARM intrinsics for AES deviate from the x86 ones in the way they cover
the different stages of each round, and so mapping one to the other is
not entirely straight-forward. However, with a bit of care, we can still
use the x86 ones to emulate the ARM ones,
Migration downtime estimation is calculated based on bandwidth and
remaining migration data. This assumes that loading of migration data in
the destination takes a negligible amount of time and that downtime
depends only on network speed.
While this may be true for RAM, it's not necessarily true
VFIO migration flags are queried once in vfio_migration_init(). Store
them in VFIOMigration so they can be used later to check the device's
migration capabilities without re-querying them.
This will be used in the next patch to check if the device supports
precopy migration.
Signed-off-by:
On 5/30/23 14:30, Akihiko Odaki wrote:
On 2023/05/30 17:30, Sriram Yagnaraman wrote:
-Original Message-
From: Akihiko Odaki
Sent: Tuesday, 30 May 2023 04:02
To: Cédric Le Goater ; Sriram Yagnaraman
; qemu-devel@nongnu.org
Cc: Jason Wang
Subject: Re: [PATCH] igb: Add Function Level
On Fri, 26 May 2023 at 15:44, Richard Henderson
wrote:
>
> On 5/26/23 02:49, Juan Quintela wrote:
> > Philippe Mathieu-Daudé wrote:
> >> Hi,
> >>
> >> On 26/5/23 01:25, Richard Henderson wrote:
> >>> Document the meaning of exclusive_high in a big-endian context,
> >>> and why we can't change it
On Tue, 30 May 2023 at 15:46, Peter Maydell wrote:
>
> On Tue, 30 May 2023 at 15:26, Yeqi Fu wrote:
> >
> > This patch introduces a set of feature instructions for native calls
> > and provides helpers to translate these instructions to corresponding
> > native functions. A shared library is
Update prebuilt firmware images to have TF-A with FEAT_FGT support
enabled. This allowed us to enable test for "max" cpu in sbsa-ref
machine.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 22 +++---
1 file changed, 11 insertions(+), 11
ppc hypervisors turn HEAI interrupts into program interrupts injected
into the guest that executed the illegal instruction, if the hypervisor
doesn't handle it some other way.
The nested-hv implementation failed to account for this HEAI->program
conversion. The virtual hypervisor wants to see the
On 5/27/23 01:15, Alex Williamson wrote:
This is a partial linux-headers update for illustrative and testing
purposes only, NOT FOR COMMIT.
Are you planing such an update for v6.5 ?
Thanks,
C.
Signed-off-by: Alex Williamson
---
linux-headers/linux/vfio.h | 14 ++
1 file
From: Marcin Juszkiewicz
We moved from VGA to Bochs to have PCIe card.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/system/arm/sbsa.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/arm/sbsa.rst
Rather than always performing partition scope page table translation
with access type of 0 (MMU_DATA_LOAD), pass through the processor
access type which first initiated the translation sequence. Process-
scoped page table loads are then set to MMU_DATA_LOAD access type in
the xlate function.
This
From: Vitaly Cheptsov
SNVS is supported on both i.MX6 and i.MX6UL and is needed
to support shutdown on the board.
Cc: Peter Maydell (odd fixer:SABRELITE / i.MX6)
Cc: Jean-Christophe Dubois (reviewer:SABRELITE / i.MX6)
Cc: qemu-...@nongnu.org (open list:SABRELITE / i.MX6)
Cc:
The hypervisor emulation assistance interrupt modifies HEIR to
contain the value of the instruction which caused the exception.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c| 23 +++
target/ppc/excp_helper.c | 13 -
From: Mostafa Saleh
In preparation for adding stage-2 support, add a S2 config
struct(SMMUS2Cfg), composed of the following fields and embedded in
the main SMMUTransCfg:
-tsz: Size of IPA input region (S2T0SZ)
-sl0: Start level of translation (S2SL0)
-affd: AF Fault Disable (S2AFFD)
into
staging (2023-05-29 14:31:52 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230530
for you to fetch changes up to b03d0d4f531a8b867e0aac1fab0b876903015680:
docs: sbsa: correct graphics card name (2023-05-30 13:32:46 +0100
From: Fabiano Rosas
Replace the 'default y if TCG' pattern with 'default y; depends on
TCG'.
That makes explict that there is a dependence on TCG and enabling
these CONFIGs via .mak files without TCG present will fail earlier.
Suggested-by: Paolo Bonzini
Signed-off-by: Fabiano Rosas
From: Mostafa Saleh
In preparation for adding stage-2 support, rename smmu_ptw_64 to
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
stage-2 page table walk.
Remove AA64 check from PTW as decode_cd already ensures that AA64 is
used, otherwise it faults with C_BAD_CD.
A
For M-profile, there is no guest-facing A-profile format FSR, but we
still use the env->exception.fsr field to pass fault information from
the point where a fault is raised to the code in
arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile
specific fault status registers. So it
Hello,
This series improves embedded PPC TLB emulation a bit and contains
some misc clean up I've found along the way. Before this patch
ppcemb_tlb_check() shows up in a memory access intensive profile
(running RageMem speed test in AmigaOS on sam460ex) at 11.91%
children, 10.77% self. After this
From: Fabiano Rosas
We currently need to select ARM_V7M unconditionally when TCG is
present in the build because some translate.c helpers and the whole of
m_helpers.c are not yet under CONFIG_ARM_V7M.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
Reviewed-by: Philippe
From: Mostafa Saleh
In smmuv3_notify_iova, read the granule based on translation stage
and use VMID if valid value is sent.
Signed-off-by: Mostafa Saleh
Reviewed-by: Eric Auger
Tested-by: Eric Auger
Tested-by: Jean-Philippe Brucker
Message-id: 20230516203327.2051088-10-smost...@google.com
From: Mostafa Saleh
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
same as CMD_TLBI_NH_VAA.
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
For stage-1 only commands, add a check to throw CERROR_ILL if used
when stage-1 is not supported.
Reviewed-by: Eric
These events include a copy of the device health information at the
time of the event. Actually using the emulated device health would
require a lot of controls to manipulate that state. Given the aim
of this injection code is to just test the flows when events occur,
inject the contents of the
On Fri, 26 May 2023 at 01:24, Richard Henderson
wrote:
>
> PAGE_WRITE is current writability, as modified by TB protection;
> PAGE_WRITE_ORG is the original page writability.
>
> Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads")
> Signed-off-by: Richard Henderson
> ---
>
On 30/5/23 15:00, Kambalin, Sergey wrote:
Got it! Thanks!
I'll split this one to three patches:
1) replace magic numbers with named constants (refactoring)
2) add new properties for VC 4
3) Add some unit tests to check the newly added properties via mailbox
Is it OK?
This looks good. Try
On Fri, 26 May 2023 at 01:25, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> .../x86_64/host/load-extract-al16-al8.h | 50 +++
> 1 file changed, 50 insertions(+)
> create mode 100644 host/include/x86_64/host/load-extract-al16-al8.h
Reviewed-by:
On 5/30/23 07:06, Peter Maydell wrote:
This is about falling through to the cmpxchg below: if !PAGE_WRITE_ORG, then
the page is
really not writable, we will SIGSEGV, and handle_sigsegv_accerr_write will kill
the process.
Right, but if !PAGE_WRITE_ORG then that implies also !PAGE_WRITE,
so we
t; are available in the Git repository at:
>>https://gitlab.com/juan.quintela/qemu.git
>> tags/migration-20230530-pull-request
>> for you to fetch changes up to
>> d83da4626ebc1462e8f0065d446f97aece681d90:
>>migration/rdma: Check sooner if we are
/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230530-1
for you to fetch changes up to ec683110def96b16be3931ec87baba65a3dc5ad0:
docs: sbsa: correct graphics card name (2023-05-30 15:50:17 +0100)
target-arm queue:
* fsl
On 5/30/23 07:48, Peter Maydell wrote:
On Tue, 30 May 2023 at 15:29, Richard Henderson
wrote:
On 5/30/23 07:06, Peter Maydell wrote:
This is about falling through to the cmpxchg below: if !PAGE_WRITE_ORG, then
the page is
really not writable, we will SIGSEGV, and handle_sigsegv_accerr_write
On Tue, 30 May 2023 at 16:09, Richard Henderson
wrote:
>
> On 5/30/23 07:48, Peter Maydell wrote:
> > On Tue, 30 May 2023 at 15:29, Richard Henderson
> > wrote:
> >>
> >> On 5/30/23 07:06, Peter Maydell wrote:
> This is about falling through to the cmpxchg below: if !PAGE_WRITE_ORG,
>
On Fri, 26 May 2023 at 00:27, Richard Henderson
wrote:
>
> While we don't require 16-byte atomicity here, using a single larger
> operation simplifies the code. Introduce finalize_memop_asimd for this.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate.h | 24
Am 16.05.2023 um 21:02 hat Stefan Hajnoczi geschrieben:
> The aio_disable_external() API temporarily suspends file descriptor monitoring
> in the event loop. The block layer uses this to prevent new I/O requests being
> submitted from the guest and elsewhere between bdrv_drained_begin() and
>
On 15.05.23 22:53, Eric Blake wrote:
Add the constants and structs necessary for later patches to start
implementing the NBD_OPT_EXTENDED_HEADERS extension in both the client
and server, matching recent commit e6f3b94a934] in the upstream nbd
project. This patch does not change any existing
The get_physical_address() function is a trivial wrapper of
get_physical_address_wtlb() that is only used once. Remove it and call
get_physical_address_wtlb() directly instead.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_helper.c | 11 +--
1 file changed, 1 insertion(+), 10
From: Mostafa Saleh
In preparation for adding stage-2 support, add Stage-2 PTW code.
Only Aarch64 format is supported as stage-1.
Nesting stage-1 and stage-2 is not supported right now.
HTTU is not supported, SW is expected to maintain the Access flag.
This is described in the SMMUv3
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index ff7f987546..bd7d7d5257 100644
--- a/target/ppc/mmu_common.c
+++
From: Fabiano Rosas
When we moved the arm default CONFIGs into Kconfig and removed them
from default.mak, we made it harder to identify which CONFIGs are
selected by default in case users want to disable them.
Bring back the default entries into default.mak, but keep them
commented out. This
From: Mostafa Saleh
In preparation for adding stage-2 support.
Add IDR0 fields related to stage-2.
VMID16: 16-bit VMID supported.
S2P: Stage-2 translation supported.
They are described in 6.3.1 SMMU_IDR0.
No functional change intended.
Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
From: Tommy Wu
When we receive a packet from the xilinx_axienet and then try to s2mem
through the xilinx_axidma, if the descriptor ring buffer is full in the
xilinx axidma driver, we’ll assert the DMASR.HALTED in the
function : stream_process_s2mem and return 0. In the end, we’ll be stuck in
an
Move out checking PID registers into a separate function which makes
mmubooke_check_tlb() simpler and avoids using goto.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 40 +---
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/ppc/excp_helper.c
From: Clément Chigot
When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS,
the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result
in a positive number as ms->smp.cpus is a unsigned int.
This will raise the following error afterwards, as Qemu will try to
instantiate
The PMU raises a performance monitor exception (causing an interrupt
when MSR[EE]=1) when MMCR0[PMAO] is set, and lowers it when clear.
Wire this up and implement the interrupt delivery for books. Linux perf
record can now collect PMI-driven samples.
fire_PMC_interrupt is renamed to perfm_alert,
On 30/5/23 15:11, David Hildenbrand wrote:
On 30.05.23 15:07, Michael S. Tsirkin wrote:
On Tue, May 30, 2023 at 01:38:36PM +0200, David Hildenbrand wrote:
There are no remaining users in the tree, so let's remove it.
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: "Michael
FCECE does not get cleared according to the ISA v3.1B.
Signed-off-by: Nicholas Piggin
---
target/ppc/power8-pmu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index c4c331c6b5..af065115f2 100644
--- a/target/ppc/power8-pmu.c
+++
On Fri, 26 May 2023 at 01:25, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
Hi Ard,
On 30/5/23 15:52, Ard Biesheuvel wrote:
ARM intrinsics for AES deviate from the x86 ones in the way they cover
the different stages of each round, and so mapping one to the other is
not entirely straight-forward. However, with a bit of care, we can still
use the x86 ones to emulate the
This patch introduces a set of feature instructions for native calls
and provides helpers to translate these instructions to corresponding
native functions. A shared library is also implemented, where native
functions are rewritten as feature instructions. At runtime, user
programs load the shared
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