On Tue, May 30, 2023 at 05:02:59PM +0800, Wei Wang wrote:
> The Postcopy preempt capability requires to be set before incoming
> starts, so change the postcopy tests to start with deferred incoming and
> call migrate-incoming after the cap has been set.
>
> Signed-off-by: Wei Wang
Hmm.. so we
On Tue, May 30, 2023 at 03:41:58PM +0200, David Hildenbrand wrote:
> On 30.05.23 15:11, David Hildenbrand wrote:
> > On 30.05.23 15:07, Michael S. Tsirkin wrote:
> > > On Tue, May 30, 2023 at 01:38:36PM +0200, David Hildenbrand wrote:
> > > > There are no remaining users in the tree, so let's
On Tue, 30 May 2023 at 15:26, Yeqi Fu wrote:
>
> This patch introduces a set of feature instructions for native calls
> and provides helpers to translate these instructions to corresponding
> native functions. A shared library is also implemented, where native
> functions are rewritten as feature
On Fri, 26 May 2023 at 01:24, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/i386/tcg-target.h | 4 +-
> tcg/i386/tcg-target.c.inc | 191 +-
> 2 files changed, 190 insertions(+), 5 deletions(-)
Reviewed-by: Peter Maydell
On Mon, 29 May 2023 15:59:56 +0800
Li Zhijian wrote:
> Only 'fw' pointer is marked as g_autofree, so we shoud free other
> resource manually in error path.
>
Good spot.
Patch title typo
hw/cxl:
It's a bit annoying we can't handle this with more autofree magic.
That would work for fw->targets
On 5/30/23 16:48, Avihai Horon wrote:
Loading of a VFIO device's data can take a substantial amount of time as
the device may need to allocate resources, prepare internal data
structures, etc. This can increase migration downtime, especially for
VFIO devices with a lot of resources.
To solve
On Fri, 26 May 2023 at 00:27, Richard Henderson
wrote:
>
> While we don't require 16-byte atomicity here, using a single larger
> load simplifies the code, and makes it a closer match to STXP.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
From: Christoph Müllner
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei
Signed-off-by: Christoph Müllner
---
disas/meson.build | 1 +
disas/riscv-xthead.c
From: Christoph Müllner
The file target/riscv/cpu.h cannot be included by files outside
of target/riscv/. To share data with other parts of QEMU (e.g.
the disassembler) we need to factor out the relevant code.
Therefore, this patch moves the definition of RISCVCPUConfig
(and tightly coupled
Reposting these since two were merged, and I moved the PMU fix out
of the series since that's a crash fix. Should be no real change
other than rebase and kvm-only build fix.
Thanks,
Nick
Nicholas Piggin (6):
target/ppc: Fix instruction loading endianness in alignment interrupt
target/ppc:
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 22 +-
1
From: Mostafa Saleh
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
Validity of field values are checked when possible.
Only AA64 tables are supported and Small Translation Tables (STT) are
not supported.
According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
From: Thomas Huth
pflash-cfi02-test.c always uses the "musicpal" machine for testing,
test-arm-mptimer.c always uses the "vexpress-a9" machine, and
microbit-test.c requires the "microbit" machine, so we should only
run these tests if the machines have been enabled in the configuration.
ISA v3.1 introduced prefix instructions. Among the changes, various
synchronous interrupts report whether they were caused by a prefix
instruction in (H)SRR1.
The case of instruction fetch that causes an HDSI due to access of a
process-scoped table faulting on the partition scoped translation is
v9: A few remaining QMP documentation formatting fixes from Markus.
Fingers crossed it's now clean!
Based on:
[PATCH v8 0/4] hw/cxl: Poison get, inject, clear
Based on: Message-ID: 20230526170010.574-1-jonathan.came...@huawei.com
Updated cover letter from earlier versions:
One challenge here
On 5/27/23 01:15, Alex Williamson wrote:
Dynamically enable Atomic Ops completer support around realize/exit of
vfio-pci devices reporting host support for these accesses and adhering
to a minimal configuration standard. While the Atomic Ops completer
bits in the root port device capabilities2
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
A comparison between the rtc command table included in the comment and the code
itself shows that the decoding for PRAM addresses 0x0 to 0xf is being done on
the raw command, and not the shifted version held in value.
Signed-off-by: Mark
From: Ira Weiny
The device status register block was defined. However, there were no
individual registers nor any data wired up.
Define the event status register [CXL 3.0; 8.2.8.3.1] as part of the
device status register block. Wire up the register and initialize the
event status for each
On Fri, 26 May 2023 at 01:25, Richard Henderson
wrote:
>
> The first move was incorrectly using TCG_TYPE_I32 while the second
> move was correctly using TCG_TYPE_REG. This prevents a 64-bit host
> from moving all 128-bits of the return value.
>
> Fixes: ebebea53ef8 ("tcg: Support TCG_TYPE_I128
Following patches will need access to the mailbox return code
type so move it to the header.
Reviewed-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 28
hw/cxl/cxl-mailbox-utils.c | 28
This fixes compiler messages like "warning: format specifies type
'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned
long') [-Wformat]".
Signed-off-by: Matheus Tavares Bernardino
---
tests/tcg/hexagon/hex_test.h | 14 ++
1 file changed, 10 insertions(+), 4
Juan Quintela writes:
> We only care about the amount of bytes transferred. Flushing is done
> by the system somewhere else.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Fabiano Rosas
This series includes two fixes on hexagon test files: one for a
non-porable printf specifier, and the other for the use of an
uninitialized register.
Marco Liebel (1):
Hexagon (hvx_misc test): fix uninitialized regs at test_load_tmp2
Matheus Tavares Bernardino (1):
Hexagon
From: Marco Liebel
This test case was using some vector registers which were not properly
initialized.
Signed-off-by: Marco Liebel
Signed-off-by: Matheus Tavares Bernardino
---
tests/tcg/hexagon/hvx_misc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
On Fri, 26 May 2023 at 01:26, Richard Henderson
wrote:
>
> Adjust the softmmu tlb to use TMP[0-2], not any of the normally available
> registers. Since we handle overlap betwen inputs and helper arguments,
> we can allow any allocatable reg.
>
> Signed-off-by: Richard Henderson
Reviewed-by:
On Fri, 26 May 2023 at 01:25, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> .../aarch64/host/load-extract-al16-al8.h | 40 +++
> 1 file changed, 40 insertions(+)
> create mode 100644 host/include/aarch64/host/load-extract-al16-al8.h
Reviewed-by:
On Tue, May 30, 2023 at 05:02:58PM +0800, Wei Wang wrote:
> qemu_start_incoming_migration needs to check the number of multifd
> channels or postcopy ram channels to configure the backlog parameter (i.e.
> the maximum length to which the queue of pending connections for sockfd
> may grow) of
On Fri, 26 May 2023 at 00:27, Richard Henderson
wrote:
>
> We have many other instances of stg in the testsuite;
> change these to provide an instance of stz2g.
>
> Signed-off-by: Richard Henderson
> ---
> tests/tcg/aarch64/mte-7.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Hi, Andrei,
On Thu, Apr 27, 2023 at 03:42:56PM +0300, Andrei Gudkov via wrote:
> Afterwards we tried to migrate VM after randomly selecting max downtime
> and bandwidth limit. Typical prediction error is 6-7%, with only 180 out
> of 5779 experiments failing badly: prediction error >=25% or
A set of small fixes for the interrupt controller (xive2) on P10.
Frederic Barrat (4):
pnv/xive2: Add definition for TCTXT Config register
pnv/xive2: Add definition for the ESB cache configuration register
pnv/xive2: Allow writes to the Physical Thread Enable registers
pnv/xive2: Handle
Add basic read/write support for the ESB cache configuration register
on P10. We don't model the ESB cache in qemu so reading/writing the
register won't do anything, but it avoids logging a guest error when
skiboot configures it:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
Add basic read/write support for the TCTXT Config register on P10. qemu
doesn't do anything with it yet, but it avoids logging a guest error
when skiboot configures the fused-core state:
qemu-system-ppc64 -machine powernv10 ... -d guest_errors
...
[0.13167,5] XIVE: [ IC 00 ]
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports/snoop buses, targeted by the address. The base address of a TIMA
is using port 0 and the other ports are 0x80 apart. Using one port or
another can be useful to balance the load on the snoop buses.
The TIMA registers are
Fix what was probably a silly mistake and allow to write the Physical
Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
variant so it went unnoticed, but there's no reason to discard a write
to the full register, it is Read-Write.
Signed-off-by: Frederic Barrat
---
Move most includes from *translate*.c to translate.h, ensuring
that we get the ordering correct. Ensure cpu.h is first.
Use disas/disas.h instead of exec/log.h.
Drop otherwise unused includes.
Signed-off-by: Richard Henderson
---
target/mips/tcg/translate.h| 6 --
Create two static libraries for use by each execution mode.
Signed-off-by: Richard Henderson
---
tcg/meson.build | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/tcg/meson.build b/tcg/meson.build
index bdc185a485..565c60bc96 100644
---
All uses replaced with TCGContext.addr_type.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index d2d0f604c2..48efd83817 100644
---
This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h,
via exec/exec-all.h, but the include of tcg.h will be removed.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index
On 31/5/23 06:03, Richard Henderson wrote:
This finally paves the way for tcg/ to be built once per mode.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 -
accel/tcg/plugin-gen.c | 1 +
tcg/region.c | 2 +-
tcg/tcg-op.c | 2 +-
tcg/tcg.c
On Mon, May 29, 2023 at 9:18 PM Hawkins Jiawei wrote:
>
> This patch introduces vhost_vdpa_net_load_offloads() to
> restore offloads state at device's startup.
>
> Signed-off-by: Hawkins Jiawei
> ---
> net/vhost-vdpa.c | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff
On Mon, May 29, 2023 at 9:18 PM Hawkins Jiawei wrote:
>
> Enable SVQ with VIRTIO_NET_F_CTRL_GUEST_OFFLOADS feature.
>
> Signed-off-by: Hawkins Jiawei
Acked-by: Jason Wang
Thanks
> ---
> net/vhost-vdpa.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/net/vhost-vdpa.c
On 5/30/2023 6:08 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 5/30/2023 1:01 PM, Wu, Fei wrote:
>>> On 5/30/2023 12:07 PM, Richard Henderson wrote:
On 5/29/23 04:49, Fei Wu wrote:
> +/*
> + * The TCGProfile structure holds data for analysing the quality of
> + * the
On 2023/5/30 22:24, Yeqi Fu wrote:
This patch introduces a set of feature instructions for native calls
and provides helpers to translate these instructions to corresponding
native functions. A shared library is also implemented, where native
functions are rewritten as feature instructions. At
On Wed, May 31, 2023 at 11:17 AM Jon Kohler wrote:
>
> If kernel supports IFF_NAPI, lets use it, which is especially useful
> on kernels containing fb3f903769e8 ("tun: support NAPI for packets
> received from batched XDP buffs"), as IFF_NAPI allows the
> vhost_tx_batch path to use NAPI on XDP
On 5/31/2023 9:32 AM, Binbin Wu wrote:
From: Robert Hoo
Linear Address Masking (LAM) is a new Intel CPU feature, which allows software
to use of the untranslated address bits for metadata.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[26]
Add CPUID definition for LAM.
More info can be found
> On May 30, 2023, at 11:35 PM, Jason Wang wrote:
>
> On Wed, May 31, 2023 at 11:32 AM Jason Wang wrote:
>>
>> On Wed, May 31, 2023 at 11:17 AM Jon Kohler wrote:
>>>
>>> If kernel supports IFF_NAPI, lets use it, which is especially useful
>>> on kernels containing fb3f903769e8 ("tun:
This makes CPUTLBEntry agnostic to the address size of the guest.
When 32-bit addresses are in effect, we can simply read the low
32 bits of the 64-bit field. Similarly when we need to update
the field for setting TLB_NOTDIRTY.
For TCG backends that could in theory be big-endian, but in
practice
This will be required outside of tcg-internal.h soon.
Signed-off-by: Richard Henderson
---
include/tcg/helper-info.h | 59 +++
tcg/tcg-internal.h| 47 +--
2 files changed, 60 insertions(+), 46 deletions(-)
create mode
Create helper-gen-common.h without the target specific portion.
Use that in tcg-op-common.h. Reorg headers in target/arm to
ensure that helper-gen.h is included before helper-info.c.inc.
All other targets are already correct in this regard.
Signed-off-by: Richard Henderson
---
The only usage of gen_tb_start and gen_tb_end are here.
Move the static icount_start_insn variable into a local
within translator_loop. Simplify the two subroutines
by passing in the existing local cflags variable.
Leave only the declaration of gen_io_start in gen-icount.h.
Signed-off-by:
The bug was hidden because they happen to have the same values.
Signed-off-by: Richard Henderson
---
tcg/region.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index bef4c4756f..f8410ba5db 100644
--- a/tcg/region.c
+++
If CONFIG_USER_ONLY is ok generically, so is CONFIG_SOFTMMU,
because they are exactly opposite.
Signed-off-by: Richard Henderson
---
include/exec/poison.h | 1 -
scripts/make-config-poison.sh | 5 +++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/poison.h
Create helper-proto-common.h without the target specific portion.
Use that in tcg-op-common.h. Include helper-proto.h in target/arm
and target/hexagon before helper-info.c.inc; all other targets are
already correct in this regard.
Signed-off-by: Richard Henderson
---
This had been pulled in via exec/exec-all.h, via exec/translator.h,
but the include of exec-all.h will be removed.
Signed-off-by: Richard Henderson
---
target/hexagon/translate.c | 1 +
target/loongarch/translate.c | 3 +--
target/mips/tcg/translate.c | 1 +
3 files changed, 3 insertions(+),
This function is only used in translator.c, and uses a
target-specific typedef, abi_ptr.
Signed-off-by: Richard Henderson
---
include/exec/plugin-gen.h | 22 --
accel/tcg/translator.c| 21 +
2 files changed, 21 insertions(+), 22 deletions(-)
diff
This finally paves the way for tcg/ to be built once per mode.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 -
accel/tcg/plugin-gen.c | 1 +
tcg/region.c | 2 +-
tcg/tcg-op.c | 2 +-
tcg/tcg.c | 2 +-
5 files changed, 4 insertions(+), 4
Since the change to CPUArchState, we have a common typedef
that can always be used.
Signed-off-by: Richard Henderson
---
include/exec/helper-head.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index
The last use was removed with 2ac01d6dafab.
Fixes: 2ac01d6dafab ("translate-all: use a binary search tree to track TBs in
TBContext")
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/exec/exec-all.h
The symbol is always defined, even if to 0.
We wanted to test for TCG_OVERSIZED_GUEST == 0.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 69c05cd9da..b0d2a05403 100644
---
On 31/5/23 06:03, Richard Henderson wrote:
Create two static libraries for use by each execution mode.
Signed-off-by: Richard Henderson
---
tcg/meson.build | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Wed, May 31, 2023 at 11:47 AM Jon Kohler wrote:
>
>
>
> > On May 30, 2023, at 11:35 PM, Jason Wang wrote:
> >
> > On Wed, May 31, 2023 at 11:32 AM Jason Wang wrote:
> >>
> >> On Wed, May 31, 2023 at 11:17 AM Jon Kohler wrote:
> >>>
> >>> If kernel supports IFF_NAPI, lets use it, which is
All uses replaced with TCGContext.addr_type.
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index c0257124fa..a8f99f7e77 100644
---
Signed-off-by: Richard Henderson
---
include/exec/helper-head.h | 18 +++---
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index f863a6ef5d..a355ef8ebe 100644
--- a/include/exec/helper-head.h
+++
The goal here is only tcg/, leaving accel/tcg/ for future work.
Changes for v3:
* Prerequisites and 3 patches merged.
r~
Richard Henderson (48):
tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL
This is all that is required by tcg/ from exec-all.h.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 135 +--
include/exec/translation-block.h | 152 +++
tcg/tcg-op-ldst.c| 2 +-
3 files changed, 154
This will enable replacement of TARGET_INSN_START_WORDS in tcg.c.
Split out "tcg/insn-start-words.h" and use it in target/.
Signed-off-by: Richard Henderson
---
include/tcg/insn-start-words.h | 17 +
include/tcg/tcg-op.h | 8
include/tcg/tcg-opc.h |
This had been included via tcg-op-common.h via tcg-op.h,
but that is going away. In idef-parser.y, shuffle some
tcg related includes into a more logical order.
Signed-off-by: Richard Henderson
---
target/hexagon/genptr.c | 1 +
target/hexagon/translate.c | 1 +
On 5/30/23 23:27, Philippe Mathieu-Daudé wrote:
On 8/5/23 09:58, Cédric Le Goater wrote:
This change completes commits 5aa281d757 ("aspeed: Introduce a
spi_boot region under the SoC") and 8b744a6a47 ("aspeed: Add a
boot_rom overlap region in the SoC spi_boot container") which
introduced a
>From this remove, it's no longer clear what this is attempting
to protect. The last time a use of this define was added to
the source tree, as opposed to merely moved around, was 2008.
There have been many cleanups since that time and this is
no longer required for the build to succeed.
All uses replaced with TCGContext.addr_type.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index d47a9e3478..11955a6cc2 100644
---
On 31/5/23 06:03, Richard Henderson wrote:
From this remove, it's no longer clear what this is attempting
to protect. The last time a use of this define was added to
the source tree, as opposed to merely moved around, was 2008.
There have been many cleanups since that time and this is
no
On 31/5/23 03:23, Nicholas Piggin wrote:
Make sure each CPU gets its state set up for gdb, not just the ones
before PowerPCCPUClass has had its gdb state set up.
Cc: qemu-sta...@nongnu.org
Fixes: 707c7c2ee1 ("target/ppc: Enable reporting of SPRs to GDB")
Signed-off-by: Nicholas Piggin
---
On 5/30/23 22:34, Philippe Mathieu-Daudé wrote:
On 8/5/23 09:58, Cédric Le Goater wrote:
Simple routine to retrieve a DeviceState object on a SPI bus using its
address/cs. It will be useful for the board to wire the CS lines.
Cc: Alistair Francis
Signed-off-by: Cédric Le Goater
---
Only 'fw' pointer is marked as g_autofree, so we shoud free other
resource manually in error path.
Signed-off-by: Li Zhijian
---
V2: Delete unnecesarry check
---
hw/cxl/cxl-host.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/cxl/cxl-host.c
Move a use of TARGET_LONG_BITS out of tcg/tcg.h.
Include the new file only where required.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu_ldst.h | 3 +--
include/tcg/oversized-guest.h | 23 +++
include/tcg/tcg.h
Create tcg/tcg-op-common.h, moving everything that does not concern
TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header
instead of tcg-op.h, in preparation for compiling tcg/ only once.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-common.h | 996
All uses replaced with TCGContext.addr_type.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 503126cd66..2795242b60 100644
---
This had been included via tcg-op-common.h via tcg-op.h,
but that is going away.
It is needed for inlines within translator.h, so we might as well
do it there and not individually in each translator c file.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 1 +
This replaces of TCG_GUEST_DEFAULT_MO in tcg-op-ldst.c.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
accel/tcg/translate-all.c | 5 +
tcg/tcg-op-ldst.c | 4 +---
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/include/tcg/tcg.h
Disconnect the layout of ArchCPU from TCG compilation.
Pass the relative offset of 'env' and 'neg.tlb.f' as a parameter.
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 39 +-
include/exec/tlb-common.h| 56
This is a step toward making TranslationBlock agnostic
to the address size of the guest.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index
Create tcg/tcg-op-gvec-common.h, moving everything that does not
concern TARGET_LONG_BITS. Adjust tcg-op-gvec.c to use the new header.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-gvec-common.h | 426 +
include/tcg/tcg-op-gvec.h| 444
New wrapper around gen_io_start which takes care of the USE_ICOUNT
check, as well as marking the DisasContext to end the TB.
Remove exec/gen-icount.h.
Signed-off-by: Richard Henderson
---
MAINTAINERS | 1 -
include/exec/gen-icount.h | 6 --
This had been pulled in via exec/translator.h,
but the include of exec-all.h will be removed.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 5b53b6215d..4d88197715
Removes the only use of TARGET_LONG_BITS from tcg.h, which is to be
target independent. Move the symbol to a define in tcg-op.h, which
will continue to be target dependent. Rather than complicate matters
for the use in tb_gen_code(), expand the definition there.
Reviewed-by: Philippe
In preparation for compiling tcg/ only once, eliminate
the all_helpers array. Instantiate the info structs for
the generic helpers in accel/tcg/, and the structs for
the target-specific helpers in each translate.c.
Since we don't see all of the info structs at startup,
initialize at first use,
This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h,
via exec/exec-all.h, but the include of tcg.h will be removed.
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 1 +
target/rx/cpu.c | 1 +
target/rx/op_helper.c | 1 +
target/tricore/cpu.c | 1 +
4 files changed, 4
Move most includes from *translate*.c to translate.h, ensuring
that we get the ordering correct. Ensure cpu.h is first.
Use disas/disas.h instead of exec/log.h.
Drop otherwise unused includes.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h| 3 +++
On 31/5/23 06:03, Richard Henderson wrote:
The only usage of gen_tb_start and gen_tb_end are here.
Move the static icount_start_insn variable into a local
within translator_loop. Simplify the two subroutines
by passing in the existing local cflags variable.
Leave only the declaration of
On 31/5/23 06:03, Richard Henderson wrote:
Move most includes from *translate*.c to translate.h, ensuring
that we get the ordering correct. Ensure cpu.h is first.
Use disas/disas.h instead of exec/log.h.
Drop otherwise unused includes.
Signed-off-by: Richard Henderson
---
On 24/05/2023 15.34, Milan Zamazal wrote:
Signed-off-by: Milan Zamazal
---
tests/qtest/vhost-user-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/vhost-user-test.c b/tests/qtest/vhost-user-test.c
index e4f95b2858..8ab10732f8 100644
---
On 31/5/23 06:03, Richard Henderson wrote:
Move most includes from *translate*.c to translate.h, ensuring
that we get the ordering correct. Ensure cpu.h is first.
Use disas/disas.h instead of exec/log.h.
Drop otherwise unused includes.
Signed-off-by: Richard Henderson
---
On 30/5/23 20:03, Thomas Huth wrote:
The test_vhost_user_vga_virgl test currently fails on some CI
machines with:
qemu-system-x86_64: egl: no drm render node available
qemu-system-x86_64: egl: render node init failed
The other test in this file already checks whether there is
an error
If kernel supports IFF_NAPI, lets use it, which is especially useful
on kernels containing fb3f903769e8 ("tun: support NAPI for packets
received from batched XDP buffs"), as IFF_NAPI allows the
vhost_tx_batch path to use NAPI on XDP buffs.
Benchmark w/ iperf -c (remote srv) -P (thread count) -l
On Wed, May 31, 2023 at 11:55 AM Jason Wang wrote:
>
> On Wed, May 31, 2023 at 11:47 AM Jon Kohler wrote:
> >
> >
> >
> > > On May 30, 2023, at 11:35 PM, Jason Wang wrote:
> > >
> > > On Wed, May 31, 2023 at 11:32 AM Jason Wang wrote:
> > >>
> > >> On Wed, May 31, 2023 at 11:17 AM Jon Kohler
On 31/5/23 06:03, Richard Henderson wrote:
Since the change to CPUArchState, we have a common typedef
that can always be used.
Signed-off-by: Richard Henderson
---
include/exec/helper-head.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Hi Li,
On 31/5/23 04:34, Li Zhijian wrote:
Only 'fw' pointer is marked as g_autofree, so we shoud free other
resource manually in error path.
Signed-off-by: Li Zhijian
---
V2: Delete unnecesarry check
---
hw/cxl/cxl-host.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
On Wed, May 31, 2023 at 11:32 AM Jason Wang wrote:
>
> On Wed, May 31, 2023 at 11:17 AM Jon Kohler wrote:
> >
> > If kernel supports IFF_NAPI, lets use it, which is especially useful
> > on kernels containing fb3f903769e8 ("tun: support NAPI for packets
> > received from batched XDP buffs"), as
Two headers are not required for the rest of the
contents of plugin-gen.h.
Signed-off-by: Richard Henderson
---
include/exec/plugin-gen.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h
index e9a976f815..52828781bc 100644
---
The replacement isn't ideal, as the raw count of bits
is not easily synced with exec/cpu-all.h, but it does
remove from tcg.h the target dependency on TARGET_PAGE_BITS_MIN
which is built into TLB_FLAGS_MASK.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 3 +++
include/tcg/tcg.h
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