Big (SMT8) cores have a complicated function to map the core, thread ID
to pervasive topology (PIR). Fix this for power8, power9, and power10.
Signed-off-by: Caleb Schlossin
---
include/hw/ppc/pnv_chip.h | 2 +-
include/hw/ppc/pnv_core.h | 1 +
hw/ppc/pnv.c | 60
On 1/24/24 04:22, Thomas Huth wrote:
Thomas Huth (4):
util/uri: Remove uri_string_unescape()
util/uri: Remove unused functions uri_resolve() and
uri_resolve_relative()
util/uri: Remove the uri_string_escape() function
util/uri: Remove unused macros ISA_RESERVED() and
On 1/20/24 00:40, Anton Johansson wrote:
--- a/accel/stubs/xen-stub.c
+++ b/accel/stubs/xen-stub.c
@@ -14,3 +14,15 @@ bool xen_allowed;
void qmp_xen_set_global_dirty_log(bool enable, Error **errp)
{
}
+
+#ifndef CONFIG_USER_ONLY
+void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t
Paolo Bonzini writes:
> Unless I'm missing something egregious, the jmp cache is only every
> populated with a valid entry by the same thread that reads the cache.
> Therefore, the contents of any valid entry are always consistent and
> there is no need for any acquire/release magic.
>
> Indeed
Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
Adding new machine Tiogapass in QEMU").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index cc59176563..4bc292ff84 100644
---
Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
of CPUs from the SoC definition") Aspeed machines use the
aspeed_soc_num_cpus() helper to set the number of CPUs.
Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e
On Tue, 23 Jan 2024 at 20:52, Michael Tokarev wrote:
>
> 23.01.2024 20:47, Thomas Huth:
> > On 23/01/2024 17.50, Michael Tokarev wrote:
> ..
>
> >> I'm picking this up for stable branches too, since there we have the same
> >> problems in CI environment. In particular, bios-tables-test almost
On 1/20/24 00:39, Anton Johansson wrote:
Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated
DisasContextBase fields.
Signed-off-by: Anton Johansson
---
include/exec/translator.h | 6 +++---
target/mips/tcg/translate.h | 3 ++-
target/hexagon/translate.c | 3 ++-
On 1/20/24 00:40, Anton Johansson wrote:
These don't vary across targets and are used in soon-to-be common code
(cputlb.c).
Signed-off-by: Anton Johansson
---
include/exec/cpu-all.h| 24
include/exec/cpu-common.h | 30 ++
2 files
On 1/23/24 22:12, Anton Johansson wrote:
On 23/01/24, Philippe Mathieu-Daudé wrote:
Hi Anton,
On 19/1/24 15:40, Anton Johansson wrote:
Adds wrapper functions around common target specific macros required by
accel/tcg.
Signed-off-by: Anton Johansson
---
include/hw/core/cpu.h | 9 +++
On 1/20/24 00:40, Anton Johansson wrote:
Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into
runtime branches.
Signed-off-by: Anton Johansson
---
accel/tcg/tcg-all.c | 25 +
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git
On 1/20/24 00:39, Anton Johansson wrote:
Prepares target for typedef'ing abi_ptr to vaddr. Fixes sign extension
bug that would result from abi_ptr being unsigned in the future.
Necessary to make memory access function signatures target agnostic.
Signed-off-by: Anton Johansson
---
On 1/20/24 00:40, Anton Johansson wrote:
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1233,19 +1233,7 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
*/
#define MMU_USER_IDX 2
-static inline int hflags_mmu_index(uint32_t hflags)
-{
-if (hflags & MIPS_HFLAG_ERL) {
On 1/20/24 00:40, Anton Johansson wrote:
Required to compile accel/tcg/translate-all.c once for softmmu targets.
The function gets quite big for some targets so uninlining makes sense.
Signed-off-by: Anton Johansson
---
include/exec/cpu-common.h | 4 +++
target/alpha/cpu.h| 11
On 1/20/24 00:40, Anton Johansson wrote:
Required by cpu_ldub_code() and friends in cputlb.c to access the MO_TE
MemOp in a target-independent way.
Signed-off-by: Anton Johansson
---
include/tcg/tcg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> Subject: Re: [PATCH] xen: Drop out of coroutine context
> xen_invalidate_map_cache_entry
>
> On Tue, 16 Jan 2024, Peng Fan (OSS) wrote:
> > From: Peng Fan
> >
> > xen_invalidate_map_cache_entry is not expected to run in a coroutine.
> > Without this, there is crash:
> >
> >
On 1/20/24 00:40, Anton Johansson wrote:
@@ -815,12 +815,13 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
unsigned bits)
{
TLBFlushRangeData d;
+const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
No, this value
On Tue, Jan 23, 2024 at 04:33:43PM +, Peter Maydell wrote:
> On Wed, 17 Jan 2024 at 19:49, Markus Armbruster wrote:
> >
> > hmp_migrate() leaks @caps when qmp_migrate() fails. Plug the leak
> > with g_autoptr().
> >
> > Fixes: 967f2de5c9ec (migration: Implement MigrateChannelList to hmp
> >
On Tue, Jan 23, 2024 at 08:21:55AM +, Daniel P. Berrangé wrote:
> On Tue, Jan 23, 2024 at 06:42:19AM +, Het Gala wrote:
> > 'uri' argument should be optional, as 'uri' and 'channels'
> > arguments are mutally exclusive in nature.
> >
> > Fixes: 074dbce5fcce (migration: New migrate and
> >
On 1/20/24 00:40, Anton Johansson wrote:
Uses target_has_precise_smc() and target_phys_addr_space_bits() to turn
ifdefs into runtime branches.
Signed-off-by: Anton Johansson
---
accel/tcg/tb-maint.c | 47 +++-
1 file changed, 25 insertions(+), 22
On 2024/01/23 19:06, Bin Meng wrote:
When configuring QEMU with --prefix=/, the generated QEMU executables
can't be relocated to other directories. Add an additional test logic
in starts_with_prefix() to handle this.
What about setting "" as CONFIG_PREFIX in Meson when --prefix=/ ?
On Tue, Jan 23, 2024 at 7:11 AM Fabiano Rosas wrote:
>
> Hao Xiang writes:
>
> > On Sun, Jan 14, 2024 at 10:02 PM Shivam Kumar
> > wrote:
> >>
> >>
> >>
> >> > On 04-Jan-2024, at 6:14 AM, Hao Xiang wrote:
> >> >
> >> > From: Juan Quintela
> >> >
> >> > We have to enable it by default until
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Instead of ignoring invalid CPU type requested by the user:
$ qemu-system-arm -M nuri -cpu cortex-a7 -S -monitor stdio
QEMU 8.2.50 monitor - type 'help' for more information
(qemu) info qom-tree
/machine
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU types.
Instead of ignoring invalid CPU type requested by the user:
$ qemu-system-arm -M midway -cpu cortex-a7 -S -monitor stdio
QEMU 8.2.50 monitor - type 'help' for more information
(qemu) info qom-tree
/machine
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/highbank.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU types.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/vexpress.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index f1b45245d5..a3561a1b56 100644
--- a/hw/arm/vexpress.c
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/xilinx_zynq.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 66d0de139f..6ec65d4780 100644
---
On 1/20/24 00:40, Anton Johansson wrote:
Signed-off-by: Anton Johansson
---
include/exec/cpu_ldst.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 6061e33ac9..eb8f3f0595 100644
--- a/include/exec/cpu_ldst.h
+++
Peter Maydell wrote:
> The const_le64() macro introduced in commit 845d80a8c7b187 turns out
> to have a bug which means that on big-endian systems the compiler
> complains if the argument isn't already a 64-bit type. This hasn't
> caused a problem yet, because there are no in-tree uses, but it
>
On Tue, 23 Jan 2024 19:15:55 +0100
Eric Auger wrote:
> aw-bits is a new option that allows to set the bit width of
> the input address range. This value will be used as a default for
> the device config input_range.end. By default it is set to 64 bits
> which is the current value.
>
>
From: Peng Fan
xen_invalidate_map_cache_entry is not expected to run in a
coroutine. Without this, there is crash:
signo=signo@entry=6, no_tid=no_tid@entry=0) at pthread_kill.c:44
threadid=) at pthread_kill.c:78
at /usr/src/debug/glibc/2.38+git-r0/sysdeps/posix/raise.c:26
On 1/20/24 00:40, Anton Johansson wrote:
+#define tcg_req_mo(type) \
+((type) & tcg_ctx->guest_mo & ~TCG_TARGET_DEFAULT_MO)
Again, no, value is out of scope.
r~
On 1/20/24 00:40, Anton Johansson wrote:
Makes translate-all.c independent of softmmu target by switching
TARGET_LONG_BITS-> target_long_bits()
TARGET_INSN_START_WORDS -> tcg_ctx->insn_start_words,
target_insn_start_words(),
On 1/20/24 00:40, Anton Johansson wrote:
Make CPUState offset calculations target independent by using that
CPUState and CPUArchState are statically guaranteed to lie next to each
other in memory.
Signed-off-by: Anton Johansson
---
accel/tcg/translator.c | 16
1 file
Since v1:
- Add missing QOM parent for CPU cores
- Dropped Aspeed changes (Cédric)
Following Gavin recent CPU type enforcement cleanups,
restrict more single-CPU ARM machines (here Cortex-A SoC).
Based-on: <20240118200643.29037-1-phi...@linaro.org> (arm-next)
Philippe Mathieu-Daudé (6):
On 1/20/24 00:39, Anton Johansson wrote:
cpu-common.h is only needed for vaddr
Signed-off-by: Anton Johansson
---
include/hw/core/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 1/20/24 00:39, Anton Johansson wrote:
Makes gen_intermediate_code() signature target agnostic so the function
can be called from accel/tcg/translate-all.c without target specifics.
Signed-off-by: Anton Johansson
---
include/exec/translator.h | 2 +-
target/alpha/translate.c | 2
On Sun, Jan 21, 2024 at 9:04 PM Alistair Francis wrote:
>
> On Tue, Jan 9, 2024 at 10:29 AM Atish Patra wrote:
> >
> > Privilege mode filtering can also be emulated for cycle/instret by
> > tracking host_ticks/icount during each privilege mode switch. This
> > patch implements that for both
On 1/20/24 00:40, Anton Johansson wrote:
Functions are target independent.
Signed-off-by: Anton Johansson
---
include/exec/cpu-all.h| 25 -
include/exec/cpu-common.h | 25 +
2 files changed, 25 insertions(+), 25 deletions(-)
Reviewed-by:
On 1/20/24 00:40, Anton Johansson wrote:
Switches computation of offsets into CPUState to use that the offset
between CPUState and CPUArchState is guaranteed to be sizeof(CPUState).
Signed-off-by: Anton Johansson
---
accel/tcg/plugin-gen.c | 15 +++
1 file changed, 7
On 1/20/24 00:40, Anton Johansson wrote:
Only depends on cpu.h.
s/Only/Doesn't/ ?
Anyway,
Reviewed-by: Richard Henderson
r~
On 1/20/24 00:40, Anton Johansson wrote:
Only depends on cpu.h.
Likewise,
Reviewed-by: Richard Henderson
r~
Signed-off-by: Anton Johansson
---
accel/tcg/tcg-runtime.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/tcg-runtime.c
On 2024/01/23 20:25, Laurent Vivier wrote:
On resume igb_vm_state_change() always calls igb_autoneg_resume()
that sets link_down to false, and thus activates the link even
if we have disabled it.
The problem can be reproduced starting qemu in paused state (-S) and
then set the link to down.
On 1/20/24 00:39, Anton Johansson wrote:
We need to be able access the variable TARGET_PAGE_* macros in a
target-independent manner.
Signed-off-by: Anton Johansson
I think you should pull all of these macros into a separate header.
The split here is a bit confusing.
r~
On 1/20/24 00:39, Anton Johansson wrote:
TARGET_PAGE_* are now target-independent for softmmu targets, and can
safely be accessed common code.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
r~
On 1/20/24 00:39, Anton Johansson wrote:
+++ b/include/exec/vaddr.h
@@ -0,0 +1,18 @@
+/* Define vaddr if it exists. */
s/if it exists//
Need a license line here. Otherwise.
Reviewed-by: Richard Henderson
r~
Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
helper to reduce code duplication.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed.c | 71 +++--
1 file changed, 28 insertions(+), 43 deletions(-)
diff --git a/hw/arm/aspeed.c
Since v1:
- Follow suggestions from Cédric from [*]
[*]
https://lore.kernel.org/qemu-devel/e13c655b-7904-4e47-a673-4efd13c26...@kaod.org/
Based-on: <20240123222508.13826-1-phi...@linaro.org>
Philippe Mathieu-Daudé (5):
hw/arm/aspeed: Remove dead code
hw/arm/aspeed: Set default CPU count
In order to alter AspeedSoCClass::cpu_type in the next
commit, introduce the aspeed_soc_cpu_type() helper to
retrieve the per-SoC CPU type from AspeedSoCClass.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast10x0.c | 2 +-
Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
Convert it to a NULL-terminated array (of a single non-NULL element).
Set MachineClass::valid_cpu_types[] to use the common machine code
to provide hints when the requested CPU is invalid (see commit
e702cbc19e ("machine:
+Gavin
On 23/1/24 23:48, Philippe Mathieu-Daudé wrote:
Since v1:
- Follow suggestions from Cédric from [*]
[*]
https://lore.kernel.org/qemu-devel/e13c655b-7904-4e47-a673-4efd13c26...@kaod.org/
Based-on: <20240123222508.13826-1-phi...@linaro.org>
Philippe Mathieu-Daudé (5):
hw/arm/aspeed:
On Wed, 24 Jan 2024, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> xen_invalidate_map_cache_entry is not expected to run in a
> coroutine. Without this, there is crash:
>
> signo=signo@entry=6, no_tid=no_tid@entry=0) at pthread_kill.c:44
> threadid=) at pthread_kill.c:78
> at
在 2024/1/15 下午4:51, Bibo Mao 写道:
CSR cpuid register is used for routing irq to different vcpus, its
value is kept unchanged since poweron. So it is not necessary to
set CSR cpuid register after system resets, and it is only set at
vm creation stage.
Signed-off-by: Bibo Mao
---
23.01.2024 20:47, Thomas Huth:
On 23/01/2024 17.50, Michael Tokarev wrote:
..
I'm picking this up for stable branches too, since there we have the same
problems in CI environment. In particular, bios-tables-test almost always
times out, even hitting retry doesn't help. Let's see how it
On 1/20/24 00:40, Anton Johansson wrote:
TLB_* macros and tlb_*() functions are target independent, move to cpu-common.h.
Signed-off-by: Anton Johansson
---
include/exec/cpu-all.h| 81 --
include/exec/cpu-common.h | 83
On 1/20/24 00:40, Anton Johansson wrote:
TCGCPUOps contains an extra function pointer when included with
NEED_CPU_H, these are moved from the middle to the end of the struct. As
such offsets to target independent function pointers don't vary in
target specific and independent code.
[Move target
On Tue, 16 Jan 2024, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> xen_invalidate_map_cache_entry is not expected to run in a
> coroutine. Without this, there is crash:
>
> signo=signo@entry=6, no_tid=no_tid@entry=0) at pthread_kill.c:44
> threadid=) at pthread_kill.c:78
> at
On 1/20/24 00:40, Anton Johansson wrote:
@@ -172,7 +172,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc,
CPUTLBDescFast *fast,
rate = desc->window_max_entries * 100 / old_size;
if (rate > 70) {
-new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS);
+
On 1/20/24 00:40, Anton Johansson wrote:
These macros are only used for softmmu targets and only used in
cputlb.c, move definitions there.
Signed-off-by: Anton Johansson
---
include/exec/cpu-defs.h | 3 ---
accel/tcg/cputlb.c | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
From: Dongwon Kim
If the guest state is paused before it gets a response for the current
scanout frame submission (resource-flush), it won't flush new frames
after being restored as it still waits for the old response, which is
accepted as a scanout render done signal. So it's needed to unblock
On 2024/01/23 17:20, Andrew Jones wrote:
On Mon, Jan 22, 2024 at 02:55:50PM +, Alex Bennée wrote:
From: Akihiko Odaki
The effective MXL value matters when booting.
I'd prefer this commit message get some elaboration. riscv_is_32bit()
is used in a variety of contexts, some where it
On 1/22/24 18:56, Alex Bennée wrote:
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions
Hi Hannes,
[+Markus as QOM/QDev rubber duck]
On 23/1/24 13:40, Hannes Reinecke wrote:
On 1/23/24 11:59, Damien Hedde wrote:
Hi all,
We are currently looking into hotplugging nvme devices and it is
currently not possible:
When nvme was introduced 2 years ago, the feature was disabled.
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
Rework aspeed_soc_num_cpus() as a new init_cpus_defaults()
helper to reduce code duplication.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed.c | 71 +++--
1 file changed, 28 insertions(+),
On 1/24/24 07:52, Philippe Mathieu-Daudé wrote:
Hi Hannes,
[+Markus as QOM/QDev rubber duck]
On 23/1/24 13:40, Hannes Reinecke wrote:
On 1/23/24 11:59, Damien Hedde wrote:
Hi all,
We are currently looking into hotplugging nvme devices and it is
currently not possible:
When nvme was
From: Ilya Leoshkevich
Currently tb_cflags() is defined in exec-all.h, which is not usable
from target-agnostic code. Move it to translation-block.h, which is.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ilya Leoshkevich
Message-ID: <20231208003754.3688038-3-...@linux.ibm.com>
From: Ilya Leoshkevich
Currently qemu_target_page_mask() is usable only from the softmmu
code. Make it possible to use it from the *-user code as well.
Make use of it in perf.c.
Signed-off-by: Ilya Leoshkevich
Message-ID: <20231208003754.3688038-2-...@linux.ibm.com>
Signed-off-by: Philippe
From: Ilya Leoshkevich
tcg/ should not depend on accel/tcg/, but perf and debuginfo
support provided by the latter are being used by tcg/tcg.c.
Since that's the only user, move both to tcg/.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ilya
Since v5:
- Rebased on commit 53e8868d69
("meson: remove OS definitions from config_targetos")
Ilya Leoshkevich (4):
target: Make qemu_target_page_mask() available for *-user
tcg: Make tb_cflags() usable from target-agnostic code
accel/tcg: Remove #ifdef TARGET_I386 from perf.c
From: Ilya Leoshkevich
Preparation for moving perf.c to tcg/.
This affects only profiling guest code, which has code in a non-0 based
segment, e.g., 16-bit code, which is not particularly important.
Suggested-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Alex Bennée
Peter Xu writes:
> On Tue, Jan 23, 2024 at 04:33:43PM +, Peter Maydell wrote:
>> On Wed, 17 Jan 2024 at 19:49, Markus Armbruster wrote:
>> >
>> > hmp_migrate() leaks @caps when qmp_migrate() fails. Plug the leak
>> > with g_autoptr().
>> >
>> > Fixes: 967f2de5c9ec (migration: Implement
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type).
Convert it to a NULL-terminated array (of a single non-NULL element).
Set MachineClass::valid_cpu_types[] to use the common machine code
to provide hints when the requested CPU
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
In order to alter AspeedSoCClass::cpu_type in the next
commit, introduce the aspeed_soc_cpu_type() helper to
retrieve the per-SoC CPU type from AspeedSoCClass.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed:
Adding new machine Tiogapass in QEMU").
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed.c | 1 -
1 file changed, 1
On Wed, 24 Jan 2024 08:41:57 +0100
Philippe Mathieu-Daudé wrote:
> Replace the manual rcu_read_(un)lock calls by the
> WITH_RCU_READ_LOCK_GUARD macro (See commit ef46ae67ba
> "docs/style: call out the use of GUARD macros").
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/9pfs/9p-synth.c
Am 23.01.24 um 19:22 schrieb Thomas Huth:
uri_string_unescape() basically does the same as the glib function
g_uri_unescape_segment(). So we can get rid of our implementation
completely by simply using the glib function instead.
Suggested-by: Stefan Weil [g_uri_unescape_string()]
The expected MTD partition detection output does not always appear on
the console, despite the test reaching the boot loader and the string
appearing in dmesg. Possibly due to an init script that quietens the
console output. Using an earlier log message improves reliability.
Signed-off-by:
Replace the manual rcu_read_(un)lock calls by the
*RCU_READ_LOCK_GUARD macros (See commit ef46ae67ba
"docs/style: call out the use of GUARD macros").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/vfio/common.c | 34 --
1 file changed, 16 insertions(+), 18
Replace the manual rcu_read_(un)lock calls by the
WITH_RCU_READ_LOCK_GUARD macro (See commit ef46ae67ba
"docs/style: call out the use of GUARD macros").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/virtio/vhost.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Replace the manual rcu_read_(un)lock calls by the
WITH_RCU_READ_LOCK_GUARD macro (See commit ef46ae67ba
"docs/style: call out the use of GUARD macros").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/display/virtio-gpu-udmabuf.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Replace the manual rcu_read_(un)lock calls by the
WITH_RCU_READ_LOCK_GUARD macro (See commit ef46ae67ba
"docs/style: call out the use of GUARD macros").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/virtio-scsi.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
Replace the manual rcu_read_(un)lock calls by the
WITH_RCU_READ_LOCK_GUARD macro (See commit ef46ae67ba
"docs/style: call out the use of GUARD macros").
Signed-off-by: Philippe Mathieu-Daudé
---
hw/9pfs/9p-synth.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
Replace the manual rcu_read_(un)lock calls by the
WITH_RCU_READ_LOCK_GUARD macro (See commit ef46ae67ba
"docs/style: call out the use of GUARD macros").
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cpu-exec.c | 24
1 file changed, 12 insertions(+), 12
Use RCU_READ_LOCK_GUARD and WITH_RCU_READ_LOCK_GUARD
to replace the manual rcu_read_(un)lock calls.
Philippe Mathieu-Daudé (6):
accel/tcg/cpu-exec: Use RCU_READ macro
hw/9pfs/9p-synth: Use RCU_READ macro
hw/display/virtio-gpu-udmabuf: Use RCU_READ macro
hw/scsi/virtio-scsi: Use RCU_READ
On 1/23/24 23:48, Philippe Mathieu-Daudé wrote:
Since commit b7f1a0cb76 ("arm/aspeed: Compute the number
of CPUs from the SoC definition") Aspeed machines use the
aspeed_soc_num_cpus() helper to set the number of CPUs.
Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc:
Add AST1030
On 24/01/24 7:13 am, Peter Xu wrote:
On Tue, Jan 23, 2024 at 08:21:55AM +, Daniel P. Berrangé wrote:
On Tue, Jan 23, 2024 at 06:42:19AM +, Het Gala wrote:
'uri' argument should be optional, as 'uri' and 'channels'
arguments are mutally exclusive in nature.
Fixes: 074dbce5fcce
This test seems to be flaky, it hangs without ever getting the
MTD partition message. But I think it might be the init process
quieting the kernel console messages that just happens to run
first. P10 seems to just hit this up more, maybe small timing
differences.
So I'll send a patch to adjust
On Jan 23 13:40, Hannes Reinecke wrote:
> On 1/23/24 11:59, Damien Hedde wrote:
> > Hi all,
> >
> > We are currently looking into hotplugging nvme devices and it is currently
> > not possible:
> > When nvme was introduced 2 years ago, the feature was disabled.
> > > commit
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH rfcv1 4/6] vfio: initialize IOMMUFDDevice and pass to
>vIOMMU
>
>On 1/15/24 11:13, Zhenzhong Duan wrote:
>> Initialize IOMMUFDDevice in vfio and pass to vIOMMU, so that vIOMMU
>> could get hw IOMMU information.
>>
>> In
Hanlde wrap around when calculating the viewport size
caused by the fact that perior to version 460A the limit variable
was 32bit quantity and not 64 bits quantity.
In the i.MX 6Dual/6Quad Applications Processor Reference Manual
document on which the original code was based
On 1/19/24 08:31, Duan, Zhenzhong wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Subject: Re: [PATCH rfcv1 1/6] backends/iommufd_device: introduce
>> IOMMUFDDevice
>>
>>
>>
>> On 1/15/24 11:13, Zhenzhong Duan wrote:
>>> IOMMUFDDevice represents a device in iommufd and can be
On Tue, 23 Jan 2024 10:13, Philippe Mathieu-Daudé wrote:
Hi Manos,
On 23/1/24 09:09, Manos Pitsidianakis wrote:
Add a simple method to return some kind of human readable identifier for
use in error messages.
Signed-off-by: Manos Pitsidianakis
---
hw/core/qdev.c | 10 ++
From: Anastasia Belova
j is used while loading an ELF file to byteswap segments'
data. If data is larger than 2GB an overflow may happen.
So j should be elf_word.
This commit fixes a minor bug: it's unlikely anybody is trying to
load ELF files with 2GB+ segments for wrong-endianness targets,
From: Mark Cave-Ayland
The am53c974/dc390 PCI interrupt has two separate sources: the first is from the
internal ESP device, and the second is from the PCI DMA transfer logic.
Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT rather than
driving the PCI IRQ directly, and
From: Mark Cave-Ayland
The setting of DMA_STAT_DONE at the end of a DMA transfer can be configured to
generate an interrupt, however the Linux driver manually checks for
DMA_STAT_DONE
being set and if it is, considers that a DMA transfer has completed.
If DMA_STAT_DONE is set but the ESP
From: guoguangyao
The PCREL patches introduced a bug when updating EIP in the !CF_PCREL case.
Using s->pc in func gen_update_eip_next() solves the problem.
Cc: qemu-sta...@nongnu.org
Fixes: b5e0d5d22fbf ("target/i386: Fix 32-bit wrapping of pc/eip computation")
Signed-off-by: guoguangyao
The following patches are queued for QEMU stable v7.2.9:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2024-01-27, and the release is planned for 2024-01-29:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any additional
From: Richard Henderson
In 32-bit mode, pc = eip + cs_base is also 32-bit, and must wrap.
Failure to do so results in incorrect memory exceptions to the guest.
Before 732d548732ed, this was implicitly done via truncation to
target_ulong but only in qemu-system-i386, not qemu-system-x86_64.
To
From: Paolo Bonzini
For PC-relative translation blocks, env->eip changes during the
execution of a translation block, Therefore, QEMU must be able to
recover an instruction's PC just from the TranslationBlock struct and
the instruction data with. Because a TB will not span two pages, QEMU
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