>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
>compatibility check with host IOMMU cap/ecap
>
>On 4/25/24 10:46, Duan, Zhenzhong wrote:
>> Hi Cédric,
>>
>>> -Original Message-
>>> From: Cédric Le Goater
>>> Subject:
Vladimir Sementsov-Ogievskiy writes:
> Now we do set MIGRATION_FAILED state, but don't give a chance to
> orchestrator to query migration state and get the error.
>
> Let's provide a possibility for QMP-based orchestrators to get an error
> like with outgoing migration.
>
> For
Fabiano Rosas writes:
> The 'skipped' field of the MigrationStats struct has been deprecated
> in 8.1. Time to remove it.
>
> Deprecation commit 7b24d32634 ("migration: skipped field is really
> obsolete.").
>
> Signed-off-by: Fabiano Rosas
> ---
> docs/about/deprecated.rst | 6 --
>
From: Dongwon Kim
Draw routine needs to be manually invoked in the next refresh
if there is a scanout blob from the guest. This is to prevent
a situation where there is a scheduled draw event but it won't
happen bacause the window is currently in inactive state
(minimized or tabified). If draw
On 2024/4/17 7:04, Daniel Henrique Barboza wrote:
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
On 2024/4/17 7:04, Daniel Henrique Barboza wrote:
We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":
"The Privileged Spec says that breakpoint exceptions that occur on
instruction
On Wed, Apr 24, 2024 at 8:49 PM Richard Henderson
wrote:
>
> On 4/24/24 01:14, Paolo Bonzini wrote:
> > The following changes since commit 62dbe54c24dbf77051bafe1039c31ddc8f37602d:
> >
> >Update version for v9.0.0-rc4 release (2024-04-16 18:06:15 +0100)
> >
> > are available in the Git
Hao Xiang writes:
> * Use a safe thread queue for DSA task enqueue/dequeue.
> * Implement DSA task submission.
> * Implement DSA batch task submission.
>
> Signed-off-by: Hao Xiang
> ---
> include/qemu/dsa.h | 28 +++
> util/dsa.c | 201
Hi Peter,
I ran the avocado tests and this patch looks good to me.
The only comment I have would be that the `test_arm-Orangepi_bionic_20_08`
is not executed anymore since the image is not available, but I guess that
can be another patch.
On Thu, Apr 25, 2024 at 9:31 PM Peter Maydell
wrote:
://github.com/philmd/qemu.git tags/hw-misc-20240425
for you to fetch changes up to 098de99aad1aa911b4950b47b55d2e2bcc4f9c0c:
hw/core: Support module-id in numa configuration (2024-04-25 12:48:12 +0200)
2 checkpatch issues:
- one spurious:
WARNING: added, moved or deleted file(s), does MAINTAINERS
ping
On 11/04/2024 18:18, Jonathan Cameron wrote:
> On Tue, 9 Apr 2024 15:58:46 +0800
> Li Zhijian wrote:
>
>> After the kernel commit
>> 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not
>> match a CFMWS window")
>> CXL type3 devices cannot be enabled again after the
On 25/04/2024 22.56, Philippe Mathieu-Daudé wrote:
Hi Thomas,
On 25/4/24 20:43, Thomas Huth wrote:
For downstream versions of QEMU, we'd like to be able to compile QEMU
without the FDC code included (since it's not required for modern VMs
anymore and the FDC code has rather a bad reputation,
On Tue, Apr 23, 2024 at 10:42 PM Mark Cave-Ayland
wrote:
> > Let's change "Despite claims to the contrary" with "Despite a
> > confusing description".
>
> Thanks for sorting this, Paolo. I suspect that KVM needs a similar patch as
> per
>
On 22/4/24 22:06, Bernhard Beschow wrote:
Given that memory_region_set_readonly() is a no-op when the readonlyness is
already as requested it is possible to simplify the pattern
if (condition) {
foo(true);
}
to
foo(condition);
which is shorter and allows to see the invariant of
On 22/4/24 22:06, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_sysfw.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Hi Bernhard,
On 22/4/24 22:06, Bernhard Beschow wrote:
Now that the -bios and -pflash code paths work the same it is possible to have a
common implementation.
While at it convert the magic number 0x10 (== 1MiB) to increase readability.
Signed-off-by: Bernhard Beschow
---
On 18/04/24, Philippe Mathieu-Daudé wrote:
> On 18/4/24 21:25, Philippe Mathieu-Daudé wrote:
> > The CPUBreakpoint and CPUWatchpoint structures are declared
> > in "hw/core/cpu.h", which contains declarations related to
> > CPUState and CPUClass. Some source files only require the
> > BP/WP
On 18/04/24, Philippe Mathieu-Daudé wrote:
> Declare tlb_vaddr_to_host() in "exec/cputlb.h" with the CPU TLB
> API. Un-inline the user emulation definition to avoid including
> "exec/cpu_ldst.h" (which declares g2h) in "exec/cputlb.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On 18/04/24, Philippe Mathieu-Daudé wrote:
> Restrict iotlb_to_section(), address_space_translate_for_iotlb()
> and memory_region_section_get_iotlb() to TCG. Declare them in
> "exec/cputlb.h". Declare iotlb_to_section() using the
> MemoryRegionSection typedef.
>
> Signed-off-by: Philippe
At 2024-04-23 14:04:29, "Alistair Francis" wrote:
>On Tue, Apr 9, 2024 at 11:46 AM yang.zhang wrote:
>>
>> From: "yang.zhang"
>>
>> Since only root APLICs can have hw IRQ lines, aplic->parent should
>> be initialized first.
>>
>> Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device
On 18/04/24, Philippe Mathieu-Daudé wrote:
> GUEST_ADDR_MAX is only used in accel/tcg/user-exec.c
> and "exec/cpu_ldst.h". Move it from "exec/cpu-all.h"
> to "exec/cpu_ldst.h" so we can avoid including
> "exec/cpu-all.h" in accel/tcg/user-exec.c.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On 24.04.24 20:33, Collin Walling wrote:
On 4/24/24 03:24, David Hildenbrand wrote:
On 23.04.24 23:06, Collin Walling wrote:
Retain a list of deprecated features disjoint from any particular
CPU model. When a query-cpu-model-expansion is provided with the
"disable-deprecated-feats" option set,
Hi Cédric,
>-Original Message-
>From: Cédric Le Goater
>Subject: Re: [PATCH v2 3/5] intel_iommu: Add a framework to do
>compatibility check with host IOMMU cap/ecap
>
>Hello Zhenzhong,
>
>On 4/18/24 10:42, Duan, Zhenzhong wrote:
>> Hi Cédric,
>>
>>> -Original Message-
>>> From:
Hi Xiaoyao,
On Wed, Apr 24, 2024 at 11:57:11PM +0800, Xiaoyao Li wrote:
> Date: Wed, 24 Apr 2024 23:57:11 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH for-9.1 0/7] target/i386/kvm: Cleanup the kvmclock
> feature name
>
> On 3/29/2024 6:19 PM, Zhao Liu wrote:
> > From: Zhao Liu
> >
> > Hi
On Wed, 24 Apr 2024 at 13:31, Mark Cave-Ayland
wrote:
>
> On 23/04/2024 12:05, Philippe Mathieu-Daudé wrote:
>
> > On 23/4/24 11:18, Manos Pitsidianakis wrote:
> >> On Tue, 23 Apr 2024 at 11:47, Manos Pitsidianakis
> >> wrote:
> >>>
> >>> On Tue, 23 Apr 2024 at 00:11, Michael S. Tsirkin wrote:
Collin Walling writes:
> On 4/24/24 02:19, Markus Armbruster wrote:
>> Collin Walling writes:
>>
>>> This optional parameter for query-cpu-model-expansion enables CPU
>>> model features flagged as deprecated to appear in the resulting
>>> list of properties.
>>>
>>> This commit does not add
On 25.04.24 00:52, Peter Xu wrote:
On Wed, Apr 24, 2024 at 10:50:14PM +0300, Vladimir Sementsov-Ogievskiy wrote:
On 24.04.24 22:40, Peter Xu wrote:
On Wed, Apr 24, 2024 at 08:42:44PM +0300, Vladimir Sementsov-Ogievskiy wrote:
1. Most of callers want to free the error after call. Let's help
On 4/25/2024 3:17 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Wed, Apr 24, 2024 at 11:57:11PM +0800, Xiaoyao Li wrote:
Date: Wed, 24 Apr 2024 23:57:11 +0800
From: Xiaoyao Li
Subject: Re: [PATCH for-9.1 0/7] target/i386/kvm: Cleanup the kvmclock
feature name
On 3/29/2024 6:19 PM, Zhao Liu wrote:
From: Prasad Pandit
Libaio defines IO_CMD_FDSYNC command to sync all outstanding
asynchronous I/O operations, by flushing out file data to the
disk storage. Enable linux-aio to submit such aio request.
When using aio=native without fdsync() support, QEMU creates
pthreads, and destroying these
On 18/04/24, Philippe Mathieu-Daudé wrote:
> cpu_physical_memory_write() is declared in "exec/cpu-common.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/xtensa/bootparam.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/xtensa/bootparam.h b/hw/xtensa/bootparam.h
> index
On Thu, Apr 25, 2024 at 07:11:41AM +0200, Thomas Huth wrote:
> On 24/04/2024 18.21, Richard Henderson wrote:
> > On 4/24/24 00:57, Thomas Huth wrote:
> > > The following changes since commit
> > > 13b1e9667737132440f4d500c31cb69320c6b15a:
> > >
> > > Merge tag 'for-upstream' of
On 22/4/24 22:06, Bernhard Beschow wrote:
This series changes the "isa-bios" MemoryRegion to be an alias rather than a
copy in the pflash case. This fixes issuing pflash commands in the isa-bios
region which matches real hardware and which some real-world legacy bioses I'm
running rely on.
Hi Zhao,
On 24/4/24 17:49, Zhao Liu wrote:
---
Zhao Liu (20):
hw/core/machine: Introduce the module as a CPU topology level
hw/core/machine: Support modules in -smp
hw/core: Introduce module-id as the topology subindex
hw/core: Support module-id in numa configuration
To reduce
On 25/4/24 09:39, Anton Johansson wrote:
On 18/04/24, Philippe Mathieu-Daudé wrote:
The include/user/ directory contains the user-emulation
specific headers. Move guest-base.h there too.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-all.h | 2 +-
include/{exec =>
On 18/04/24, Philippe Mathieu-Daudé wrote:
> Declare tlb_reset_dirty() and tlb_reset_dirty_range_all()
> in "exec/cputlb.h". Restrict tlb_reset_dirty_range_all()
> to TCG accel.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/exec/cputlb.h | 12 +++-
>
On 18/04/24, Philippe Mathieu-Daudé wrote:
> The include/user/ directory contains the user-emulation
> specific headers. Move guest-base.h there too.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/exec/cpu-all.h | 2 +-
> include/{exec => }/user/guest-base.h | 4 ++--
>
On 18/04/24, Philippe Mathieu-Daudé wrote:
> Declare 'have_guest_base' in "user/guest-base.h".
>
> Very few files require this header, so explicitly include
> it there instead of "exec/cpu-all.h" which is used in many
> source files.
>
> Assert this user-specific header is only included from
On 25/04/2024 07:30, Manos Pitsidianakis wrote:
On Wed, 24 Apr 2024 at 13:31, Mark Cave-Ayland
wrote:
On 23/04/2024 12:05, Philippe Mathieu-Daudé wrote:
On 23/4/24 11:18, Manos Pitsidianakis wrote:
On Tue, 23 Apr 2024 at 11:47, Manos Pitsidianakis
wrote:
On Tue, 23 Apr 2024 at 00:11,
On 25/04/24, Anton Johansson via wrote:
> On 18/04/24, Philippe Mathieu-Daudé wrote:
> > Declare tlb_vaddr_to_host() in "exec/cputlb.h" with the CPU TLB
> > API. Un-inline the user emulation definition to avoid including
> > "exec/cpu_ldst.h" (which declares g2h) in "exec/cputlb.h".
> >
> >
On Wed, 24 Apr 2024 at 19:13, Alexandra Diupina wrote:
>
> Add a function xlnx_dpdma_read_descriptor() that
> combines reading the descriptor from desc_addr
> by calling dma_memory_read() and swapping desc
> fields from guest memory order to host memory order.
>
> Found by Linux Verification
I just realized I dropped this on the floor. I apologize for the delay.
Daniel P. Berrangé writes:
> On Mon, Jan 08, 2024 at 06:23:37PM +, Daniel P. Berrangé wrote:
>> The general expectation is that header files should follow the same
>> file/path naming scheme as the corresponding source
在 2024/4/24 5:04, Ira Weiny 写道:
Alison Schofield wrote:
On Wed, Apr 17, 2024 at 03:50:52PM +0800, Shiyang Ruan wrote:
[snip]
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index e5f13260fc52..cdfce932d5b1 100644
--- a/drivers/cxl/core/trace.h
+++
On Mon, Apr 22, 2024 at 10:06:21PM +0200, Bernhard Beschow wrote:
> This series changes the "isa-bios" MemoryRegion to be an alias rather than a
> copy in the pflash case. This fixes issuing pflash commands in the isa-bios
> region which matches real hardware and which some real-world legacy
On Thu, 25 Apr 2024 at 13:24, Michael S. Tsirkin wrote:
>
> On Thu, Apr 25, 2024 at 01:04:31PM +0300, Manos Pitsidianakis wrote:
> > On Thu, 25 Apr 2024 at 10:49, Mark Cave-Ayland
> > wrote:
> > >
> > > On 25/04/2024 07:30, Manos Pitsidianakis wrote:
> > >
> > > > On Wed, 24 Apr 2024 at 13:31,
24.04.2024 20:39, Michael Tokarev wrote:
Hi everyone,
The QEMU v8.2.3 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-8.2.3.tar.xz
Some devices and machines need to handle the reset before a vmsave
snapshot is loaded differently -- the main user is the handling of
RNG seed information, which does not want to put a new RNG seed into
a ROM blob when we are doing a snapshot load.
Currently this kind of reset handling is
Rather than directly calling the device's implementation of its 'hold'
reset phase, call device_cold_reset(). This means we don't have to
adjust this callsite when we add another argument to the function
signature for the hold and exit reset methods.
Signed-off-by: Peter Maydell
Reviewed-by:
Hi Alexandra,
On 25/4/24 12:07, Alexandra Diupina wrote:
Add a function xlnx_dpdma_read_descriptor() that
combines reading the descriptor from desc_addr
by calling dma_memory_read() and swapping desc
fields from guest memory order to host memory order.
Found by Linux Verification Center
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI
bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit
should be set or clear
From: Jinjie Ruan
In vCPU Interface, if the vIRQ has the non-maskable property, report
vINMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240407081733.3231820-23-ruanjin...@huawei.com
Signed-off-by: Peter Maydell
From: Arnaud Minier
Add the basic infrastructure (register read/write, type...)
to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART
of the STM32L4x5 to deduplicate code and enable the
implementation of different behaviors depending on the type.
From: Jinjie Ruan
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter
From: Arnaud Minier
Add a function to change the settings of the
serial connection.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
Message-id: 20240329174402.60382-4-arnaud.min...@telecom-paris.fr
Signed-off-by: Peter Maydell
---
From: Jinjie Ruan
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240407081733.3231820-7-ruanjin...@huawei.com
Signed-off-by: Peter Maydell
---
target/arm/cpu-qom.h | 5
From: Jinjie Ruan
Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it
is not GICv2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Message-id: 20240407081733.3231820-12-ruanjin...@huawei.com
Signed-off-by: Peter Maydell
---
hw/arm/virt.c | 10 +-
1
From: Jinjie Ruan
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is
higher than 0x80, otherwise it is higher than 0x0. And save the interrupt
non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR
and GICD can deliver NMI, it is both necessary to
From: Arnaud Minier
Add the USART to the SoC and connect it to the other implemented devices.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Peter Maydell
Message-id: 20240329174402.60382-5-arnaud.min...@telecom-paris.fr
[PMM: fixed a few checkpatch nits]
Signed-off-by:
From: Anastasia Belova
In soc_dma_set_request() we try to set a bit in a uint64_t, but we
do it with "1 << ch->num", which can't set any bits past 31;
any use for a channel number of 32 or more would fail due to
integer overflow.
This doesn't happen in practice for our current use of this code,
From: Jinjie Ruan
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to
Cédric Le Goater writes:
> Since vfio_ccw_register_irq_notifier() takes an 'Error **' argument,
> best practices suggest to return a bool. See the qapi/error.h Rules
> section.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/vfio/ccw.c | 22 +++---
> 1 file changed, 11
From: Zhao Liu
In x86, module is the topology level above core, which contains a set
of cores that share certain resources (in current products, the resource
usually includes L2 cache, as well as module scoped features and MSRs).
Though smp.clusters could also share the L2 cache resource [1],
Commit fd3f7d24d4 ("include/hw/core: Remove i386 conditional
on fake_user_interrupt") remove the need to check on NEED_CPU_H.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240321154838.95771-3-phi...@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 3 ---
1
From: Zhao Liu
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
So make ct3_build_cdat() return boolean, and this is the preparation for
cxl_doe_cdat_init() returning boolean.
Suggested-by: Markus Armbruster
Signed-off-by: Zhao Liu
On 4/25/2024 6:29 PM, Zhao Liu wrote:
On Thu, Apr 25, 2024 at 04:40:10PM +0800, Xiaoyao Li wrote:
Date: Thu, 25 Apr 2024 16:40:10 +0800
From: Xiaoyao Li
Subject: Re: [PATCH for-9.1 0/7] target/i386/kvm: Cleanup the kvmclock
feature name
On 4/25/2024 3:17 PM, Zhao Liu wrote:
Hi Xiaoyao,
On
On Mon, Apr 22, 2024 at 02:31:36PM +0200, Andrew Jones wrote:
> On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> > kvm_riscv_handle_sbi() may return not supported return code to not
> > trigger qemu abort with vendor-specific sbi.
> >
> > Add new error path to provide proper
On Thu, Apr 25, 2024 at 11:34:46AM +0200, Markus Armbruster wrote:
> I just realized I dropped this on the floor. I apologize for the delay.
>
> Daniel P. Berrangé writes:
>
> > On Mon, Jan 08, 2024 at 06:23:37PM +, Daniel P. Berrangé wrote:
> >> The general expectation is that header
Add a function xlnx_dpdma_read_descriptor() that
combines reading the descriptor from desc_addr
by calling dma_memory_read() and swapping desc
fields from guest memory order to host memory order.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: d3c6369a96 ("introduce
From: Jinjie Ruan
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id:
We pass a ResetType argument to the Resettable class enter phase
method, but we don't pass it to hold and exit, even though the
callsites have it readily available. This means that if a device
cared about the ResetType it would need to record it in the enter
phase method to use later on. We
The npcm7xx_clk and npcm7xx_gcr device reset methods look at
the ResetType argument and only handle RESET_TYPE_COLD,
producing a warning if another reset type is passed. This
is different from how every other three-phase-reset method
we have works, and makes it difficult to add new reset types.
A
From: Jinjie Ruan
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id:
From: Jinjie Ruan
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240407081733.3231820-18-ruanjin...@huawei.com
Signed-off-by: Peter Maydell
---
hw/intc/gicv3_internal.h
From: Jinjie Ruan
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the
GIC or come from the hcrx_el2.HCRX_VINMI bit,
From: Jinjie Ruan
So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it
an error to try to set has-nmi=true for the KVM GICv3.
Signed-off-by: Jinjie Ruan
Message-id: 20240407081733.3231820-15-ruanjin...@huawei.com
Suggested-by: Peter Maydell
Signed-off-by: Peter Maydell
From: Jinjie Ruan
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked. As Richard suggested, place
ALLINT bit in PSTATE in env->pstate.
In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which
treats
Cédric Le Goater writes:
> Signed-off-by: Cédric Le Goater
Reviewed-by: Markus Armbruster
Cédric Le Goater writes:
> Signed-off-by: Cédric Le Goater
Reviewed-by: Markus Armbruster
From: Maksim Davydov
To control that creating new machine type doesn't affect the previous
types (their compat_props) and to check complex compat_props inheritance
we need qmp command to print machine type compatibility properties.
This patch adds the ability to get list of all the compat_props
From: Maksim Davydov
This script runs QEMU to obtain compat_props of machines and default
values of different types of drivers to produce comparison table. This
table can be used to compare machine types to choose the most suitable
machine or compare binaries to be sure that migration to the
Have applesmc_find_key() return a const pointer.
Since the returned buffers are not modified in
applesmc_io_data_write(), it is pointless to
delete and re-add the keys in the DeviceReset
handler. Add them once in DeviceRealize, and
discard them in the DeviceUnrealize handler.
Signed-off-by:
From: Maksim Davydov
Add a supportive property to access the path to the QEMU binary
Signed-off-by: Maksim Davydov
Reviewed-by: John Snow
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240318213550.155573-4-davydov-...@yandex-team.ru>
Signed-off-by: Philippe Mathieu-Daudé
---
From: Maksim Davydov
qmp_qom_list_properties can print default values if they are available
as qmp_device_list_properties does, because both of them use the
ObjectPropertyInfo structure with default_value field. This can be useful
when working with "not device" types (e.g. memory-backend).
From: Zhao Liu
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
With returned boolean, there's no need to dereference @errp to check
failure case.
Suggested-by: Markus Armbruster
Signed-off-by: Zhao Liu
Reviewed-by: Philippe
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240422200625.2768-2-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc_sysfw.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
From: Zhao Liu
Add module-id in CpuInstanceProperties, to locate the CPU with module
level.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
Tested-by: Babu Moger
Acked-by: Markus Armbruster
Message-ID: <20240424154929.1487382-4-zhao1@intel.com>
Signed-off-by:
On Thu, 25 Apr 2024 at 10:49, Mark Cave-Ayland
wrote:
>
> On 25/04/2024 07:30, Manos Pitsidianakis wrote:
>
> > On Wed, 24 Apr 2024 at 13:31, Mark Cave-Ayland
> > wrote:
> >>
> >> On 23/04/2024 12:05, Philippe Mathieu-Daudé wrote:
> >>
> >>> On 23/4/24 11:18, Manos Pitsidianakis wrote:
> On
On Thu, Apr 25, 2024 at 01:04:31PM +0300, Manos Pitsidianakis wrote:
> On Thu, 25 Apr 2024 at 10:49, Mark Cave-Ayland
> wrote:
> >
> > On 25/04/2024 07:30, Manos Pitsidianakis wrote:
> >
> > > On Wed, 24 Apr 2024 at 13:31, Mark Cave-Ayland
> > > wrote:
> > >>
> > >> On 23/04/2024 12:05, Philippe
On 25/04/2024 11:04, Manos Pitsidianakis wrote:
On Thu, 25 Apr 2024 at 10:49, Mark Cave-Ayland
wrote:
On 25/04/2024 07:30, Manos Pitsidianakis wrote:
On Wed, 24 Apr 2024 at 13:31, Mark Cave-Ayland
wrote:
On 23/04/2024 12:05, Philippe Mathieu-Daudé wrote:
On 23/4/24 11:18, Manos
From: Jinjie Ruan
Add a property has-nmi to the GICv3 device, and use this to set
the NMI bit in the GICD_TYPER register. This isn't visible to
guests yet because the property defaults to false and we won't
set it in the board code until we've landed all of the changes
needed to implement
From: Jinjie Ruan
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240407081733.3231820-4-ruanjin...@huawei.com
Signed-off-by: Peter Maydell
---
From: Zhao Liu
Add "modules" parameter parsing support in -smp.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
Tested-by: Babu Moger
Acked-by: Markus Armbruster
Message-ID: <20240424154929.1487382-3-zhao1@intel.com>
Signed-off-by: Philippe Mathieu-Daudé
---
sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1,
resulting in painful developer experience. Use snprintf() instead.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Message-Id: <20240411104340.6617-6-phi...@linaro.org>
Signed-off-by: Richard Henderson
---
cpu_physical_memory_write() is declared in "exec/cpu-common.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-Id: <20240418192525.97451-21-phi...@linaro.org>
---
hw/xtensa/bootparam.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/xtensa/bootparam.h
migration/ram.c: API Conversion qemu_mutex_lock(),
and qemu_mutex_unlock() to WITH_QEMU_LOCK_GUARD macro
Signed-off-by: Will Gyda
---
migration/ram.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index a975c5af16..50df1e9cd2
On Thu, Apr 25, 2024 at 01:15:43PM +0200, Philippe Mathieu-Daudé wrote:
> On 25/4/24 12:40, Mark Cave-Ayland wrote:
> > On 25/04/2024 11:26, Manos Pitsidianakis wrote:
> >
> > > On Thu, 25 Apr 2024 at 13:24, Michael S. Tsirkin wrote:
> > > >
> > > > On Thu, Apr 25, 2024 at 01:04:31PM +0300,
Bill Mills writes:
> Hi Markus,
>
> On 4/23/24 6:39 AM, Markus Armbruster wrote:
>> Gustavo Romero writes:
>>
>>> Hi Markus,
>>>
>>> Thanks for interesting in the ivshmem-flat device.
>>>
>>> Bill Mills (cc:ed) is the best person to answer your question,
>>> so please find his answer below.
Daniel P. Berrangé writes:
> Ping
>
> I don't want to spend time rebasing without opinions on whether
> this is a desirable kind of cleanup to make.
>
> (obviously this is /not/ for 9.0)
FYI, I just rebased it. Easy enough, but let's not duplicate the work.
Markus Armbruster writes:
> I just realized I dropped this on the floor. I apologize for the delay.
>
> Daniel P. Berrangé writes:
>
>> On Mon, Jan 08, 2024 at 06:23:37PM +, Daniel P. Berrangé wrote:
>>> The general expectation is that header files should follow the same
>>> file/path
On Thu, Apr 25, 2024 at 04:40:10PM +0800, Xiaoyao Li wrote:
> Date: Thu, 25 Apr 2024 16:40:10 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH for-9.1 0/7] target/i386/kvm: Cleanup the kvmclock
> feature name
>
> On 4/25/2024 3:17 PM, Zhao Liu wrote:
> > Hi Xiaoyao,
> >
> > On Wed, Apr 24, 2024
From: Jinjie Ruan
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240407081733.3231820-24-ruanjin...@huawei.com
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c
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