Re: [Qemu-devel] [PULL 0/9] ppc-for-2.12 queue 20180315

On Fri, Mar 16, 2018 at 05:25:04PM +, Peter Maydell wrote: > On 15 March 2018 at 04:18, David Gibson wrote: > > The following changes since commit 026aaf47c02b79036feb830206cfebb2a726510d: > > > > Merge remote-tracking branch > >

[Qemu-devel] [PATCH v5.2 for 2.13 0/4] tpm: Extend TPM with state migration support

This series of patches implements support for migrating the state of the external 'swtpm' TPM emulator as well as that of the TIS interface. For testing of TPM 2 (migration) please use the following git repos and branches: libtpms: - repo: https://github.com/stefanberger/libtpms -

[Qemu-devel] [PATCH v5.2 for 2.13 4/4] tpm: Add test cases that uses the external swtpm with CRB interface

Add a test program for testing the CRB with the external swtpm. The 1st test case extends a PCR and reads back the value and compares it against an expected return packet. The 2nd test case repeats the 1st test case and then migrates the external swtpm's state along with the VM state to a

[Qemu-devel] [PATCH v5.2 for 2.13 2/4] tpm: extend TPM TIS with state migration support

Extend the TPM TIS interface with state migration support. We need to synchronize with the backend thread to make sure that a command being processed by the external TPM emulator has completed and its response been received. Signed-off-by: Stefan Berger ---

[Qemu-devel] [PATCH v5.2 for 2.13 1/4] tpm: extend TPM emulator with state migration support

Extend the TPM emulator backend device with state migration support. The external TPM emulator 'swtpm' provides a protocol over its control channel to retrieve its state blobs. We implement functions for getting and setting the different state blobs. In case the setting of the state blobs fails,

[Qemu-devel] [PATCH v5.2 for 2.13 3/4] docs: tpm: add VM save/restore example and troubleshooting guide

Extend the docs related to TPM with specs related to VM save and restore and a troubleshooting guide for TPM migration. Signed-off-by: Stefan Berger --- docs/specs/tpm.txt | 106 + 1 file changed, 106 insertions(+)

[Qemu-devel] [Bug 1435359] Re: Booting kernel 3.19.2 fails most of the time

I haven't seen this for a long time so please proceed with closing this ticket. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1435359 Title: Booting kernel 3.19.2 fails most of the time Status in

Re: [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3

My apologies for the below style issues - I've already fixed them up for v4... -Aaron On Mar 16 13:58, no-re...@patchew.org wrote: > Hi, > > This series seems to have some coding style problems. See output below for > more information: > > Type: series > Message-id:

Re: [Qemu-devel] [PATCH v5.1 for 2.13 0/4] tpm: Extend TPM with state migration support

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1521242665-15807-1-git-send-email-stef...@linux.vnet.ibm.com Subject: [Qemu-devel] [PATCH v5.1 for 2.13 0/4] tpm: Extend TPM with state migration support === TEST SCRIPT

[Qemu-devel] [PATCH v5.1 for 2.13 3/4] docs: tpm: add VM save/restore example and troubleshooting guide

Extend the docs related to TPM with specs related to VM save and restore and a troubleshooting guide for TPM migration. Signed-off-by: Stefan Berger --- docs/specs/tpm.txt | 106 + 1 file changed, 106 insertions(+)

[Qemu-devel] [PATCH v5.1 for 2.13 1/4] tpm: extend TPM emulator with state migration support

Extend the TPM emulator backend device with state migration support. The external TPM emulator 'swtpm' provides a protocol over its control channel to retrieve its state blobs. We implement functions for getting and setting the different state blobs. In case the setting of the state blobs fails,

[Qemu-devel] [PATCH v5.1 for 2.13 4/4] tpm: Add test cases that uses the external swtpm with CRB interface

Add a test program for testing the CRB with the external swtpm. The 1st test case extends a PCR and reads back the value and compares it against an expected return packet. The 2nd test case repeats the 1st test case and then migrates the external swtpm's state along with the VM state to a

Re: [Qemu-devel] [PATCH v5 for 2.13 0/4] tpm: Extend TPM with state migration support

On 03/16/2018 06:00 PM, no-re...@patchew.org wrote: Hi, This series failed docker-quick@centos6 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id:

[Qemu-devel] [PATCH v5.1 for 2.13 2/4] tpm: extend TPM TIS with state migration support

Extend the TPM TIS interface with state migration support. We need to synchronize with the backend thread to make sure that a command being processed by the external TPM emulator has completed and its response been received. Signed-off-by: Stefan Berger ---

[Qemu-devel] [PATCH v5.1 for 2.13 0/4] tpm: Extend TPM with state migration support

This series of patches implements support for migrating the state of the external 'swtpm' TPM emulator as well as that of the TIS interface. For testing of TPM 2 (migration) please use the following git repos and branches: libtpms: - repo: https://github.com/stefanberger/libtpms -

[Qemu-devel] [PATCH for-2.13] i386: Helpers to encode cache information consistently

Instead of having a collection of macros that need to be used in complex expressions to build CPUID data, define a CPUCacheInfo struct that can hold information about a given cache. Helper functions will take a CPUCacheInfo struct as input to encode CPUID leaves for a cache. This will help us

Re: [Qemu-devel] [PATCH] i386/kvm: add support for KVM_CAP_X86_DISABLE_EXITS

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1521211002-4529-1-git-send-email-wanpen...@tencent.com Subject: [Qemu-devel] [PATCH] i386/kvm: add support for KVM_CAP_X86_DISABLE_EXITS === TEST SCRIPT BEGIN ===

Re: [Qemu-devel] [Qemu-block] [PATCH for-2.12 0/2] qcow2: add overlap check for bitmap directory

On 11/30/2017 11:47 AM, Vladimir Sementsov-Ogievskiy wrote: > Add simple constant overlap check. > > Vladimir Sementsov-Ogievskiy (2): > qcow2: add overlap check for bitmap directory > qcow2: fix indentation after previous patch > > block/qcow2.h | 45

Re: [Qemu-devel] [PATCH v5 for 2.13 0/4] tpm: Extend TPM with state migration support

Hi, This series failed docker-quick@centos6 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 1521236796-24551-1-git-send-email-stef...@linux.vnet.ibm.com Subject: [Qemu-devel]

[Qemu-devel] [PATCH v5 for 2.13 4/4] tpm: Add test cases that uses the external swtpm with CRB interface

Add a test program for testing the CRB with the external swtpm. The 1st test case extends a PCR and reads back the value and compares it against an expected return packet. The 2nd test case repeats the 1st test case and then migrates the external swtpm's state along with the VM state to a

[Qemu-devel] [PATCH v5 for 2.13 3/4] docs: tpm: add VM save/restore example and troubleshooting guide

Extend the docs related to TPM with specs related to VM save and restore and a troubleshooting guide for TPM migration. Signed-off-by: Stefan Berger --- docs/specs/tpm.txt | 106 + 1 file changed, 106 insertions(+)

[Qemu-devel] [PATCH v5 for 2.13 2/4] tpm: extend TPM TIS with state migration support

Extend the TPM TIS interface with state migration support. We need to synchronize with the backend thread to make sure that a command being processed by the external TPM emulator has completed and its response been received. Signed-off-by: Stefan Berger ---

[Qemu-devel] [PATCH v5 for 2.13 0/4] tpm: Extend TPM with state migration support

This series of patches implements support for migrating the state of the external 'swtpm' TPM emulator as well as that of the TIS interface. For testing of TPM 2 (migration) please use the following git repos and branches: libtpms: - repo: https://github.com/stefanberger/libtpms -

[Qemu-devel] [PATCH v5 for 2.13 1/4] tpm: extend TPM emulator with state migration support

Extend the TPM emulator backend device with state migration support. The external TPM emulator 'swtpm' provides a protocol over its control channel to retrieve its state blobs. We implement functions for getting and setting the different state blobs. In case the setting of the state blobs fails,

Re: [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1521232280-13089-1-git-send-email-alind...@codeaurora.org Subject: [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3 === TEST SCRIPT BEGIN === #!/bin/bash

Re: [Qemu-devel] [PATCH v2] RISC-V: Fix riscv_isa_string, use popcount to count bits

On Fri, Mar 16, 2018 at 10:03 AM, Michael Clark wrote: > > On Thu, Mar 15, 2018 at 12:27 PM, Peter Maydell > wrote: > >> On 10 March 2018 at 21:25, Philippe Mathieu-Daudé >> wrote: >> > On 03/09/2018 10:01 PM, Michael Clark wrote: >>

[Qemu-devel] [PATCH v3 20/22] target/arm: PMU: Add instruction and cycle events

The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay

[Qemu-devel] [PATCH v3 15/22] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions

Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 3 +++ target/arm/cpu.h | 1 + 2 files changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b0d032c..e544f1d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -765,6 +765,7 @@ static

[Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0

The pmu_counter_filtered and pmu_op_start/finish functions are generic (as opposed to PMCCNTR-specific) to allow for the implementation of other events. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c| 3 ++ target/arm/cpu.h| 37 +++

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

On 03/16/2018 07:36 PM, Michael Clark wrote: > On Fri, Mar 16, 2018 at 11:30 AM, Michael Clark wrote: > >> >> >> On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann < >> kbast...@mail.uni-paderborn.de> wrote: >> >>> Hi Mark, >>> >>> On 03/10/2018 10:40 AM, Mark Cave-Ayland

[Qemu-devel] [PATCH v3 11/22] target/arm: Fix bitmask for PMCCFILTR writes

It was shifted to the left one bit too few. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 50eaed7..0102357 100644 --- a/target/arm/helper.c +++

[Qemu-devel] [PATCH v3 19/22] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Add arrays to hold the registers, the definitions themselves, access functions, and add logic to reset counters when PMCR.P is set. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h| 7 +- target/arm/helper.c | 219

[Qemu-devel] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO

During code generation, surround CPSR writes and exception returns which call the EL change hooks with gen_io_start/end. The immediate need is for the PMU to access the clock and icount during EL change to support mode filtering. Signed-off-by: Aaron Lindsay ---

[Qemu-devel] [PATCH v3 21/22] target/arm: PMU: Set PMCR.N to 4

This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

[Qemu-devel] [PATCH v3 22/22] target/arm: Implement PMSWINC

Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 44 ++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 06e2e2c..4f8d11c 100644 --- a/target/arm/helper.c +++

[Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET

Adding an array for v7VE+ CP registers was necessary so that PMOVSSET wasn't defined for all v7 processors. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH v3 09/22] target/arm: Add pre-EL change hooks

Because the design of the PMU requires that the counter values be converted between their delta and guest-visible forms for mode filtering, an additional hook which occurs before the EL is changed is necessary. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c |

[Qemu-devel] [PATCH v3 18/22] target/arm: Add array for supported PMU events, generate PMCEID[01]

This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay ---

[Qemu-devel] [PATCH v3 17/22] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f5e800e..2073d56 100644 ---

Re: [Qemu-devel] [patches] Re: [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup

On Fri, Mar 16, 2018 at 1:06 PM, wrote: > Hi, > > This series seems to have some coding style problems. See output below for > more information: > > Type: series > Message-id: 1521229281-73637-1-git-send-email-...@sifive.com > Subject: [Qemu-devel] [PATCH v3 00/24] RISC-V

[Qemu-devel] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N

This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 24 +++- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index

[Qemu-devel] [PATCH v3 08/22] target/arm: Support multiple EL change hooks

Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 15 ++- target/arm/cpu.h | 23 --- target/arm/internals.h | 7 --- 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c

[Qemu-devel] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState

This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay --- hw/intc/arm_gicv3_cpuif.c

[Qemu-devel] [PATCH v3 13/22] target/arm: Allow AArch32 access for PMCCFILTR

Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 95b09d6..d4f06e6 100644 --- a/target/arm/helper.c +++

[Qemu-devel] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide

This is a bug fix to ensure 64-bit reads of this register don't read adjacent data. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c3b5ef..fb2f983 100644

[Qemu-devel] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync

pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Split pmccntr_sync into pmccntr_op_start and pmccntr_op_finish, passing the clock value between the two, to avoid losing time between the two calls. Signed-off-by: Aaron Lindsay

[Qemu-devel] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0

They share the same underlying state Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5e48982..5634561 100644 --- a/target/arm/helper.c +++

[Qemu-devel] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit

Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 022d8c5..072cbbf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1524,7 +1524,7 @@ static void

[Qemu-devel] [PATCH v3 01/22] target/arm: A53: Initialize PMCEID[01]

A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]. pmceid[01] are already being initialized to zero for both A15 and A57. Signed-off-by: Aaron Lindsay --- target/arm/cpu64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu64.c

[Qemu-devel] [PATCH v3 03/22] target/arm: Check PMCNTEN for whether PMCCNTR is enabled

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 09893e3..5e48982 100644 ---

[Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3

The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events and filter them based on execution mode. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition

[Qemu-devel] [PATCH] migration: Fix block migration flag case

From: "Dr. David Alan Gilbert" Fix the case where when a migration with a bad protocol is tried, we leave the block migration capability set. (This is a cut down version of my 'migration: Fix block failure cases' where it's other case was fixed by Peter's dd0ee30caeebbd )

Re: [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1521229281-73637-1-git-send-email-...@sifive.com Subject: [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup === TEST SCRIPT BEGIN === #!/bin/bash

[Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model

- Model borrowed from target/sh4/cpu.c - Rewrote riscv_cpu_list to use object_class_get_list - Dropped 'struct RISCVCPUInfo' and used TypeInfo array - Replaced riscv_cpu_register_types with DEFINE_TYPES - Marked base class as abstract Cc: Igor Mammedov Cc: Sagar Karandikar

[Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48

Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection

Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe

[Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update

After reading cpu_physical_memory_write and friends, it seems that memory_region_is_ram is a more appropriate interface, and matches the intent of the code that is calling it. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by:

[Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle

These fields are marked WARL in the specification so illegal writes are silently dropped. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt ---

[Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent

Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé --- include/hw/riscv/virt.h | 2 +- 1 file

[Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt

This is essentially dead-code elimination. Support for more local interrupts will be added in a future revision, as they will be defined in a future version of the Privileged ISA specification. Cc: Sagar Karandikar Cc: Bastian Koppelmann

[Qemu-devel] [PATCH v3 13/24] RISC-V: Make some header guards more specific

Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé --- include/hw/riscv/spike.h | 4 ++--

[Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional

Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by:

[Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case

satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and

[Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order

Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I

[Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info

mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar

[Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement

Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by: Philippe Mathieu-Daudé --- target/riscv/op_helper.c | 3 +-- 1

[Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory

>From reading other code that accesses memory regions directly, it appears that the rcu_read_lock needs to be held. Note: the original code for accessing RAM directly was added because there is no other way to use atomic_cmpxchg on guest physical address space. Cc: Sagar Karandikar

[Qemu-devel] [PATCH v3 05/24] RISC-V: Remove identity_translate from load_elf

When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar Cc: Bastian Koppelmann

[Qemu-devel] [PATCH v3 09/24] RISC-V: Include intruction hex in disassembly

This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael

[Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance

- Inline PTE_TABLE check for better readability - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Set READ flag for PTE X flag if mstatus.mxr is in effect - Change access

[Qemu-devel] [PATCH v3 07/24] RISC-V: Remove unused class definitions

Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete

[Qemu-devel] [PATCH v3 01/24] RISC-V: Make virt create_fdt interface consistent

create_fdt sets the fdt variable on RISCVVirtState and this is used to access the fdt. This reverts a change introduced in https://github.com/riscv/riscv-qemu/pull/109 which introduced a redundant return value, overlooking the RISCVVirtState structure member that made create_fdt inconsistent with

[Qemu-devel] [PATCH v3 08/24] RISC-V: Make sure rom has space for fdt

Remove a potential buffer overflow (not seen in practice). Perhaps cpu_physical_memory_write already has bound checks. This change however makes space for the maximum device tree size and adds an explicit bounds check and error message. It doesn't trigger, but it may help in the future if the

[Qemu-devel] [PATCH v3 06/24] RISC-V: Mark ROM read-only after copying in code

The sifive_u machine already marks its ROM readonly. This fixes the remaining boards. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt ---

[Qemu-devel] [PATCH v3 03/24] RISC-V: Make virt board description match spike

This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt Reviewed-by:

[Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup

This is a series of spec conformance bug fixes and code cleanups that we would like to get in before the QEMU 2.12 release. This series does not contain the fix to riscv_isa_string. Previous versions of this series have been included in the riscv.org QEMU repository and these changes have had

[Qemu-devel] [PATCH v3 02/24] RISC-V: Replace hardcoded constants with enum values

The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt

[Qemu-devel] [PATCH v3 04/24] RISC-V: Use ROM base address and size from memmap

Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Michael Clark Signed-off-by: Palmer Dabbelt

[Qemu-devel] [PULL 1/1] pc: correct misspelled CPU model-id for pc 2.2

From: Wang Xin Signed-off-by: Wang Xin Message-Id: <1517367668-25048-1-git-send-email-wangxinxin.w...@huawei.com> Acked-by: Michael S. Tsirkin Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h

[Qemu-devel] [PULL 0/1] PC compat bug fix for v2.12

Dropped all the other commits from machine-next and kept only the bug fix below. The following changes since commit 2bb39a657abeac3f33ab3298177fb27c35f5b50a: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180316' into staging (2018-03-16 17:25:33 +) are available in the Git

Re: [Qemu-devel] [PULL v2 0/7] Machine queue, 2018-03-15

On Fri, Mar 16, 2018 at 07:05:29PM +, Peter Maydell wrote: > On 15 March 2018 at 18:14, Eduardo Habkost wrote: > > Changes in v2 (v1 was 2018-03-12): > > * Fix bsd-user build error > > > > The following changes since commit 56e8698ffa8aba9f762f980bc21b5340b006f24b: > > >

Re: [Qemu-devel] [PULL v2 00/44] Block layer patches

On 15 March 2018 at 17:18, Kevin Wolf wrote: > The following changes since commit 56e8698ffa8aba9f762f980bc21b5340b006f24b: > > Merge remote-tracking branch > 'remotes/stsquad/tags/pull-travis-speedup-130318-1' into staging (2018-03-15 > 14:48:09 +) > > are available in

Re: [Qemu-devel] [PULL v2 0/7] Machine queue, 2018-03-15

On 15 March 2018 at 18:14, Eduardo Habkost wrote: > Changes in v2 (v1 was 2018-03-12): > * Fix bsd-user build error > > The following changes since commit 56e8698ffa8aba9f762f980bc21b5340b006f24b: > > Merge remote-tracking branch >

Re: [Qemu-devel] [PATCH] gdbstub: send a terminaison packet instead of crashing gdb

On 03/16/2018 05:34 PM, Peter Maydell wrote: On 16 March 2018 at 16:23, KONRAD Frederic wrote: Since the commit: commit 4486e89c219c0d1b9bd8dfa0b1dd5b0d51ff2268 Author: Stefan Hajnoczi Date: Wed Mar 7 14:42:05 2018 + vl: introduce

Re: [Qemu-devel] [PATCH] ide: fix invalid TRIM range abortion for macio

On 03/16/2018 07:20 AM, Mark Cave-Ayland wrote: > On 05/03/18 21:54, Mark Cave-Ayland wrote: > >> On 02/03/18 17:08, Anton Nefedov wrote: >> >>> commit 947858b0 "ide: abort TRIM operation for invalid range" >>> is incorrect for macio; just ide_dma_error() without doing a callback >>> is not

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

On Fri, Mar 16, 2018 at 11:30 AM, Michael Clark wrote: > > > On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann < > kbast...@mail.uni-paderborn.de> wrote: > >> Hi Mark, >> >> On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote: >> > On 10/03/18 03:02, Michael Clark wrote: >> > >> >>

Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device

On Sun, Mar 11, 2018 at 4:43 AM, Bastian Koppelmann < kbast...@mail.uni-paderborn.de> wrote: > Hi Mark, > > On 03/10/2018 10:40 AM, Mark Cave-Ayland wrote: > > On 10/03/18 03:02, Michael Clark wrote: > > > >> On Sat, Mar 10, 2018 at 1:39 AM, Philippe Mathieu-Daudé < > f4...@amsat.org> > >> wrote:

Re: [Qemu-devel] qemu master build failure

On 16 March 2018 at 18:12, Christian Borntraeger wrote: > Does it make sense to have something like > > diff --git a/configure b/configure > index 831ebf2..67d7ae3 100755 > --- a/configure > +++ b/configure > @@ -552,6 +552,10 @@ else > pwd_is_source_path="n" > fi >

Re: [Qemu-devel] qemu master build failure

On Fri, Mar 16, 2018 at 07:12:26PM +0100, Christian Borntraeger wrote: > Does it make sense to have something like > > diff --git a/configure b/configure > index 831ebf2..67d7ae3 100755 > --- a/configure > +++ b/configure > @@ -552,6 +552,10 @@ else > pwd_is_source_path="n" > fi > > +if

[Qemu-devel] [PATCH] vhost-user: avoid misaligned access

We can't pass a pointer to memory field directly since it's within a packed structure, so isn't aligned. Pass a pointer on stack and copy. Fixes: 30c4cc7 ("vhost: used_memslots refactoring") Cc: Jay Zhou Signed-off-by: Michael S. Tsirkin --- I had to

Re: [Qemu-devel] [virtio-dev] Re: [v23 1/2] virtio-crypto: Add virtio crypto device specification

On 03/16/2018 05:27 PM, Michael S. Tsirkin wrote: > On Tue, Jan 09, 2018 at 06:05:41PM +0100, Halil Pasic wrote: >>> +\item[\field{max_cipher_key_len}] is the maximum length of cipher key >>> supported by the device. >> >> I can't find what happens if this limit isn't honored by the driver.

Re: [Qemu-devel] qemu master build failure

Does it make sense to have something like diff --git a/configure b/configure index 831ebf2..67d7ae3 100755 --- a/configure +++ b/configure @@ -552,6 +552,10 @@ else pwd_is_source_path="n" fi +if test -f $source_path\/qemu-version.h -a $pwd_is_source_path = "n" ; then +error_exit "source

Re: [Qemu-devel] [PULL v2 0/3] tcg queued patches

branch > 'remotes/stsquad/tags/pull-travis-speedup-130318-1' into staging (2018-03-15 > 14:48:09 +) > > are available in the Git repository at: > > git://github.com/rth7680/qemu.git tags/pull-tcg-20180316 > > for you to fetch changes up to adb196cbd5cff26547bc32a208

Re: [Qemu-devel] [RFC v11 00/15] mutifd

On Fri, Mar 16, 2018 at 12:53:48PM +0100, Juan Quintela wrote: > Multifd > > > Hi > > [v11] > > Changes on top of previous sumbimission: > - Now on top of migration-tests/v6 that I sent on Wednesday > - Rebased to latest upstream > - Everything that is sent through the network should be

Re: [Qemu-devel] [PATCH v11 12/15] migration: Transmit initial package through the multifd channels

On Fri, Mar 16, 2018 at 12:54:00PM +0100, Juan Quintela wrote: > Signed-off-by: Juan Quintela > > -- > > Be network agnostic. > Add error checking for all values. > --- > migration/ram.c | 97 > ++--- > 1 file changed,

Re: [Qemu-devel] [PATCH v11 11/15] migration: Delay start of migration main routines

On Fri, Mar 16, 2018 at 12:53:59PM +0100, Juan Quintela wrote: > We need to make sure that we have started all the multifd threads. > > Signed-off-by: Juan Quintela > --- > migration/migration.c | 4 ++-- > migration/migration.h | 1 + > migration/ram.c | 3 +++ >

Re: [Qemu-devel] [PATCH v4 2/5] target/i386: Populate AMD Processor Cache Information

On Mon, Mar 12, 2018 at 05:00:46PM -0400, Babu Moger wrote: > From: Stanislav Lanci > > Add information for cpuid 0x801D leaf. Populate cache topology information > for different cache types(Data Cache, Instruction Cache, L2 and L3) supported > by 0x801D leaf. Please

Re: [Qemu-devel] [PATCH v11 10/15] migration: Create multifd channels

On Fri, Mar 16, 2018 at 12:53:58PM +0100, Juan Quintela wrote: > In both sides. We still don't transmit anything through them. > > Signed-off-by: Juan Quintela > --- > migration/ram.c | 50 -- > 1 file changed, 40

Re: [Qemu-devel] [PATCH v11 01/15] migration: Set error state in case of error

On Fri, Mar 16, 2018 at 05:49:07PM +, Daniel P. Berrangé wrote: > On Fri, Mar 16, 2018 at 12:53:49PM +0100, Juan Quintela wrote: > > Signed-off-by: Juan Quintela > > --- > > migration/ram.c | 20 > > 1 file changed, 20 insertions(+) > > > > diff

Re: [Qemu-devel] [PATCH v11 05/15] migration: Be sure all recv channels are created

On Fri, Mar 16, 2018 at 12:53:53PM +0100, Juan Quintela wrote: > We need them before we start migration. > > Signed-off-by: Juan Quintela > --- > migration/migration.c | 6 +- > migration/ram.c | 11 +++ > migration/ram.h | 1 + > 3 files changed,

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