Re: [PATCH v3 5/7] qapi: Introduce QAPI_LIST_APPEND

24.12.2020 01:11, Eric Blake wrote: Similar to the existing QAPI_LIST_PREPEND, but designed for use where we want to preserve insertion order. Callers will be added in upcoming patches. Note the difference in signature: PREPEND takes List*, APPEND takes List**. Signed-off-by: Eric Blake ---

Re: Problems with irq mapping in qemu v5.2

On Thu, Dec 24, 2020 at 02:34:07AM +0100, BALATON Zoltan wrote: [ ... ] > > If we need legacy mode then we may be able to emulate that by setting BARs > to legacy ports ignoring what values are written to them if legacy mode > config is set (which may be what the real chip does) and we already

[PATCH v3 4/8] hw/pci-host/bonito: Fixup pci.lomem mapping

The original mapping had wrong base address. Signed-off-by: Jiaxun Yang --- hw/pci-host/bonito.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 3fad470fc6..737ee131e1 100644 --- a/hw/pci-host/bonito.c +++

[PATCH v3 7/8] hw/mips/fuloong2e: Add highmem support

highmem starts at 0x2000. Now we can have up to 2G RAM. Signed-off-by: Jiaxun Yang --- v2: Handle SPD for dual DIMM correctly. v3: Typo corrections --- hw/mips/fuloong2e.c | 61 - 1 file changed, 49 insertions(+), 12 deletions(-) diff --git

[PATCH v3 3/8] hw/pci-host/bonito: Fixup IRQ mapping

Accroading to arch/mips/pci/fixup-fuloong2e.c in kernel, despites south bridge IRQs needs special care, all other IRQ pins are mapped by 'LOONGSON_IRQ_BASE + 25 + pin'. As south bridge IRQs are all handled by ISA bus, we can make a simple direct mapping. Signed-off-by: Jiaxun Yang --- v3:

[PATCH v3 5/8] hw/mips/fuloong2e: Remove unused env entry

modetty is not handled by kernel and the parameter here seems unreasonable. Signed-off-by: Jiaxun Yang --- v3: Bring busclock back --- hw/mips/fuloong2e.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index d846ef7b00..c4843dd15e 100644 ---

[PATCH v3 8/8] tests/acceptance: Test boot_linux_console for fuloong2e

The kernel comes from debian archive so it's trusted. Signed-off-by: Jiaxun Yang Reviewed-by: Wainer dos Santos Moschetta Reviewed-by: Willian Rampazzo Reviewed-by: Huacai Chen --- tests/acceptance/boot_linux_console.py | 21 + 1 file changed, 21 insertions(+) diff --git

[PATCH v3 6/8] hw/mips/fuloong2e: Correct cpuclock env

It was missed in 3ca7639ff00 ("hw/mips/fuloong2e: Set CPU frequency to 533 MHz"), we need to tell kernel correct clocks. Fixes: 3ca7639ff00 ("hw/mips/fuloong2e: Set CPU frequency to 533 MHz"). Signed-off-by: Jiaxun Yang Reviewed-by: Huacai Chen Reviewed-by: Philippe Mathieu-Daudé ---

[PATCH v3 2/8] hw/mips/fuloong2e: Relpace fault links

Websites are downing, but GitHub may last forever. Loongson even doesn't recogonize 2E as their products nowadays.. Signed-off-by: Jiaxun Yang Reviewed-by: Huacai Chen Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- hw/mips/fuloong2e.c | 13 +++-- 1 file

[PATCH v3 1/8] hw/mips/fuloong2e: Remove define DEBUG_FULOONG2E_INIT

Seems useless Fixes: 051c190bce5 ("MIPS: Initial support of fulong mini pc (machine construction)") Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen --- hw/mips/fuloong2e.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/mips/fuloong2e.c

[PATCH v3 0/8] hw/mips/fuloong2e fixes

It can now boot Debian installer[1] as well as a custom PMON bootloader distribution[2]. Note that it can't boot PMON shipped with actual machine as our ATI vgabios is using some x86 hack that can't be handled by x86emu in original PMON. Tree avilable at:

Re: Problems with irq mapping in qemu v5.2

在 2020/12/24 上午9:34, BALATON Zoltan 写道: On Thu, 24 Dec 2020, BALATON Zoltan wrote: On Wed, 23 Dec 2020, Guenter Roeck wrote: v3.1: pci :00:05.1: [Firmware Bug]: reg 0x10: invalid BAR (can't size) pci :00:05.1: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci :00:05.1:

Re: Problems with irq mapping in qemu v5.2

On Thu, 24 Dec 2020, BALATON Zoltan wrote: On Wed, 23 Dec 2020, Guenter Roeck wrote: v3.1: pci :00:05.1: [Firmware Bug]: reg 0x10: invalid BAR (can't size) pci :00:05.1: [Firmware Bug]: reg 0x14: invalid BAR (can't size) pci :00:05.1: [Firmware Bug]: reg 0x18: invalid BAR (can't

Re: [RFC PATCH 1/3] mm: support hugetlb free page reporting

> >>> +static int > >>> +hugepage_reporting_cycle(struct page_reporting_dev_info *prdev, > >>> + struct hstate *h, unsigned int nid, > >>> + struct scatterlist *sgl, unsigned int *offset) > >>> +{ > >>> + struct list_head *list =

[PATCH 2/3] hmp-commands: Add new HMP command for COLO passthrough

From: Zhang Chen Add hmp_colo_passthrough_add and hmp_colo_passthrough_del make user can maintain COLO network passthrough list in human monitor. Signed-off-by: Zhang Chen --- hmp-commands.hx | 26 ++ include/monitor/hmp.h | 2 ++ monitor/hmp-cmds.c| 20

[PATCH 3/3] net/colo-compare: Add handler for passthrough connection

From: Zhang Chen Currently, we just use guest's TCP/UDP source port as the key to bypass certain network traffic. Signed-off-by: Zhang Chen --- net/colo-compare.c | 49 ++ net/colo-compare.h | 2 ++ net/net.c | 27 +

[PATCH 0/3] Bypass specific network traffic in COLO

From: Zhang Chen Since the real user scenario does not need to monitor all traffic. This series give user ability to bypass kinds of network stream. Zhang Chen (3): qapi/net: Add new QMP command for COLO passthrough hmp-commands: Add new HMP command for COLO passthrough net/colo-compare:

[PATCH 1/3] qapi/net: Add new QMP command for COLO passthrough

From: Zhang Chen Since the real user scenario does not need to monitor all traffic. Add colo-passthrough-add and colo-passthrough-del to maintain a COLO network passthrough list. Signed-off-by: Zhang Chen --- net/net.c | 12 qapi/net.json | 46

Re: [RFC PATCH 1/3] mm: support hugetlb free page reporting

> > > > + spin_lock_irq(_lock); > > > > + > > > > + if (huge_page_order(h) > MAX_ORDER) > > > > + budget = HUGEPAGE_REPORTING_CAPACITY; > > > > + else > > > > + budget = HUGEPAGE_REPORTING_CAPACITY * 32; > > > > > > Wouldn't huge_page_order always be

Re: Problems with irq mapping in qemu v5.2

On Wed, 23 Dec 2020, Guenter Roeck wrote: On 12/23/20 12:20 PM, BALATON Zoltan wrote: On Wed, 23 Dec 2020, Guenter Roeck wrote: On 12/23/20 8:09 AM, Mark Cave-Ayland wrote: On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote: FWIW bisecting Fuloong2E starts failing here:

Re: Problems with irq mapping in qemu v5.2

On Wed, Dec 23, 2020 at 11:47 PM Guenter Roeck wrote: > > On Wed, Dec 23, 2020 at 10:05:12PM +, Mark Cave-Ayland wrote: > > On 23/12/2020 21:01, Guenter Roeck wrote: > > > > > I don't have a real machine, and therefore did not test it on one. > > > > > > I tried with Linux mainline

Re: Problems with irq mapping in qemu v5.2

On Wed, Dec 23, 2020 at 10:05:12PM +, Mark Cave-Ayland wrote: > On 23/12/2020 21:01, Guenter Roeck wrote: > > > I don't have a real machine, and therefore did not test it on one. > > > > I tried with Linux mainline (v5.10-12913-g614cb5894306), v3.16.85, v4.4.248, > > and v4.14.212. I can't

Re: [PATCH v1 1/1] chardev: enable guest socket status/crontrol via DTR and DCD

On 12/16/20 4:06 PM, Darrin M. Gorski wrote: > This patch adds a 'modemctl' option to "-chardev socket" to enable control > of the socket via the guest serial port. > The default state of the option is disabled. > > 1. disconnect a connected socket when DTR transitions to low, also reject > new

[PATCH v3 4/7] qapi: Use QAPI_LIST_PREPEND() where possible

Anywhere we create a list of just one item or by prepending items (typically because order doesn't matter), we can use the QAPI_LIST_PREPEND macro. But places where we must keep the list in order by appending remain open-coded until later patches. Note that as a side effect, this also performs a

[PATCH v3 6/7] qapi: Use QAPI_LIST_APPEND in trivial cases

The easiest spots to use QAPI_LIST_APPEND are where we already have an obvious pointer to the tail of a list. While at it, consistently use the variable name 'tail' for that purpose. Signed-off-by: Eric Blake --- backends/hostmem.c | 10 ++-- block/dirty-bitmap.c

[PATCH v3 5/7] qapi: Introduce QAPI_LIST_APPEND

Similar to the existing QAPI_LIST_PREPEND, but designed for use where we want to preserve insertion order. Callers will be added in upcoming patches. Note the difference in signature: PREPEND takes List*, APPEND takes List**. Signed-off-by: Eric Blake --- include/qapi/util.h | 13

[PATCH v3 1/7] net: Clarify early exit condition

On first glance, the loop in qmp_query_rx_filter() has early return paths that could leak any allocation of filter_list from a previous iteration. But on closer inspection, it is obvious that all of the early exits are guarded by has_name, and that the bulk of the loop body can be executed at

[PATCH v3 7/7] qapi: More complex uses of QAPI_LIST_APPEND

These cases require a bit more thought to review; in each case, the code was appending to a list, but not with a FOOList **tail variable. Signed-off-by: Eric Blake --- block/gluster.c| 13 ++ block/qapi.c | 14 +- dump/dump.c| 22 +++--

[PATCH v3 3/7] migration: Refactor migrate_cap_add

Instead of taking a list parameter and returning a new head at a distance, just return the new item for the caller to insert into a list via QAPI_LIST_PREPEND. Update some variable names to avoid long lines, and drop a useless comment. Signed-off-by: Eric Blake Reviewed-by: Markus Armbruster

[PATCH v3 0/7] Common macros for QAPI list growth

I worked on rebasing this while not checking my emails, and now that I'm writing it up, I see that Markus already has incorporated earlier patches in the v2 series into his tree. So I may have to rebase yet again, but it's at least time for me to get this on list again. v2 was here:

[PATCH v3 2/7] rocker: Revamp fp_port_get_info

Instead of modifying the value member of a list element passed as a parameter, and open-coding the manipulation of that list, it's nicer to just return a freshly allocated value to be prepended to a list using QAPI_LIST_PREPEND. Signed-off-by: Eric Blake Reviewed-by: Markus Armbruster ---

Re: Problems with irq mapping in qemu v5.2

On 23/12/2020 21:01, Guenter Roeck wrote: I don't have a real machine, and therefore did not test it on one. I tried with Linux mainline (v5.10-12913-g614cb5894306), v3.16.85, v4.4.248, and v4.14.212. I can't test older version because my cross compiler is too new. Each of those kernel

Re: [PATCH v15 08/20] multi-process: add qio channel read function

> On Dec 23, 2020, at 6:24 AM, Marc-André Lureau > wrote: > > Hi > > On Wed, Dec 23, 2020 at 10:17 AM wrote: > From: Elena Ufimtseva > > Adds qio_channel_readv_full_all() to read both data and FDs. > Refactors existing code to use this function. > > Signed-off-by: Elena Ufimtseva >

Re: [PATCH v2] acpi: Permit OEM ID and OEM table ID fields to be changed

Thanks for the thorough review. Igor Mammedov writes: > On Tue, 22 Dec 2020 13:33:53 +0200 > Marian Posteuca wrote: > > I see defaults are now initialized in pcmc->oem_[table_]id fields, > and sometimes used from there, so question is why > do we need use_sig_oem and keeping old code > >

[PATCH] gdbstub.c uses incorrect check for active gdb in use_gdb_syscalls

When checking whether there is a live gdb connection, code shouldn't use 'gdbserver_state.init' as that value is set when the gdbserver_state structure is initialized in init_gdbserver_state, not when the gdb socket has a valid connection. The 'handle_detach' function appears to use

[PULL 10/15] qdev: Make PropertyInfo.create return ObjectProperty*

Returning ObjectProperty* will be useful for new property registration code that will add additional callbacks to ObjectProperty after registering it. Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov Message-Id: <20201211220529.2290218-25-ehabk...@redhat.com> Signed-off-by: Eduardo

[PULL 14/15] qdev: Avoid unnecessary DeviceState* variable at set_prop_arraylen()

We're just doing pointer math with the device pointer, we can simply use obj instead. Signed-off-by: Eduardo Habkost Reviewed-by: Marc-André Lureau Reviewed-by: Igor Mammedov Message-Id: <20201211220529.2290218-32-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost ---

[PULL 15/15] bugfix: hostmem: Free host_nodes list right after visited

From: Keqian Zhu In host_memory_backend_get_host_nodes, we build host_nodes list and output it to v (a StringOutputVisitor) but forget to free the list. This fixes the memory leak. The memory leak stack: Direct leak of 32 byte(s) in 2 object(s) allocated from: #0 0xfffda30b3393 in

[PULL 09/15] qdev: Move dev->realized check to qdev_property_set()

Every single qdev property setter function manually checks dev->realized. We can just check dev->realized inside qdev_property_set() instead. Signed-off-by: Eduardo Habkost Reviewed-by: Stefan Berger Reviewed-by: Cornelia Huck Reviewed-by: Igor Mammedov Acked-by: Paul Durrant Message-Id:

[PULL 04/15] qdev: Get just property name at error_set_from_qdev_prop_error()

Replace `Property *prop` parameter with `char *name`, to reduce dependency of getter and setter functions on the Property struct (which will be changed in following patches). Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov Reviewed-by: Cornelia Huck Message-Id:

[PULL 13/15] qdev: Rename qdev_get_prop_ptr() to object_field_prop_ptr()

The function will be moved to common QOM code, as it is not specific to TYPE_DEVICE anymore. Signed-off-by: Eduardo Habkost Reviewed-by: Stefan Berger Reviewed-by: Cornelia Huck Reviewed-by: Igor Mammedov Acked-by: Paul Durrant Message-Id: <20201211220529.2290218-31-ehabk...@redhat.com>

[PULL 08/15] qdev: Wrap getters and setters in separate helpers

We'll add extra code to the qdev property getters and setters, so add wrapper functions where additional actions can be performed. The new functions have a "field_prop_" prefix instead of "qdev_" because the code will eventually be moved outside qdev-properties.c, to common QOM code.

[PULL 07/15] qdev: Add name argument to PropertyInfo.create method

This will make it easier to remove the Property.name field in the future. Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov Message-Id: <20201211220529.2290218-22-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost --- hw/core/qdev-properties.c| 7 ---

[PULL 02/15] qdev: Reuse DEFINE_PROP in all DEFINE_PROP_* macros

Instead of duplicating the code that sets name, info, offset, and does type checking, make DEFINE_PROP accept a variable number of arguments and reuse it in all DEFINE_PROP_* macros. Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov Message-Id:

[PULL 06/15] qdev: Add name parameter to qdev_class_add_property()

This will make it easier to remove Property.name in the future. Signed-off-by: Eduardo Habkost Message-Id: <20201211220529.2290218-21-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost --- hw/core/qdev-properties.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git

[PULL 12/15] qdev: Move qdev_prop_tpm declaration to tpm_prop.h

Move the variable declaration close to the macro that uses it. Signed-off-by: Eduardo Habkost Reviewed-by: Marc-André Lureau Reviewed-by: Stefan Berger Reviewed-by: Igor Mammedov Message-Id: <20201211220529.2290218-29-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost --- hw/tpm/tpm_prop.h

[PULL 05/15] qdev: Avoid using prop->name unnecessarily

We already get the property name as argument to the property getter and setters, we don't need to use prop->name. This will make it easier to remove the Property.name field in the future. Signed-off-by: Eduardo Habkost Reviewed-by: Stefan Berger Reviewed-by: Igor Mammedov Message-Id:

[PULL 11/15] qdev: Make qdev_class_add_property() more flexible

Support Property.set_default and PropertyInfo.description even if PropertyInfo.create is set. Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov Message-Id: <20201211220529.2290218-26-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost --- hw/core/qdev-properties.c | 14 ++

[PULL 01/15] qdev: Move softmmu properties to qdev-properties-system.h

Move the property types and property macros implemented in qdev-properties-system.c to a new qdev-properties-system.h header. Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov Message-Id: <20201211220529.2290218-16-ehabk...@redhat.com> Signed-off-by: Eduardo Habkost ---

[PULL 03/15] sparc: Use DEFINE_PROP for nwindows property

Use the DEFINE_PROP macro (which will set extra fields in the struct) instead of initializing a Property struct manually. Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov Acked-by: Mark Cave-Ayland Message-Id: <20201211220529.2290218-18-ehabk...@redhat.com> Signed-off-by: Eduardo

[PULL 00/15] Machine queue, 2020-12-23

The following changes since commit a05f8ecd88f15273d033b6f044b850a8af84a5b8: Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging (2020-12-18 11:12:35 +) are available in the Git repository at: https://gitlab.com/ehabkost/qemu.git

Re: Problems with irq mapping in qemu v5.2

On 12/23/20 12:20 PM, BALATON Zoltan wrote: > On Wed, 23 Dec 2020, Guenter Roeck wrote: >> On 12/23/20 8:09 AM, Mark Cave-Ayland wrote: >>> On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote: >>> On 12/22/20 5:16 PM, Guenter Roeck wrote: > Hi, > > commit 459ca8bfa41 ("pci: Assert

Re: Problems with irq mapping in qemu v5.2

On Wed, 23 Dec 2020, Guenter Roeck wrote: On 12/23/20 8:09 AM, Mark Cave-Ayland wrote: On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote: On 12/22/20 5:16 PM, Guenter Roeck wrote: Hi, commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in pci_bus_change_irq_level") added

Re: [PATCH] vhost-user: Check vhost features for CONFIGURE_MEM_SLOTS

>Agreed - VHOST_USER_PROTCOL_F_CONFIGURE_MEM_SLOTS is negotiated at the >vhost-user, not virtio layer. The dev->protocol_features flags are taken >from the VHOST_USER_GET_PROTOCOL_FEATURES message, which retrieves the >supported vhost-user features from the backend. See libvhost-user for a >simple

Re: Problems with irq mapping in qemu v5.2

On Wed, 23 Dec 2020, Philippe Mathieu-Daudé wrote: On 12/22/20 5:16 PM, Guenter Roeck wrote: Hi, commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in pci_bus_change_irq_level") added sanity checks to the interrupt number passed to pci_bus_change_irq_level(). That makes sense,

Re: [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured

On Tue, 2020-12-22 at 18:49 -0800, Richard Henderson wrote: > On 12/22/20 5:21 PM, Atish Patra wrote: > > +++ b/target/riscv/pmp.c > > @@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState > > *env, uint32_t pmp_index) > >  /* > >   * Count the number of active rules. > >   */ > >

[PATCH v2 2/2] pnv: Fix reverse dependency on PCI express root ports

qemu-system-ppc64 built with --without-default-devices crashes: Type 'pnv-phb4-root-port' is missing its parent 'pcie-root-port-base' Aborted (core dumped) Have POWERNV to select PCIE_PORT. This is done through a new PCI_POWERNV config in hw/pci-host/Kconfig since POWERNV doesn't have a direct

[PATCH v2 1/2] ppc: Fix build with --without-default-devices

Linking of the qemu-system-ppc64 fails on a POWER9 host when --without-default-devices is passed to configure: $ ./configure --without-default-devices \ --target-list=ppc64-softmmu && make ... libqemu-ppc64-softmmu.fa.p/hw_ppc_e500.c.o: In function `ppce500_init_mpic_kvm':

[PATCH v2] target/riscv/pmp: Raise exception if no PMP entry is configured

As per the privilege specification, any access from S/U mode should fail if no pmp region is configured. Signed-off-by: Atish Patra --- Changes from v2->v1 1. Removed the static from the function definition --- target/riscv/op_helper.c | 5 + target/riscv/pmp.c | 4 ++--

Re: [PATCH] multi-process: Acceptance test for multiprocess QEMU

On 12/23/20 3:44 AM, elena.ufimts...@oracle.com wrote: From: Jagannathan Raman Runs the Avocado acceptance test to check if a remote lsi53c895a device gets identified by the guest. Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Signed-off-by: Jagannathan Raman ---

Re: [PATCH] multi-process: Acceptance test for multiprocess QEMU

On Wed, Dec 23, 2020 at 03:01:24PM +0400, Marc-André Lureau wrote: > Hi > > On Wed, Dec 23, 2020 at 10:45 AM wrote: > > > From: Jagannathan Raman > > > > Runs the Avocado acceptance test to check if a > > remote lsi53c895a device gets identified by the guest. > > > > Signed-off-by: Elena

Re: [PATCH] multi-process: Acceptance test for multiprocess QEMU

Hi, On 12/23/20 8:01 AM, Marc-André Lureau wrote: Hi On Wed, Dec 23, 2020 at 10:45 AM > wrote: From: Jagannathan Raman mailto:jag.ra...@oracle.com>> Runs the Avocado acceptance test to check if a remote lsi53c895a device gets identified by the

Re: [RFC PATCH 1/3] mm: support hugetlb free page reporting

On 12/22/20 7:57 PM, Liang Li wrote: >> On 12/21/20 11:46 PM, Liang Li wrote: >>> +static int >>> +hugepage_reporting_cycle(struct page_reporting_dev_info *prdev, >>> + struct hstate *h, unsigned int nid, >>> + struct scatterlist *sgl, unsigned int

Re: Problems with irq mapping in qemu v5.2

On 23/12/2020 13:17, BALATON Zoltan via wrote: On Wed, 23 Dec 2020, Mark Cave-Ayland wrote: On 22/12/2020 21:23, Guenter Roeck wrote: (Added jiaxun.y...@flygoat.com as CC) Are you sure? It does not show up on cc list for me so unless the list ate it you might have forgotten to copy the

Re: Problems with irq mapping in qemu v5.2

On 23/12/2020 17:01, Guenter Roeck wrote: On 12/23/20 8:09 AM, Mark Cave-Ayland wrote: On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote: On 12/22/20 5:16 PM, Guenter Roeck wrote: Hi, commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in pci_bus_change_irq_level") added

[PATCH] gdb: riscv: Add target description

Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier --- target/riscv/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git

Re: Problems with irq mapping in qemu v5.2

On 12/23/20 8:09 AM, Mark Cave-Ayland wrote: > On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote: > >> On 12/22/20 5:16 PM, Guenter Roeck wrote: >>> Hi, >>> >>> commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in >>> pci_bus_change_irq_level") added sanity checks to the

Re: [RFC PATCH 1/3] mm: support hugetlb free page reporting

On Tue, Dec 22, 2020 at 7:39 PM Liang Li wrote: > > > > +hugepage_reporting_cycle(struct page_reporting_dev_info *prdev, > > > +struct hstate *h, unsigned int nid, > > > +struct scatterlist *sgl, unsigned int *offset) > > > +{ > > > + struct

Re: Problems with irq mapping in qemu v5.2

On 23/12/2020 15:21, Philippe Mathieu-Daudé wrote: On 12/22/20 5:16 PM, Guenter Roeck wrote: Hi, commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in pci_bus_change_irq_level") added sanity checks to the interrupt number passed to pci_bus_change_irq_level(). That makes

Re: Problems with irq mapping in qemu v5.2

On 12/22/20 5:16 PM, Guenter Roeck wrote: > Hi, > > commit 459ca8bfa41 ("pci: Assert irqnum is between 0 and bus->nirqs in > pci_bus_change_irq_level") added sanity checks to the interrupt number passed > to pci_bus_change_irq_level(). That makes sense, given that bus->irq_count > is indexed and

Re: scripts/gdb: issues when loading modules after lx-symbols

On Mon, Oct 5, 2020 at 3:03 PM Stefano Garzarella wrote: > On Mon, Oct 05, 2020 at 01:48:35PM +0200, Jan Kiszka wrote: > > On 05.10.20 13:05, Stefano Garzarella wrote: > > > On Mon, Oct 05, 2020 at 11:45:41AM +0200, Jan Kiszka wrote: > > >> On 05.10.20 11:29, Stefano Garzarella wrote: > > >>> On

Re: Problems with irq mapping in qemu v5.2

On Wed, 23 Dec 2020, Mark Cave-Ayland wrote: On 22/12/2020 22:23, BALATON Zoltan via wrote: I've just remembered that for sam460ex we had this commit: 484ab3dffadc (sam460ex: Fix PCI interrupts with multiple devices) that changed that mapping for that machine so I guess you got the exception

Re: Problems with irq mapping in qemu v5.2

On Tue, 22 Dec 2020, Guenter Roeck wrote: On 12/22/20 2:57 PM, BALATON Zoltan wrote: [ ... ] I've already forgot about the details but we have analysed it quite throughly back when the via ide changes were made. Here are some random pointers to threads that could have some info: This was

Re: [PATCH v5 2/2] hw/block: m25p80: Implement AAI-WP command support for SST flashes

On [2020 Dec 23] Wed 10:00:25, Bin Meng wrote: > From: Xuzhou Cheng > > Auto Address Increment (AAI) Word-Program is a special command of > SST flashes. AAI-WP allows multiple bytes of data to be programmed > without re-issuing the next sequential address location. > > Signed-off-by: Xuzhou

Re: Problems with irq mapping in qemu v5.2

On Wed, 23 Dec 2020, Mark Cave-Ayland wrote: On 22/12/2020 21:23, Guenter Roeck wrote: (Added jiaxun.y...@flygoat.com as CC) Are you sure? It does not show up on cc list for me so unless the list ate it you might have forgotten to copy the address there. Done now just in case, sorry if this

Re: [PATCH] ppc: Fix build with --without-default-devices

On Wed, 23 Dec 2020 09:55:58 +0100 Paolo Bonzini wrote: > On 23/12/20 09:10, Greg Kurz wrote: > > Linking of the qemu-system-ppc64 fails on a POWER9 host when > > --without-default-devices is passed to configure: > > > > $ ./configure --without-default-devices \ > >

Re: Various spelling fixes

Am 23.12.20 um 11:58 schrieb Michael Tokarev: An assorted set of spelling fixes in various places. Signed-off-by: Michael Tokarev diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp index 90e63b83674..2b096552719 100644 --- a/disas/nanomips.cpp +++ b/disas/nanomips.cpp @@ -840 +840 @@ int

Re: [PATCH v15 08/20] multi-process: add qio channel read function

Hi On Wed, Dec 23, 2020 at 10:17 AM wrote: > From: Elena Ufimtseva > > Adds qio_channel_readv_full_all() to read both data and FDs. > Refactors existing code to use this function. > > Signed-off-by: Elena Ufimtseva > Signed-off-by: John G Johnson > Signed-off-by: Jagannathan Raman > --- >

Re: [PATCH] multi-process: Acceptance test for multiprocess QEMU

Hi On Wed, Dec 23, 2020 at 10:45 AM wrote: > From: Jagannathan Raman > > Runs the Avocado acceptance test to check if a > remote lsi53c895a device gets identified by the guest. > > Signed-off-by: Elena Ufimtseva > Signed-off-by: John G Johnson > Signed-off-by: Jagannathan Raman > --- >

Various spelling fixes

An assorted set of spelling fixes in various places. Signed-off-by: Michael Tokarev diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp index 90e63b83674..2b096552719 100644 --- a/disas/nanomips.cpp +++ b/disas/nanomips.cpp @@ -840 +840 @@ int NMD::Disassemble(const uint16 * data, std::string

Re: [PATCH v2] acpi: Permit OEM ID and OEM table ID fields to be changed

On Tue, 22 Dec 2020 13:33:53 +0200 Marian Posteuca wrote: > Qemu's ACPI table generation sets the fields OEM ID and OEM table ID > to "BOCHS " and "BXPC" where "" is replaced by the ACPI > table name. > > Some games like Red Dead Redemption 2 seem to check the ACPI OEM ID > and OEM

Re: Problems with irq mapping in qemu v5.2

On 22/12/2020 22:23, BALATON Zoltan via wrote: I've just remembered that for sam460ex we had this commit: 484ab3dffadc (sam460ex: Fix PCI interrupts with multiple devices) that changed that mapping for that machine so I guess you got the exception with the bamboo board then. I'm not sure

Re: Problems with irq mapping in qemu v5.2

On 22/12/2020 21:23, Guenter Roeck wrote: (Added jiaxun.y...@flygoat.com as CC) I don't really have a good solution for pci_bonito_map_irq(). It may not matter much - I have not been able to boot fuloong_2e since qemu v4.0, and afaics that is the only platform using it. Maybe it is just

Re: Problems with irq mapping in qemu v5.2

On 22/12/2020 21:23, Guenter Roeck wrote: ppc4xx_pci_map_irq() is definitely buggy. I just don't know what the correct mapping should be. slot  & 3, maybe ? Yeah that doesn't look right. Certainly both the Mac PPC machines use ((pci_dev->devfn >> 3)) & 3) plus the interrupt pin so I think

Re: [PATCH 4/4] fuzz: delay IO until they can't trigger the crash

On Tue, 2020-12-22 at 13:30 -0500, Alexander Bulekov wrote: > On 201222 1922, Qiuhao Li wrote: > > On Mon, 2020-12-21 at 16:17 -0500, Alexander Bulekov wrote: > > > On 201220 0256, Qiuhao Li wrote: > > > > Since programmers usually trigger an IO just before they need > > > > it. > > > > Try to > >

[PATCH v3 5/8] acpi/gpex: Append pxb devs in ascending order

The overlap check of IO resource window would fail when Linux kernel registers an IO resource [b, c) earlier than another resource [a, b). Though this incorrect check could be fixed by [1], it would be better to append pxb devs into DSDT table in ascending order. [1]:

[PATCH v3 8/8] acpi: Update addr_trans and _DSM in expected files

Addr_trans in _CRS is changed and a new _DSM #5 method is added. Also the expected file for pxb for ARM virt does not match the source code. Update expected DSDT files accordingly, and re-enable their testing. Full diff of changed files disassembly: diff -ru

[PATCH v3 7/8] acpi: Enable pxb unit-test for ARM virt machine

No matter whether the pxb is enabled or not, the CONFIG_PXB macro in test would keep undefined. And since pxb is now enabled for ARM Virt machine by default, let's enable pxb unit-test by removing the CONFIG_PXB. Signed-off-by: Jiahui Cen --- tests/qtest/bios-tables-test.c | 4 1 file

[PATCH v3 0/8] acpi: Some fixes for pxb support for ARM virt machine

This patch series adds some fixes for ARM virt machine pxb support. 1. Pass addr offset for IO, MMIO and bus number when builing crs, because the addr_trans is needed to describe an addr resource. [1] 2. Inform guest os not to ignore the resource map generated by firmware as the x86 default way.

[PATCH v3 1/8] acpi: Allow DSDT acpi table changes

Signed-off-by: Jiahui Cen --- tests/qtest/bios-tables-test-allowed-diff.h | 5 + 1 file changed, 5 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..42418e58e7 100644 ---

[PATCH v3 2/8] acpi: Add addr offset in build_crs

AML needs Address Translation offset to describe how a bridge translates addresses accross the bridge when using an address descriptor, and especially on ARM, the translation offset of pio resource is usually non zero. Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus

[PATCH v3 4/8] acpi/gpex: Exclude pxb's resources from PCI0

Exclude the resources of extra root bridges from PCI0's _CRS. Otherwise, the resource windows would overlap in guest, and the IO resource window would fail to be registered. Signed-off-by: Jiahui Cen --- hw/pci-host/gpex-acpi.c | 64 +--- 1 file changed, 43 insertions(+), 21

[PATCH v3 3/8] acpi/gpex: Inform os to keep firmware resource map

There may be some differences in pci resource assignment between guest os and firmware. Eg. A Bridge with Bus [d2] -+-[:d2]---01.0-[d3]01.0 where [d2:01.00] is a pcie-pci-bridge with BAR0 (mem, 64-bit, non-pref) [size=256] [d3:01.00] is a PCI Device with BAR0 (mem,

[PATCH v3 6/8] Kconfig: Enable PXB for ARM_VIRT by default

PXB is now supported on ARM, so let's enable it by default. Signed-off-by: Jiahui Cen --- hw/pci-bridge/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-bridge/Kconfig b/hw/pci-bridge/Kconfig index a51ec716f5..f8df4315ba 100644 --- a/hw/pci-bridge/Kconfig +++

Re: [PATCH] ppc: Fix build with --without-default-devices

On 23/12/20 09:10, Greg Kurz wrote: Linking of the qemu-system-ppc64 fails on a POWER9 host when --without-default-devices is passed to configure: $ ./configure --without-default-devices \ --target-list=ppc64-softmmu && make ... libqemu-ppc64-softmmu.fa.p/hw_ppc_e500.c.o: In

Re: [PATCH] char-socket: disable reconnect timer in the sync connect

Hi On Mon, Dec 21, 2020 at 6:06 PM Wang Xin wrote: > From: suruifeng > > The qio_channel_socket_connect_sync maybe called twice if the > openvswitchd restart during we attaching a vhost-user nic. > > -> call trace 1: > net_vhost_user_init > tcp_chr_wait_connected //loop call sync connect

[PATCH] ppc: Fix build with --without-default-devices

Linking of the qemu-system-ppc64 fails on a POWER9 host when --without-default-devices is passed to configure: $ ./configure --without-default-devices \ --target-list=ppc64-softmmu && make ... libqemu-ppc64-softmmu.fa.p/hw_ppc_e500.c.o: In function `ppce500_init_mpic_kvm':