Re: [PATCH] hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset()

Peter Maydell writes: > The omap_mmc_reset() function resets its SD card via > device_legacy_reset(). We know that the SD card does not have a qbus > of its own, so the new device_cold_reset() function (which resets > both the device and its child buses) is equivalent here to >

[Bug 1911075] Re: [OSS-Fuzz] ahci: stack overflow in ahci_cond_start_engines

This is an automated cleanup. This bug report has been moved to QEMU's new bug tracker on gitlab.com and thus gets marked as 'expired' now. Please continue with the discussion here: https://gitlab.com/qemu-project/qemu/-/issues/62 ** Changed in: qemu Status: Confirmed => Expired **

[Bug 1918302] Re: qemu-system-arm segfaults while servicing SYS_HEAPINFO

This is an automated cleanup. This bug report has been moved to QEMU's new bug tracker on gitlab.com and thus gets marked as 'expired' now. Please continue with the discussion here: https://gitlab.com/qemu-project/qemu/-/issues/61 ** Changed in: qemu Status: Confirmed => Expired **

Re: [Trivial] docs: More precisely describe memory-backend-*::id's user

Robert Hoo writes: > 'id' of memory-backend-{file,ram} is not only for '-numa''s reference, but > also other parameters like '-device nvdimm'. > More clearly call out this to avoid misinterpretation. > > Signed-off-by: Robert Hoo > --- > qemu-options.hx | 6 +++--- > 1 file changed, 3

[Bug 1859021] Re: qemu-system-aarch64 (tcg): cval + voff overflow not handled, causes qemu to hang

This is an automated cleanup. This bug report has been moved to QEMU's new bug tracker on gitlab.com and thus gets marked as 'expired' now. Please continue with the discussion here: https://gitlab.com/qemu-project/qemu/-/issues/60 ** Changed in: qemu Status: Confirmed => Expired **

Re: [PATCH v3 3/4] hw/arm: sabrelite: Connect the Ethernet PHY at address 6

On Fri, Apr 30, 2021 at 10:41 PM Guenter Roeck wrote: > > Hi, > > On Wed, Jan 06, 2021 at 02:35:03PM +0800, Bin Meng wrote: > > From: Bin Meng > > > > At present, when booting U-Boot on QEMU sabrelite, we see: > > > > Net: Board Net Initialization Failed > > No ethernet found. > > > >

[PATCH 2/2] target/ppc: Reduce the size of ppc_spr_t

We elide values when registering sprs, we might as well save space in the array as well. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68..b704261b49 100644

Re: [Trivial] docs: More precisely describe memory-backend-*::id's user

Ping for review ... Thanks. On Thu, 2021-04-22 at 16:42 +0800, Robert Hoo wrote: > 'id' of memory-backend-{file,ram} is not only for '-numa''s > reference, but > also other parameters like '-device nvdimm'. > More clearly call out this to avoid misinterpretation. > > Signed-off-by: Robert Hoo >

[PATCH 0/2] target/ppc: Clean up _spr_register

This is a fleshed out version of the pseudo-patch I posted in response to Bruno Larsen's "untangle CPU init" patch set, specifically to replace https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg06754.html Plus, ppc_spr_t can use some love to match. r~ PS, I generated this vs master, so

[PATCH 1/2] target/ppc: Clean up _spr_register et al

Introduce 3 helper macros to elide arguments that we cannot supply. This reduces the repetition required to get the job done. Signed-off-by: Richard Henderson --- target/ppc/translate_init.c.inc | 154 +++- 1 file changed, 74 insertions(+), 80 deletions(-) diff

Re: [PATCH] meson: Set implicit_include_directories to false

2021-04-30 16:48 Paolo Bonzini : > > On 29/04/21 04:43, Katsuhiro Ueno wrote: > > Without this, libvixl cannot be compiled with macOS 11.3 SDK due to > > include file name conflict (usr/include/c++/v1/version conflicts with > > VERSION). > > > > Signed-off-by: Katsuhiro Ueno > > --- > >

Re: [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic

On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote: +++ b/target/ppc/cpu_init.c @@ -18,6 +18,7 @@ * License along with this library; if not, see. */ +#include "qemu/osdep.h" #include "disas/dis-asm.h" #include "exec/gdbstub.h" #include "kvm_ppc.h"

Re: [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration

On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote: Since vscr is not an spr, its initialization was removed from the spr registration functions, and moved to the relevant init_procs. We may look into adding vscr to the reset path instead of the init path (as suggested by David Gibson), but

Re: [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static

On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote: +++ b/target/ppc/spr_tcg.c.inc @@ -17,6 +17,8 @@ * License along with this library; if not, see . */ +#include "spr_tcg.h" ... +++ b/target/ppc/translate_init.c.inc @@ -42,6 +42,7 @@ #include

Re: [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions

On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote: Removed functions gen_read_xer and gen_write_xer, moving their logic directly into spr_read_xer and spr_write_xer, respectively. Signed-off-by: Bruno Larsen (billionai) --- "Unnecessary" makes me believe that the code isn't used at all. A

Re: [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks

On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote: Moved all SPR read/write callback, and some related functions, to a new file specific for it. These callbacks are TCG only, so separating them is required to support the build flag disable-tcg. Making the spr_noaccess function not static, and

Re: [PATCH v3 27/30] target/ppc: Move D/DS/X-form integer loads to decodetree

On 4/30/21 4:54 PM, Matheus K. Ferst wrote: The only difference between those two is tcg_gen_addi_tl/tcg_gen_movi_tl and tcg_gen_add_tl/tcg_gen_mov_tl. We could do this in a single method if we tcg_const_tl(a->si) in do_ldst_D. I'm not sure about the costs involved, and we'd need to

Re: [PATCH v6 04/19] i386: stop using env->features[] for filling Hyper-V CPUIDs

On Thu, Apr 22, 2021 at 06:11:15PM +0200, Vitaly Kuznetsov wrote: > As a preparatory patch to dropping Hyper-V CPUID leaves from > feature_word_info[] stop using env->features[] as a temporary > storage of Hyper-V CPUIDs, just build Hyper-V CPUID leaves directly > from kvm_hyperv_properties[]

Re: [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro

On 4/30/21 12:35 PM, Bruno Larsen (billionai) wrote: moved RW callback parameters of _spr_register into an ifdef, to support building without TCG in the future, and added definitions for spr_register and spr_register_kvm, to keep the same call regardless of build options Signed-off-by: Bruno

Re: [PATCH v3 27/30] target/ppc: Move D/DS/X-form integer loads to decodetree

On 29/04/2021 22:15, Richard Henderson wrote: These are all connected by macros in the legacy decoding. Decode the D and DS forms into the PLS_D argument set so that prefixed insns can share code. Signed-off-by: Richard Henderson --- target/ppc/insn32.decode | 37 ++

Re: [RFC PATCH v2 2/2] hw/ppc: Moved TCG code to spapr_hcall_tcg

"Lucas Mateus Castro (alqotel)" writes: > Also spapr_hcall_tcg.c only has 2 duplicated functions (valid_ptex and > is_ram_address), what is the advised way to deal with these > duplications? valid_ptex is only needed by the TCG hcalls isn't it? is_ram_address could in theory stay where it is

Re: [PATCH v3 25/30] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI

On 30/04/2021 15:43, Richard Henderson wrote: On 4/30/21 11:02 AM, Matheus K. Ferst wrote: But in this case ADDI probably doesn't use PLS_D. You could use static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a) { arg_D d; if (!resolve_PLS_D(ctx, , a)) { return false; } return

Re: [PATCH v6 03/19] i386: always fill Hyper-V CPUID feature leaves from X86CPU data

On Thu, Apr 22, 2021 at 06:11:14PM +0200, Vitaly Kuznetsov wrote: > We have all the required data in X86CPU already and as we are about to > split hyperv_handle_properties() into hyperv_expand_features()/ > hyperv_fill_cpuids() we can remove the blind copy. The functional change > is that QEMU

Re: [PATCH v6 02/19] i386: invert hyperv_spinlock_attempts setting logic with hv_passthrough

On Thu, Apr 22, 2021 at 06:11:13PM +0200, Vitaly Kuznetsov wrote: > There is no need to have this special case: like all other Hyper-V > enlightenments we can just use kernel's supplied value in hv_passthrough > mode. Worth documenting this behaviour at docs/hyperv.txt? I was expecting all

Re: [PATCH v6 01/19] i386: keep hyperv_vendor string up-to-date

On Thu, Apr 22, 2021 at 06:11:12PM +0200, Vitaly Kuznetsov wrote: > When cpu->hyperv_vendor is not set manually we default to "Microsoft Hv" > and in 'hv_passthrough' mode we get the information from the host. This > information is stored in cpu->hyperv_vendor_id[] array but we don't update >

Re: [PATCH v4 4/6] migration-test: Make sure that multifd and cancel works

On Wed, 22 Jan 2020 at 11:20, Juan Quintela wrote: > > Test that this sequerce works: > > - launch source > - launch target > - start migration > - cancel migration > - relaunch target > - do migration again > > Signed-off-by: Juan Quintela > Reviewed-by: Dr. David Alan Gilbert > Signed-off-by:

Re: [PATCH v3] Set the correct env->fpip for x86 float instructions

Patchew URL: https://patchew.org/QEMU/20210430223701.176696-1-ziqiaok...@gmail.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210430223701.176696-1-ziqiaok...@gmail.com Subject: [PATCH v3] Set the correct

[PATCH v3] Set the correct env->fpip for x86 float instructions

Changes since v2: - Change the sequence of fpcs, fpds, fpip and fpdp in CPUX86State. - Use stl instead of stw in do_fstenv. - Move variables to floats instruction case block. - Move last accessed memory operand to a temp variable to avoid another load. - Move segment selectors instead of

Re: [PULL 30/39] block: bdrv_reopen_multiple: refresh permissions on updated graph

On Fri, 30 Apr 2021 at 11:53, Kevin Wolf wrote: > > From: Vladimir Sementsov-Ogievskiy > > Move bdrv_reopen_multiple to new paradigm of permission update: > first update graph relations, then do refresh the permissions. > > We have to modify reopen process in file-posix driver: with new scheme >

Re: [PULL 18/39] block: add bdrv_attach_child_common() transaction action

On Fri, 30 Apr 2021 at 11:53, Kevin Wolf wrote: > > From: Vladimir Sementsov-Ogievskiy > > Split out no-perm part of bdrv_root_attach_child() into separate > transaction action. bdrv_root_attach_child() now moves to new > permission update paradigm: first update graph relations then update >

Re: [PATCH 2/2] vhost-vdpa: doorbell mapping support

On 4/15/2021 1:04 AM, Jason Wang wrote: This patch implements the doorbell mapping support for vhost-vDPA. This is simply done by using mmap()/munmap() for the vhost-vDPA fd during device start/stop. For the device without doorbell support, we fall back to eventfd based notification

Re: [PULL 37/64] block/snapshot: Fix fallback

On Mon, 7 Sept 2020 at 12:11, Kevin Wolf wrote: > > From: Max Reitz > > If the top node's driver does not provide snapshot functionality and we > want to fall back to a node down the chain, we need to snapshot all > non-COW children. For simplicity's sake, just do not fall back if there > is

Re: [PATCH v3 25/30] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI

On 4/30/21 1:32 PM, Luis Fernando Fujita Pires wrote: From: Richard Henderson On 4/30/21 11:45 AM, Luis Fernando Fujita Pires wrote: I think we can already pass multiple files to decodetree.py and it will handle them correctly. I just didn't find a way to do that from the meson build files,

Re: [PATCH v2] target/i386: add "-cpu, lbr-fmt=*" support to enable guest LBR

On Fri, Apr 30, 2021 at 11:20:08AM +0800, Like Xu wrote: [...] > > > +if (cpu->lbr_fmt) { > > > +if (!cpu->enable_pmu) { > > > +error_setg(errp, "LBR is unsupported since guest PMU is > > > disabled."); > > > +return; > > > +} > > > +

[PATCH] hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset()

The omap_mmc_reset() function resets its SD card via device_legacy_reset(). We know that the SD card does not have a qbus of its own, so the new device_cold_reset() function (which resets both the device and its child buses) is equivalent here to device_legacy_reset() and we can just switch to

Re: [PULL 00/18] aspeed queue

On Fri, 30 Apr 2021 at 23:17, Peter Maydell wrote: > Same thing is also a build failure on 32-bit hosts (where the types > are genuinely different sizes): > > ../../hw/misc/aspeed_hace.c: In function 'do_hash_operation': > ../../hw/misc/aspeed_hace.c:128:49: error: passing argument 3 of >

Re: [PULL 00/18] aspeed queue

legoater/qemu/ tags/pull-aspeed-20210430 > > for you to fetch changes up to 1401dcd8aac9039797b995bfab078877a820c9c5: > > aspeed: Add support for the quanta-q7l1-bmc board (2021-04-30 10:30:42 > +0200) > > >

[PATCH] Add missing coroutine_fn function signature to functions

>From 447601c28d5ed0b1208a0560390f760e75ce5613 Mon Sep 17 00:00:00 2001 From: Cenne Dee Date: Fri, 30 Apr 2021 15:52:28 -0400 Subject: [PATCH] Add missing coroutine_fn function signature to functions Patch adds the signature for all relevant functions ending with _co or those that use them.

[PATCH v2 2/2] ui/cocoa: add option to swap Option and Command, enable by default

From: Gustavo Noronha Silva On Mac OS X the Option key maps to Alt and Command to Super/Meta. This change swaps them around so that Alt is the key closer to the space bar and Meta/Super is between Control and Alt, like on non-Mac keyboards. It is a cocoa display option, enabled by default.

[PATCH v2 0/2] cocoa: keyboard quality of life

From: Gustavo Noronha Silva v2 fixes QAPI issues pointed out by Markus and comes with his Acked-By. I tried also applying Gerd's suggestion of flipping the flags on modifiers, but turns out it is more intricate than that, as we then also need to flip the keyCode that is used on the switch, but

Re: [PATCH v3 04/15] qemu-iotests: add option to attach gdbserver

On 30/04/2021 13:38, Max Reitz wrote: On 14.04.21 19:03, Emanuele Giuseppe Esposito wrote: Add -gdb flag and GDB_QEMU environmental variable to python tests to attach a gdbserver to each qemu instance. Well, this patch doesn’t do this, but OK. Maybe "define" rather than "add"? In the

RE: [PATCH v3 05/30] target/ppc: Add cia field to DisasContext

> From: Richard Henderson > Signed-off-by: Richard Henderson > --- > target/ppc/translate.c | 34 ++ > 1 file changed, 18 insertions(+), 16 deletions(-) Reviewed-by: Luis Pires

[PATCH v6 82/82] target/arm: Enable SVE2 and related extensions

Signed-off-by: Richard Henderson --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 13 + 2 files changed, 14 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0dd623e590..30fd5d5ff7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1464,6 +1464,7 @@

[PATCH v6 81/82] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index fc9c4f12be..299116d450 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -648,8 +648,18 @@ static uint32_t

[PATCH v2 1/2] ui/cocoa: capture all keys and combos when mouse is grabbed

From: Gustavo Noronha Silva Applications such as Gnome may use Alt-Tab and Super-Tab for different purposes, some use Ctrl-arrows so we want to allow qemu to handle everything when it captures the mouse/keyboard. However, Mac OS handles some combos like Command-Tab and Ctrl-arrows at an earlier

RE: [PATCH v3 25/30] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI

From: Richard Henderson > On 4/30/21 11:45 AM, Luis Fernando Fujita Pires wrote: > > I think we can already pass multiple files to decodetree.py and it will > > handle > them correctly. I just didn't find a way to do that from the meson build > files, > which assume decodetree will always use a

Re: [PATCH v3 14/15] qemu_iotests: add option to show qemu binary logs on stdout

On 30/04/2021 15:50, Max Reitz wrote: On 14.04.21 19:03, Emanuele Giuseppe Esposito wrote: Using the flag -p, allow the qemu binary to print to stdout. This helps especially when doing print-debugging. I think this shouldn’t refer to prints but to qemu’s stdout/stderr in general, i.e

[PATCH v6 80/82] target/arm: Implement integer matrix multiply accumulate

This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE, and V{S,U,US}MMLA.S8 for AArch32 NEON. Signed-off-by: Richard Henderson --- target/arm/helper.h | 7 target/arm/neon-shared.decode | 7 target/arm/sve.decode | 6 +++ target/arm/translate-a64.c| 18

[PATCH v6 66/82] target/arm: Implement SVE2 FCVTLT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 23 +++

Re: [PATCH v3 10/15] qemu_iotests: extent QMP socket timeout when using valgrind

On 30/04/2021 15:02, Max Reitz wrote: On 14.04.21 19:03, Emanuele Giuseppe Esposito wrote: As with gdbserver, valgrind delays the test execution, so the default QMP socket timeout timeout too soon. I’m curious: The default timeouts should be long enough for slow systems, too, though (e.g.

[PATCH v6 79/82] target/arm: Implement aarch32 VSUDOT, VUSDOT

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/neon-shared.decode | 6 ++ target/arm/translate-neon.c | 27 +++ 3 files changed, 38 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index

[PATCH v6 72/82] target/arm: Implement SVE2 bitwise shift immediate

From: Stephen Long Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Signed-off-by: Stephen Long Message-Id: <20200430194159.24064-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 33 + target/arm/sve.decode | 5

Re: [PATCH v3 05/15] qemu-iotests: delay QMP socket timers

On 30/04/2021 13:59, Max Reitz wrote: On 14.04.21 19:03, Emanuele Giuseppe Esposito wrote: Attaching a gdbserver implies that the qmp socket should wait indefinitely for an answer from QEMU. Signed-off-by: Emanuele Giuseppe Esposito ---   python/qemu/machine.py    |  3 +++  

[PATCH v6 69/82] target/arm: Share table of sve load functions

The table used by do_ldrq is a subset of the table used by do_ld_zpa; we can share them by passing dtype instead of msz to do_ldrq. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 254 ++--- 1 file changed, 126 insertions(+), 128 deletions(-)

[PATCH v6 75/82] target/arm: Split out do_neon_ddda_fpst

Split out a helper that can handle the 4-register format for helpers shared with SVE. Signed-off-by: Richard Henderson --- target/arm/translate-neon.c | 98 - 1 file changed, 43 insertions(+), 55 deletions(-) diff --git a/target/arm/translate-neon.c

[PATCH v6 68/82] target/arm: Implement SVE2 FLOGB

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200430191405.21641-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fixed esz index and c++ comments v3: Fixed denormal arithmetic and raise invalid. --- target/arm/helper-sve.h| 4 +++ target/arm/sve.decode

[PATCH v6 78/82] target/arm: Split decode of VSDOT and VUDOT

Now that we have a common helper, sharing decode does not save much. Also, this will solve an upcoming naming problem. Signed-off-by: Richard Henderson --- target/arm/neon-shared.decode | 9 ++--- target/arm/translate-neon.c | 30 ++ 2 files changed, 28

[PATCH v6 70/82] target/arm: Implement SVE2 LD1RO

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 97 ++ 2 files changed, 101 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 17adb393ff..df870ce23b 100644 ---

[PATCH v6 54/82] target/arm: Implement SVE2 saturating multiply-add high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 + target/arm/sve.decode | 8 target/arm/sve_helper.c| 40 ++ target/arm/translate-sve.c | 8 4 files changed, 70 insertions(+) diff --git

[PATCH v6 63/82] target/arm: Implement SVE2 crypto constructive binary operations

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 3 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 384c92eebb..c75601b221 100644 ---

[PATCH v6 76/82] target/arm: Remove unused fpst from VDOT_scalar

Cut and paste error from another pattern. Signed-off-by: Richard Henderson --- target/arm/translate-neon.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 41a7b2208e..a0e267694b 100644 --- a/target/arm/translate-neon.c +++

RE: [PATCH v3 06/30] target/ppc: Split out decode_legacy

From: Richard Henderson > Signed-off-by: Richard Henderson > --- > target/ppc/translate.c | 115 +++-- > 1 file changed, 64 insertions(+), 51 deletions(-) Reviewed-by: Luis Pires

[PATCH v6 55/82] target/arm: Implement SVE2 saturating multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 9 + target/arm/sve.decode | 18 ++ target/arm/sve_helper.c| 30 ++ target/arm/translate-sve.c | 32 4 files changed, 81 insertions(+),

[PATCH v6 62/82] target/arm: Implement SVE2 crypto destructive binary operations

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 38 ++ 3 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index

[PATCH v6 64/82] target/arm: Implement SVE2 TBL, TBX

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428144352.9275-1-stepl...@quicinc.com> [rth: rearrange the macros a little and rebase] Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 10 + target/arm/sve.decode | 5 +++ target/arm/sve_helper.c|

[PATCH v6 56/82] target/arm: Implement SVE2 saturating multiply (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 12 target/arm/sve_helper.c| 20 target/arm/translate-sve.c | 19 +++ 4 files changed, 52 insertions(+), 4 deletions(-) diff --git

[PATCH v6 67/82] target/arm: Implement SVE2 FCVTXNT, FCVTX

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-4-stepl...@quicinc.com> [rth: Use do_frint_mode, which avoids a specific runtime helper.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 2 ++ target/arm/translate-sve.c | 49

[PATCH v6 71/82] target/arm: Implement 128-bit ZIP, UZP, TRN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 3 ++ target/arm/sve.decode | 8 ++ target/arm/sve_helper.c| 29 +-- target/arm/translate-sve.c | 58 ++ 4 files changed, 90 insertions(+), 8 deletions(-) diff

[PATCH v6 77/82] target/arm: Fix decode for VDOT (indexed)

We were extracting the M register twice, once incorrectly as M:vm and once correctly as rm. Remove the incorrect name and remove the incorrect decode. Signed-off-by: Richard Henderson --- target/arm/neon-shared.decode | 4 +- target/arm/translate-neon.c | 90

[PATCH v6 57/82] target/arm: Implement SVE2 signed saturating doubling multiply high

Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 + target/arm/sve.decode | 4 ++ target/arm/translate-sve.c | 18 target/arm/vec_helper.c| 84 ++ 4 files changed, 116 insertions(+) diff --git a/target/arm/helper.h

[PATCH v6 65/82] target/arm: Implement SVE2 FCVTNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200428174332.17162-2-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 5 + target/arm/sve.decode | 4 target/arm/sve_helper.c| 20

[PATCH v6 48/82] target/arm: Pass separate addend to {U, S}DOT helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- v4: Fix double addition (zhiwei). --- target/arm/helper.h | 20 +++--- target/arm/sve.decode

[PATCH v6 73/82] target/arm: Implement SVE2 fp multiply-add long

From: Stephen Long Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT Signed-off-by: Stephen Long Message-Id: <20200504171240.11220-1-stepl...@quicinc.com> [rth: Rearrange to use float16_to_float32_by_bits.] Signed-off-by: Richard Henderson --- target/arm/helper.h|

[PATCH v6 47/82] target/arm: Implement SVE2 SPLICE, EXT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200423180347.9403-1-stepl...@quicinc.com> [rth: Rename the trans_* functions to *_sve2.] Signed-off-by: Richard Henderson --- target/arm/sve.decode | 11 +-- target/arm/translate-sve.c | 35

[PATCH v6 61/82] target/arm: Implement SVE2 crypto unary operations

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 6 ++ target/arm/translate-sve.c | 11 +++ 2 files changed, 17 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 73f1348313..6ab13b2f78 100644 --- a/target/arm/sve.decode +++

[PATCH v6 45/82] target/arm: Implement SVE2 gather load insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus

[PATCH v6 74/82] target/arm: Implement aarch64 SUDOT, USDOT

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/translate-a64.c | 25 + 2 files changed, 30 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c75601b221..b2b684df55 100644 --- a/target/arm/cpu.h +++

[PATCH v6 53/82] target/arm: Implement SVE2 integer multiply-add (indexed)

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 8 target/arm/translate-sve.c | 23 +++ 2 files changed, 31 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 65cb0a2206..9bfaf737b7 100644 --- a/target/arm/sve.decode

[PATCH v6 51/82] target/arm: Split out formats for 3 vectors + 1 index

Used by FMLA and DOT, but will shortly be used more. Split FMLA from FMLS to avoid an extra sub field; similarly for SDOT from UDOT. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 29 +++-- target/arm/translate-sve.c | 38

[PATCH v6 58/82] target/arm: Implement SVE2 saturating multiply high (indexed)

Signed-off-by: Richard Henderson --- target/arm/helper.h| 14 ++ target/arm/sve.decode | 8 target/arm/translate-sve.c | 8 target/arm/vec_helper.c| 88 ++ 4 files changed, 118 insertions(+) diff --git a/target/arm/helper.h

[PATCH v6 41/82] target/arm: Implement SVE2 RSUBHNB, RSUBHNT

From: Stephen Long This completes the section 'SVE2 integer add/subtract narrow high part' Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-5-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix round bit type (laurent desnogues) --- target/arm/helper-sve.h| 8

[PATCH v6 50/82] target/arm: Split out formats for 2 vectors + 1 index

Currently only used by FMUL, but will shortly be used more. Signed-off-by: Richard Henderson --- target/arm/sve.decode | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 04ef38f148..a504b55dad 100644 ---

[PATCH v6 49/82] target/arm: Pass separate addend to FCMLA helpers

For SVE, we potentially have a 4th argument coming from the movprfx instruction. Currently we do not optimize movprfx, so the problem is not visible. Signed-off-by: Richard Henderson --- target/arm/helper.h | 20 +++ target/arm/translate-a64.c | 28 +

[PATCH v6 42/82] target/arm: Implement SVE2 HISTCNT, HISTSEG

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200416173109.8856-1-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix overlap between output and input vectors. v4: Fix histseg counting (zhiwei). --- target/arm/helper-sve.h| 7 ++ target/arm/sve.decode

[PATCH v6 46/82] target/arm: Implement SVE2 FMMLA

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200422165503.13511-1-stepl...@quicinc.com> [rth: Fix indexing in helpers, expand macro to straight functions.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ target/arm/helper-sve.h| 3 ++

[PATCH v6 37/82] target/arm: Implement SVE2 complex integer multiply-add

Signed-off-by: Richard Henderson --- v2: Fix do_sqrdmlah_d (laurent desnogues) --- target/arm/helper-sve.h| 18 target/arm/vec_internal.h | 5 + target/arm/sve.decode | 5 + target/arm/sve_helper.c| 42 ++

[PATCH v6 59/82] target/arm: Implement SVE mixed sign dot product (indexed)

Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.h| 4 +++ target/arm/sve.decode | 4 +++ target/arm/translate-sve.c | 16 + target/arm/vec_helper.c| 68 ++ 5 files changed, 97 insertions(+)

[PATCH v6 40/82] target/arm: Implement SVE2 SUBHNB, SUBHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-4-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c| 10 ++ target/arm/translate-sve.c |

[PATCH v6 38/82] target/arm: Implement SVE2 ADDHNB, ADDHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-2-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 5 + target/arm/sve_helper.c| 36

[PATCH v6 60/82] target/arm: Implement SVE mixed sign dot product

Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 ++ target/arm/sve.decode | 4 target/arm/translate-sve.c | 16 target/arm/vec_helper.c| 18 ++ 4 files changed, 40 insertions(+) diff --git a/target/arm/helper.h

[PATCH v6 44/82] target/arm: Implement SVE2 scatter store insns

From: Stephen Long Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal store insns. 64-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) * STNT1W (vector plus scalar) * STNT1D (vector plus scalar) 32-bit * STNT1B (vector plus scalar) * STNT1H (vector plus scalar) *

[PATCH v6 39/82] target/arm: Implement SVE2 RADDHNB, RADDHNT

From: Stephen Long Signed-off-by: Stephen Long Message-Id: <20200417162231.10374-3-stepl...@quicinc.com> Signed-off-by: Richard Henderson --- v2: Fix round bit type (laurent desnogues) --- target/arm/helper-sve.h| 8 target/arm/sve.decode | 2 ++ target/arm/sve_helper.c

[PATCH v6 52/82] target/arm: Implement SVE2 integer multiply (indexed)

Signed-off-by: Richard Henderson --- target/arm/sve.decode | 7 +++ target/arm/translate-sve.c | 30 ++ 2 files changed, 37 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 74ac72bdbd..65cb0a2206 100644 ---

[PATCH v6 34/82] target/arm: Implement SVE2 saturating multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 14 ++ target/arm/sve.decode | 14 ++ target/arm/sve_helper.c| 30 + target/arm/translate-sve.c | 54 ++ 4 files changed, 112 insertions(+) diff

[PATCH v6 43/82] target/arm: Implement SVE2 XAR

In addition, use the same vector generator interface for AdvSIMD. This fixes a bug in which the AdvSIMD insn failed to clear the high bits of the SVE register. Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 4 ++ target/arm/helper.h| 2 +

[PATCH v6 36/82] target/arm: Implement SVE2 integer multiply-add long

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 28 ++ target/arm/sve.decode | 11 ++ target/arm/sve_helper.c| 18 + target/arm/translate-sve.c | 76 ++ 4 files changed, 133 insertions(+) diff --git

[PATCH v6 27/82] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN

Signed-off-by: Richard Henderson --- target/arm/helper-sve.h| 16 +++ target/arm/sve.decode | 4 ++ target/arm/sve_helper.c| 35 ++ target/arm/translate-sve.c | 98 ++ 4 files changed, 153 insertions(+) diff --git

[PATCH v6 33/82] target/arm: Implement SVE2 MATCH, NMATCH

From: Stephen Long Reviewed-by: Richard Henderson Signed-off-by: Stephen Long Message-Id: <20200415145915.2859-1-stepl...@quicinc.com> [rth: Expanded comment for do_match2] Signed-off-by: Richard Henderson --- v2: Apply esz_mask to input pg to fix output flags. --- target/arm/helper-sve.h

[PATCH v6 35/82] target/arm: Implement SVE2 saturating multiply-add high

SVE2 has two additional sizes of the operation and unlike NEON, there is no saturation flag. Create new entry points for SVE2 that do not set QC. Signed-off-by: Richard Henderson --- target/arm/helper.h| 17 target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 18

[PATCH v6 30/82] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS

Rename the existing sve_while (less-than) helper to sve_whilel to make room for a new sve_whileg helper for greater-than. Signed-off-by: Richard Henderson --- v2: Use a new helper function to implement this. v4: Update for PREDDESC. --- target/arm/helper-sve.h| 3 +- target/arm/sve.decode

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