On 03/09/2021 19.45, Philippe Mathieu-Daudé wrote:
Per
https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
The old API took the size of the memory to duplicate as a guint,
whereas most memory functions take memory sizes as a gsize. This
made it easy to
On Fri, Sep 03, 2021 at 07:45:08PM +0200, Philippe Mathieu-Daudé wrote:
> Per
> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>
> The old API took the size of the memory to duplicate as a guint,
> whereas most memory functions take memory sizes as a
Daniel P. Berrangé writes:
> On Wed, Sep 01, 2021 at 04:14:10PM +0200, Markus Armbruster wrote:
>> Michael Roth writes:
>>
>> > Most of the current 'query-sev' command is relevant to both legacy
>> > SEV/SEV-ES guests and SEV-SNP guests, with 2 exceptions:
>> >
>> > - 'policy' is a 64-bit
On Wed, Sep 01, 2021 at 03:19:26PM +0200, Markus Armbruster wrote:
> Daniel Henrique Barboza writes:
>
> > At this moment we only provide one event to report a hotunplug error,
> > MEM_UNPLUG_ERROR. As of Linux kernel 5.12 and QEMU 6.0.0, the pseries
> > machine is now able to report unplug
On Fri, Sep 03, 2021 at 07:44:58PM +0200, Philippe Mathieu-Daudé wrote:
> Per
> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>
> The old API took the size of the memory to duplicate as a guint,
> whereas most memory functions take memory sizes as a
'
>> into staging (2021-09-03 08:27:38 +0100)
>>
>> are available in the Git repository at:
>>
>> https://github.com/legoater/qemu/ tags/pull-aspeed-20210903
>>
>> for you to fetch changes up to 907796622b2a6b945c87641d94e254ac898b96ae:
&g
[Expired for qemu (Ubuntu) because there has been no activity for 60
days.]
** Changed in: qemu (Ubuntu)
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1770417
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1770417
Title:
Qemu can
On Fri, Sep 03, 2021 at 01:07:00PM +0200, Philippe Mathieu-Daudé wrote:
> Per
> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>
> The old API took the size of the memory to duplicate as a guint,
> whereas most memory functions take memory sizes as a
On Fri, Sep 03, 2021 at 01:06:50PM +0200, Philippe Mathieu-Daudé wrote:
> Per
> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>
> The old API took the size of the memory to duplicate as a guint,
> whereas most memory functions take memory sizes as a
> On Sep 3, 2021, at 8:30 AM, Philippe Mathieu-Daudé wrote:
>
> On 9/3/21 10:20 AM, p...@fb.com wrote:
>> From: Peter Delevoryas
>>
>> This adds a new machine type "fuji-bmc" based on the following device tree:
>>
>>
On Sat, Sep 4, 2021 at 1:06 AM Richard Henderson
wrote:
>
> On 9/3/21 1:23 AM, Alistair Francis wrote:
> > +DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
>
> Dash not underscore for the prop name, I think.
>
But we also have "priv_spec" :)
The name "mtval_inst" sounds like
On Wed, 25 Aug 2021 15:56:20 +0800
"Longpeng(Mike)" wrote:
> In migration resume phase, all unmasked msix vectors need to be
> setup when load the VF state. However, the setup operation would
> takes longer if the VF has more unmasked vectors.
>
> In our case, the VF has 65 vectors and each one
On Wed, 25 Aug 2021 15:56:18 +0800
"Longpeng(Mike)" wrote:
> The vf's unmasked msix vectors will be enable one by one in
> migraiton resume phase, VFIO_DEVICE_SET_IRQS will be called
> for each vector, it's a bit expensive if the vf has more
> vectors.
>
> We can call VFIO_DEVICE_SET_IRQS once
On Wed, 25 Aug 2021 15:56:19 +0800
"Longpeng(Mike)" wrote:
> The kvm_irqchip_commit_routes() is relatively expensive, so
> provide the users a choice to commit the route immediately
> or not when they add msi/msix route.
>
> Signed-off-by: Longpeng(Mike)
> ---
> accel/kvm/kvm-all.c| 10
On Wed, 25 Aug 2021 15:56:17 +0800
"Longpeng(Mike)" wrote:
> 'msix_function_masked' is kept pace with the device's config,
s/pace/synchronized/?
> we can use it to replace the complex conditional in
> msix_set/unset_vector_notifiers.
>
> poll_notifier should be reset to NULL in the error path
On Wed, 25 Aug 2021 15:56:16 +0800
"Longpeng(Mike)" wrote:
> The main difference of the failure path in vfio_msi_enable and
> vfio_msi_disable_common is enable INTX or not.
>
> Extend the vfio_msi_disable_common to provide a arg to decide
"an arg"
> whether need to fallback, and then we can
On Fri, Sep 03, 2021 at 01:28:00PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> We are generally moving to int64_t for both offset and bytes parameters
> on all io paths.
...
> Still, the functions may be called directly, not only by drv->...
> Let's check:
>
> git grep
On Fri, Sep 03, 2021 at 01:27:59PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> We are generally moving to int64_t for both offset and bytes parameters
> on all io paths.
>
> Main motivation is realization of 64-bit write_zeroes operation for
> fast zeroing large disk chunks, up to the whole
On Fri, Sep 03, 2021 at 07:45:10PM +0200, Philippe Mathieu-Daudé wrote:
> g_memdup() is insecure and as been deprecated in GLib 2.68.
> QEMU provides the safely equivalent g_memdup2() wrapper.
>
> Do not allow more g_memdup() calls in the repository, provide
> a hint to use g_memdup2().
>
>
On 9/3/21 11:13 PM, Eric Blake wrote:
> On Fri, Sep 03, 2021 at 07:44:47PM +0200, Philippe Mathieu-Daudé wrote:
>> Per
>> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>>
>> The old API took the size of the memory to duplicate as a guint,
>> whereas most
On 8/31/21 6:39 PM, Luis Pires wrote:
+if (decNumberIsSpecial(dn) || (dn->exponent < 0) ||
+ (dn->digits + dn->exponent > 39)) {
+goto Invalid;
+} else {
No need for the goto and the else. Pick one. Probably the goto, since you need it anyway
for the other overflow
On 27/08/2021 1:26, Michael Roth wrote:
> From: Brijesh Singh
>
> SEV-SNP support relies on a different set of properties/state than the
> existing 'sev-guest' object. This patch introduces the 'sev-snp-guest'
> object, which can be used to configure an SEV-SNP guest. For example,
> a
On Fri, Sep 03, 2021 at 07:44:47PM +0200, Philippe Mathieu-Daudé wrote:
> Per
> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>
> The old API took the size of the memory to duplicate as a guint,
> whereas most memory functions take memory sizes as a
On 9/3/21 10:42 PM, Richard Henderson wrote:
> On 9/3/21 2:50 AM, David Gibson wrote:
>> On Thu, Sep 02, 2021 at 06:15:34PM +0200, Philippe Mathieu-Daudé wrote:
>>> Each POWER cpu has its own has_work() implementation. Instead of
>>> overloading CPUClass on each PowerPCCPUClass init, register the
On Fri, Sep 03, 2021 at 07:44:45PM +0200, Philippe Mathieu-Daudé wrote:
> Per
> https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
>
> The old API took the size of the memory to duplicate as a guint,
> whereas most memory functions take memory sizes as a
On 8/31/21 6:39 PM, Luis Pires wrote:
+*phigh = ahi + blo;
+
+return (bhi > 0) || (*phigh < ahi);
return add64_overflow(ahi, blo, phigh) || bhi != 0
With that,
Reviewed-by: Richard Henderson
r~
On 9/2/21 11:07 PM, Luis Fernando Fujita Pires wrote:
From: Richard Henderson
Hmm. I'll note that we have a better divmod primitive in tree, but we aren't
using it
here: udiv_qrnnd in include/fpu/softfloat-macros.h.
Good to know! I'll change to a (much simpler) implementation using
On Fri, Sep 03, 2021 at 05:38:20PM +0200, Philippe Mathieu-Daudé wrote:
> Since commits cc05c43ad94..42874d3a8c6 ("memory: Define API for
> MemoryRegionOps to take attrs and return status") the Memory API
> returns a zero (MEMTX_OK) response meaning success, anything else
> indicating a failure.
>
On 9/3/21 9:12 PM, Richard Henderson wrote:
> On 9/2/21 5:16 PM, Philippe Mathieu-Daudé wrote:
>> Restrict cpu_exec_interrupt() and its callees to sysemu.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> target/avr/cpu.h | 2 ++
>> target/avr/cpu.c | 2 +-
>> target/avr/helper.c | 2
On 9/3/21 8:19 PM, Philippe Mathieu-Daudé wrote:
cpu_common_has_work() is the default has_work() implementation
and returns 'false'.
Explicit it for the QTest / HAX / HVF / NVMM / Xen accelerators
and remove cpu_common_has_work().
Since there are no more implementations of
On 9/3/21 8:14 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Though I think the one existing reference to CONFIG_TCG for this target is a
mistake,
On 9/3/21 8:14 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
No CONFIG_TCG, otherwise,
Reviewed-by: Richard Henderson
r~
On 9/3/21 8:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/xtensa/cpu.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index
On 9/3/21 2:50 AM, David Gibson wrote:
On Thu, Sep 02, 2021 at 06:15:34PM +0200, Philippe Mathieu-Daudé wrote:
Each POWER cpu has its own has_work() implementation. Instead of
overloading CPUClass on each PowerPCCPUClass init, register the
generic ppc_cpu_has_work() handler, and have it call
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 25a4aa2976d..0d0cf6f9028 100644
---
On 9/3/21 7:55 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 9/3/21 10:34 PM, Philippe Mathieu-Daudé wrote:
Drop CONFIG_TCG for alpha; it's always true.
What is the rational? "Old" architectures (with no active /
official hw development) are unlikely to add hardware
acceleration, so TCG is the single one possible? Thus no
need to clutter the code
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On Fri, Sep 03, 2021 at 07:44:44PM +0200, Philippe Mathieu-Daudé wrote:
> When experimenting raising GLIB_VERSION_MIN_REQUIRED to 2.68
> (Fedora 34 provides GLib 2.68.1) we get:
>
> hw/virtio/virtio-crypto.c:245:24: error: 'g_memdup' is deprecated: Use
> 'g_memdup2' instead
On 9/3/21 10:47 PM, Philippe Mathieu-Daudé wrote:
On 9/3/21 9:12 PM, Richard Henderson wrote:
On 9/2/21 5:16 PM, Philippe Mathieu-Daudé wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/avr/cpu.h | 2 ++
target/avr/cpu.c
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
The common ppc_cpu_has_work() handler already checks for cs->halted,
so we can simplify all callees.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu_init.c | 294 --
1 file changed, 138
the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-aspeed-20210903
>
> for you to fetch changes up to 907796622b2a6b945c87641d94e254ac898b96ae:
>
> hw/arm/aspeed: Add Fuji machine type (2021-09-03 18:43:16 +0200)
>
> ---
This patch starts the counter negative EBB support by enabling PMC1
counter negative overflow when PMC1 is counting cycles.
A counter negative overflow happens when a performance monitor counter
reaches the value 0x8000. When that happens, if counter negative
condition events are enabled in
All performance monitor counters can trigger a counter negative
condition if the proper MMCR0 bits are set. This patch does that
for all PMCs that can count cycles by doing the following:
- pmc_counter_negative_enabled() will check whether a given PMC is
eligible to trigger the counter negative
On 9/3/21 8:13 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 2047742d03c..6c47d28631c 100644
On 9/3/21 9:41 PM, Cédric Le Goater wrote:
> From: Peter Delevoryas
>
> This adds a new machine type "fuji-bmc" based on the following device tree:
>
> https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts
>
> Most of the i2c devices are not there,
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/openrisc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time
We're missing two counter freeze bits that are used to further control
how the PMCs behaves: MMCR0_FC14 and MMCR0_FC56. These bits can frozen
PMCs separately: MMCR0_FC14 freezes PMCs 1 to 4 and MMCR0_FC56 freezes
PMCs 5 and 6.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu.h|
On 9/3/21 2:50 AM, David Gibson wrote:
> On Thu, Sep 02, 2021 at 06:15:34PM +0200, Philippe Mathieu-Daudé wrote:
>> Each POWER cpu has its own has_work() implementation. Instead of
>> overloading CPUClass on each PowerPCCPUClass init, register the
>> generic ppc_cpu_has_work() handler, and have it
On 9/3/21 10:18 PM, Richard Henderson wrote:
> On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
>> Restrict has_work() to TCG sysemu.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> target/alpha/cpu.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git
The current logic is only considering event-based exceptions triggered
by the performance monitor. This is true now, but we might want to add
support for external event-based exceptions in the future.
Let's make it a bit easier to do so by adding the bit logic that would
happen in case we were
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions
(Perf event PM_INST_CMPL) by counting the amount of instructions
translated
Hi Michael,
On 27/08/2021 1:26, Michael Roth wrote:
> From: Brijesh Singh
>
> Sync the kvm.h with the kernel to include the SNP specific commands.
>
> Signed-off-by: Brijesh Singh
> Signed-off-by: Michael Roth
> ---
> linux-headers/linux/kvm.h | 50 +++
>
From: Gustavo Romero
Following up the rfebb implementation, this patch adds the EBB exception
support that are triggered by Performance Monitor alerts. This exception
occurs when an enabled PMU condition or event happens and both MMCR0_EBE
and BESCR_PME are set.
The supported PM alerts will
Up until this moment we were assuming that the counter negative
enabled bits, PMC1CE and PMCjCE, would never be changed when the
PMU is already started.
Turns out that there is no such restriction in the PowerISA v3.1,
and software can enable/disable overflow conditions of the counters
at any
This patch enable all PMCs but PMC5 to count cycles. To do that we
need to implement MMCR1 bits where the event are stored, retrieve
them, see if the PMC was configured with a PM_CYC event, and
calculate cycles if that's the case.
PowerISA v3.1 defines the following conditions to count cycles:
-
The initial PMU support were made under the assumption that the counters
would be set before running the PMU and read after either freezing the
PMU manually or via a performance monitor alert.
Turns out that some EBB powerpc kernel tests set the counters after
unfreezing the counters. Setting a
Enabling counter negative overflow for the PMCs that are counting
instructions is simpler than when counting cycles. Instruction
counting is done via helper_insns_inc(), which is called every
time a TB ends.
Firing a performance monitor alert due to a counter negative overflow
in this case is a
This patch adds the barebones of the PMU logic by enabling cycle
counting, done via the performance monitor counter 6. The overall logic
goes as follows:
- a helper is added to control the PMU state on each MMCR0 write. This
allows for the PMU to start/stop as the frozen counter bit (MMCR0_FC)
is
The PMU needs to enable writing of its uregs to userspace, otherwise
Perf applications will not able to setup the counters correctly. This
patch enables user space writing of all PMU uregs.
MMCR0 is a special case because its userspace writing access is controlled
by MMCR0_PMCC bits. There are 4
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The
Hi,
This version contains changes suggested by David and Matheus. No big
design changes were made.
Changes from v2:
- former patch 1: merged into patch 2 (former 3)
- patches 1 and 2 (former 2 and 3):
* no more intermediate write reg functions that will replaced shortly after
* do not name
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1e..f1f976bdad7
From: Gustavo Romero
We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+
emulation and following PowerISA v3.1.
Let's start by handling the user read of UMMCR0 and UMMCR2. According to
PowerISA 3.1 these registers omit some of its bits from userspace.
CC: Gustavo Romero
Hi Michael,
On 27/08/2021 1:26, Michael Roth wrote:
> From: Brijesh Singh
>
> During the SNP guest launch sequence, a special secrets and cpuid page
> needs to be populated by the SEV-SNP firmware.
Just to be clear: these are two distinct pages. I suggest rephrasing to
"... a special secrets
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
has_work() is sysemu specific, and Hexagon target only provides
a linux-user implementation. Remove the unused hexagon_cpu_has_work().
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletions(-)
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.c | 6 --
target/i386/tcg/tcg-cpu.c | 8 +++-
2 files changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static bool cris_cpu_has_work(CPUState *cs)
No CONFIG_TCG for cris. Otherwise,
Reviewed-by: Richard Henderson
r~
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 66d22d11895..94b35cb4a50 100644
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 93e16a2ffb4..32cf5a2ea9f
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/avr/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index e9fa54c9777..6267cc6d530 100644
---
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e8edd189bfc..cf1f656218f 100644
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
cpu_has_work() is only called from system emulation code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Implement WHPX has_work() handler in AccelOpsClass and
remove it from cpu_thread_is_idle() since cpu_has_work()
is already called.
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/cpus.c| 4 +---
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Add TCG target-specific has_work() handler in TCGCPUOps,
and add tcg_cpu_has_work() as AccelOpsClass has_work()
implementation.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 4
accel/tcg/tcg-accel-ops.c |
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Implement KVM has_work() handler in AccelOpsClass and
remove it from cpu_thread_is_idle() since cpu_has_work()
is already called.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-accel-ops.c | 6 ++
softmmu/cpus.c| 2 +-
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
Introduce an accelerator-specific has_work() handler.
Eventually call it from cpu_has_work().
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/accel-ops.h | 5 +
softmmu/cpus.c | 3 +++
2 files changed, 8 insertions(+)
On 9/2/21 6:15 PM, Philippe Mathieu-Daudé wrote:
We want to make cpu_has_work() per-accelerator. Only declare its
prototype and move its definition to softmmu/cpus.c.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 8 +---
softmmu/cpus.c| 8
2 files
From: Andrew Jeffery
While some of the critical fields remain the same, there is variation in
the definition of the control register across the SoC generations.
Reserved regions are adjusted, while in other cases the mutability or
behaviour of fields change.
Introduce a callback to sanitize the
From: Andrew Jeffery
The logic in the handling for the control register required toggling the
enable state for writes to stick. Rework the condition chain to allow
sequential writes that do not update the enable state.
Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by:
From: Guenter Roeck
According to its dts file in the Linux kernel, we need mac0 and mac1 enabled
instead of mac1 and mac2. Also, g220a is based on aspeed-g5 (ast2500) which
doesn't even have the third interface.
Signed-off-by: Guenter Roeck
Reviewed-by: Cédric Le Goater
Message-Id:
From: Guenter Roeck
Commit 7582591ae7 ("aspeed: Support AST2600A1 silicon revision") switched
the silicon revision for AST2600 to revision A1. On revision A1, the first
Ethernet interface is operational. Enable it.
Signed-off-by: Guenter Roeck
Reviewed-by: Joel Stanley
Reviewed-by: Cédric Le
From: Peter Delevoryas
When you run QEMU with an Aspeed machine and a single serial device
using stdio like this:
qemu -machine ast2600-evb -drive ... -serial stdio
The guest OS can read and write to the UART5 registers at 0x1E784000 and
it will receive from stdin and write to stdout. The
On 03.09.21 21:20, Peter Xu wrote:
On Fri, Sep 03, 2021 at 09:58:06AM +0200, David Hildenbrand wrote:
That'll be good enough for live snapshot as uffd-wp works for zero pages,
however I'm just afraid it may stop working for some new users of it when zero
pages won't suffice.
I thought about
On 03.09.21 21:40, David Hildenbrand wrote:
On 03.09.21 21:20, Peter Xu wrote:
On Fri, Sep 03, 2021 at 09:58:06AM +0200, David Hildenbrand wrote:
That'll be good enough for live snapshot as uffd-wp works for zero pages,
however I'm just afraid it may stop working for some new users of it when
From: Joel Stanley
This contains some hardcoded register values that were obtained from the
hardware after reading the temperature.
It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
operation modes other than the default as used by Linux are not modelled.
Signed-off-by:
Generated documentation uses operators "and", "or", and "!". Change
the latter to "not".
Signed-off-by: Markus Armbruster
Message-Id: <20210831123809.1107782-9-arm...@redhat.com>
Reviewed-by: Marc-André Lureau
---
scripts/qapi/common.py | 2 +-
tests/qapi-schema/doc-good.txt | 2 +-
2
From: Joel Stanley
This is the latest revision of the ASPEED 2600 SoC. As there is no
need to model multiple revisions of the same SoC for the moment,
update the SCU AST2600 to model the A3 revision instead of the A1 and
adapt the AST2600 SoC and machines.
Reset values are taken from v8 of the
From: Joel Stanley
These are the devices documented by the Rainier device tree. With this
we can see the guest discovering the multiplexers and probing the eeprom
devices:
i2c i2c-2: Added multiplexed i2c bus 16
i2c i2c-2: Added multiplexed i2c bus 17
i2c i2c-2: Added multiplexed i2c bus 18
From: Andrew Jeffery
There was a bit of a thinko in the state calculation where every odd pin
in was reported in e.g. "pwm0" mode rather than "off". This was the
result of an incorrect bit shift for the 2-bit field representing each
LED state.
Fixes: a90d8f84674d ("misc/pca9552: Add qom set and
From: Joel Stanley
Witherspoon uses the DPS310 as a temperature sensor. Rainier uses it as
a temperature and humidity sensor.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Message-Id: <20210629142336.750058-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 4
The C code generated for 'if' conditionals is incorrectly
parenthesized. For instance,
'if': { 'not': { 'any': [ { 'not': 'TEST_IF_EVT' },
{ 'not': 'TEST_IF_STRUCT' } ] } } }
generates
#if !(!defined(TEST_IF_EVT)) || (!defined(TEST_IF_STRUCT))
This is
From: Joel Stanley
There are two GPIO controllers in the ast2600; one is 3.3V and the other
is 1.8V.
Signed-off-by: Joel Stanley
Reviewed-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
Message-Id: <20210713065854.134634-4-j...@jms.id.au>
Signed-off-by: Cédric Le Goater
---
When commit 5d83b9a130 "qapi: replace if condition list with dict
{'all': [...]}" made cgen_ifcond() and docgen_ifcond() recursive, it
messed up parenthesises in the former, and got them right in the
latter, as the previous commit demonstrates.
To fix, adopt the latter's working code for the
1 - 100 of 478 matches
Mail list logo
