On 9/20/21 8:56 PM, Paolo Bonzini wrote:
On Mon, Nov 16, 2020 at 7:31 PM Hannes Reinecke wrote:
The current code sets an infinite timeout on SG_IO requests,
causing the guest to stall if the host experiences a frame
loss.
This patch adds an 'io_timeout' parameter for SCSIDevice to
make the
Hi Daniel,
On 9/14/21 7:20 AM, Daniel P. Berrangé wrote:
> This is a counterpart to the HMP "info lapic" command. It is being
> added with an "x-" prefix because this QMP command is intended as an
> adhoc debugging tool and will thus not be modelled in QAPI as fully
> structured data, nor will it
Hi,
> But, in anyway, I'll still need to store the target architecture that
> can use such core module, like I did here in this patch. Otherwise,
> if I compile different targets at the same time, I'll end up with the
> same problem of targets trying to load wrong modules.
That all works just
On 9/17/21 16:31, Markus Armbruster wrote:
> Commit b359f4b203 "tests: Rename UserDefNativeListUnion to
> UserDefListUnion" renamed test_clone_native_list() to
> test_clone_list_union(). The function has nothing to do with unions.
> Rename it to test_clone_list().
>
> Signed-off-by: Markus
On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
> The reset value of IPIDR should be zero for Freescale chipset, per
> the following 2 manuals I checked:
>
> - P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
> - P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
On Mon, Sep 20, 2021 at 09:42:25AM +0200, Cédric Le Goater wrote:
> On 9/20/21 09:34, David Gibson wrote:
> > On Mon, Sep 20, 2021 at 08:12:02AM +0200, Cédric Le Goater wrote:
> > > Signed-off-by: Cédric Le Goater
> >
> > So.. all the functions here are called *set_irq*, but you've named the
> >
On Mon, Sep 20, 2021 at 02:49:40PM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> This version has a changed asked by Greg in patch 4, along with
> Greg's R-bs.
>
> Changes from v8:
> - added Greg's reviewed-by in patches 3, 5, 6 and 7
> - patch 4:
> * changed get_associativity() to return a
On Mon, Sep 20, 2021 at 02:49:46PM -0300, Daniel Henrique Barboza wrote:
> The main feature of FORM2 affinity support is the separation of NUMA
> distances from ibm,associativity information. This allows for a more
> flexible and straightforward NUMA distance assignment without relying on
>
On Mon, Sep 20, 2021 at 02:49:47PM -0300, Daniel Henrique Barboza wrote:
> numa_complete_configuration() in hw/core/numa.c always adds a NUMA node
> for the pSeries machine if none was specified, but without node distance
> information for the single node created.
>
> NUMA FORM1 affinity code
On Mon, Sep 20, 2021 at 08:12:03AM +0200, Cédric Le Goater wrote:
> The current way the mask is built can overflow with a 64-bit decrementer.
> Use sextract64() to extract the signed values and remove the logic to
> handle negative values which has become useless.
>
> Cc: Luis Fernando Fujita
While we may have had some thought of allowing system-mode
to return from this hook, we have no guests that require this.
Reviewed-by: Alistair Francis
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/tcg-cpu-ops.h | 3 ++-
Let the compiler decide about inlining.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg-target.c.inc | 45 +++---
1 file changed, 22 insertions(+), 23 deletions(-)
diff --git a/tcg/sparc/tcg-target.c.inc
Only use indirect jumps. Finish weaning away from the
unique alignment requirements for code_gen_buffer.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.h | 12 +---
tcg/mips/tcg-target.c.inc | 23 +--
2 files
This version of tcg_out_mov is emits a nop to fill the
delay slot if the move is not required.
The only current use, for INDEX_op_goto_ptr, will always
require the move but properly documents the delay slot.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Weaning off of unique alignment requirements, so allow JAL
to not reach the target. TCG_TMP1 is always available for
use as a scratch because it is clobbered by the subroutine
being called.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 6
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index c16f96b401..dc8d8f1de2
There is nothing target specific about this. The implementation
is host specific, but the declaration is 100% common.
Reviewed-By: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 13 +
://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210920
for you to fetch changes up to b21ba5dfe3f4a367910d490d10fa7c9fa76f1504:
tcg/riscv: Remove add with zero on user-only memory access (2021-09-20
14:17:54 -0700)
Move
From: Philippe Mathieu-Daudé
Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following
comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn():
case EXCP_HALTED:
/* during start-up the vCPU is reset and the thread is
* kicked several times. If we don't
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/region.c | 91
1 file changed, 91 deletions(-)
diff --git a/tcg/region.c b/tcg/region.c
index e64c3ea230..9cc30d4922 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@
Let the compiler decide about inlining.
Remove tcg_out_ext8s and tcg_out_ext16s as unused.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 76 ++-
1 file changed, 27 insertions(+), 49 deletions(-)
diff
From: Frank Chang
When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect.
Modifying the floating-point state when V=1 causes both fields to
be set to 3 (Dirty).
However, it's possible that HS-level sstatus.FS is Clean and VS-level
vsstatus.FS is Dirty at the time mark_fs_dirty() is
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 218 +++
target/hexagon/helper.h | 1 +
target/hexagon/op_helper.c | 5 +
3 files changed, 224 insertions(+)
Acked-by: Richard
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Add new file to target/hexagon/meson.build
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/decode_ext_mmvec.h | 24
target/hexagon/decode.c | 24 +++-
target/hexagon/mmvec/decode_ext_mmvec.c | 236
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Imported from the Hexagon architecture library
imported/allext.idef Top level file for all extensions
imported/mmvec/ext.idefHVX instruction definitions
Support functions added to target/hexagon/genptr.c
Acked-by: Richard
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 150 +++
1 file changed, 150 insertions(+)
Acked-by: Richard Henderson
r~
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 26 ++
1 file changed, 26 insertions(+)
Reviewed-by: Richard Henderson
r~
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 103 +++
1 file changed, 103 insertions(+)
Reviewed-by: Richard Henderson
r~
On 9/20/21 2:24 PM, Taylor Simpson wrote:
+#define fGEN_TCG_V6_pred_xor(SHORTCODE) \
+tcg_gen_gvec_xor(MO_64, QdV_off, QsV_off, QtV_off, \
+ sizeof(MMQReg), sizeof(MMQReg))
+
+#define fGEN_TCG_V6_pred_or_n(SHORTCODE) \
+do { \
+intptr_t tmpoff =
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 34 ++
1 file changed, 34 insertions(+)
Reviewed-by: Richard Henderson
r~
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 122 +++
1 file changed, 122 insertions(+)
Reviewed-by: Richard Henderson
r~
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 31 +++
1 file changed, 31 insertions(+)
Reviewed-by: Richard Henderson
r~
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 50
1 file changed, 50 insertions(+)
Reviewed-by: Richard Henderson
r~
Hi guys,
Ping...
I just sent out V3, please review on V3, thanks!
在 2021/9/9 14:06, Longpeng(Mike) 写道:
> Hi guys,
>
> In vfio migration resume phase, the cost would increase if the
> vfio device has more unmasked vectors. We try to optimize it in
> this series.
>
> You can see the commit
In migration resume phase, all unmasked msix vectors need to be
setup when load the VF state. However, the setup operation would
take longer if the VM has more VFs and each VF has more unmasked
vectors.
The hot spot is kvm_irqchip_commit_routes, it'll scan and update
all irqfds that already
'defer_kvm_irq_routing' indicates whether we should defer to commit
the kvm routing.
Signed-off-by: Longpeng(Mike)
---
hw/vfio/pci.c | 43 ++-
hw/vfio/pci.h | 1 +
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/hw/vfio/pci.c
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_helper_funcs.py | 112 ++--
target/hexagon/gen_helper_protos.py | 16 ++-
target/hexagon/gen_tcg_funcs.py | 258 ++--
3 files changed, 364
'msix_function_masked' is synchronized with the device's config,
we can use it to replace the complex conditional statementis in
msix_set/unset_vector_notifiers.
Signed-off-by: Longpeng(Mike)
---
hw/pci/msix.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
Move re-enabling INTX out, and the callers should decide to
re-enable it or not.
Signed-off-by: Longpeng(Mike)
---
hw/vfio/pci.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index f7a3a13fb0..1e6797fd4b 100644
---
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_dectree_import.c | 13 +
1 file changed, 13 insertions(+)
Acked-by: Richard Henderson
r~
It's unnecessary to test against the specific return value of
VFIO_DEVICE_SET_IRQS, since any positive return is an error
indicating the number of vectors we should retry with.
Signed-off-by: Longpeng(Mike)
---
hw/vfio/pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi guys,
In vfio migration resume phase, the cost would increase if the
vfio device has more unmasked vectors. We try to optimize it in
this series.
You can see the commit message in PATCH 9 for details.
Patch 1-5 are simple cleanups and fixup.
Patch 6-8 are the preparations for the
Commit ecebe53fe993 ("vfio: Avoid disabling and enabling vectors
repeatedly in VFIO migration") avoid inefficiently disabling and
enabling vectors repeatedly and let the unmasked vectors to be
enabled one by one.
But we want to batch multiple routes and defer the commit, and only
commit once out
'msix_vector_poll_notifier' should be reset to NULL in the error
path in msix_set_vector_notifiers().
Signed-off-by: Longpeng(Mike)
---
hw/pci/msix.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 67682289af..805770942b 100644
--- a/hw/pci/msix.c
+++
Extract a common helper that add MSI route for specific vector
but does not commit immediately.
Signed-off-by: Longpeng(Mike)
---
accel/kvm/kvm-all.c | 15 +--
include/sysemu/kvm.h | 6 ++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/accel/kvm/kvm-all.c
Use vfio_msi_disable_common to simplify the error handling
in vfio_msi_enable.
Signed-off-by: Longpeng(Mike)
---
hw/vfio/pci.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 1e6797fd4b..8e97ca93cf 100644
---
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Add HVX support to the semantics generator
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_semantics.c | 33 +
target/hexagon/hex_common.py | 13 +
2 files changed, 46 insertions(+)
Acked-by:
On 9/20/21 2:24 PM, Taylor Simpson wrote:
Imported from the Hexagon architecture library
imported/allext_macros.def Top level macro include for all extensions
imported/macros.def Scalar core macros (some HVX here)
imported/mmvec/macros.defHVX macro
On 9/20/21 2:24 PM, Taylor Simpson wrote:
macros to interface with the generator
macros referenced in instruction semantics
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 22 +++
target/hexagon/mmvec/macros.h | 341 ++
2 files
On 9/20/21 2:23 PM, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/attribs_def.h.inc | 22 ++
1 file changed, 22 insertions(+)
Acked-by: Richard Henderson
r~
On 9/20/21 2:23 PM, Taylor Simpson wrote:
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Signed-off-by:
On Fri, Sep 17, 2021 at 04:31:33PM +0200, Markus Armbruster wrote:
> Signed-off-by: Markus Armbruster
> ---
> 65 files changed, 48 insertions(+), 48 deletions(-)
The diff is harder to read in email (due to file rename comparison
sometimes going astray on short and similar file contents) when
cpu_common_has_work() is the default has_work() implementation
and returns 'false'.
Explicit it for the QTest / HAX / HVF / NVMM / Xen accelerators
and remove cpu_common_has_work().
Since there are no more implementations of SysemuCPUOps::has_work,
remove it along with the assertion in
Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
> The declaration ROM is located at the top-most address of the standard slot
> space.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/nubus/nubus-device.c | 44 +++-
> include/hw/nubus/nubus.h | 6 ++
>
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index b95682b7f04..419fa624bd5 100644
---
> -Original Message-
> From: Philippe Mathieu-Daudé On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Monday, September 20, 2021 4:59 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: a...@rev.ng; Brian Cain ;
> richard.hender...@linaro.org
> Subject: Re: [PATCH v3 15/30] Hexagon HVX
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/rx/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 25a4aa2976d..ac6b40b2716 100644
--- a/target/rx/cpu.c
+++
On 9/20/21 23:24, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/gen_tcg_hvx.h | 31 +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
> index eb29566..bcd53d4 100644
>
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/openrisc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 27cb04152f9..3c368a1bde7 100644
---
On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote:
-g_assert(cc->has_work);
-return cc->has_work(cpu);
+if (cc->has_work) {
+return cc->has_work(cpu);
+}
+if (cpus_accel->has_work) {
+return cpus_accel->has_work(cpu);
+}
+g_assert_not_reached();
This
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 00e0c55d0e4..3639c03f8ea 100644
---
On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 66d22d11895..ad5d26b5c9e 100644
--- a/target/m68k/cpu.c
On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote:
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 7 +--
target/arm/cpu_tcg.c | 2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index e83e305aa9d..4a63ed12644 100644
---
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/xtensa/cpu.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index c1cbd03595e..5cb19a88819 100644
---
On 9/20/21 2:44 PM, Philippe Mathieu-Daudé wrote:
+static bool tcg_cpu_has_work(CPUState *cpu)
+{
+CPUClass *cc = CPU_GET_CLASS(cpu);
+
+g_assert(cc->tcg_ops->has_work);
+return cc->tcg_ops->has_work(cpu);
+}
Now, you're expecting cc->has_work to disappear as cc->tcg_ops->has_work
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/sh4/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 2047742d03c..fb2116dc52e 100644
--- a/target/sh4/cpu.c
+++
Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work()
- SysemuCPUOps::has_work() implementation - to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/cpu-qom.h | 4 +++-
target/ppc/cpu_init.c | 24 ++--
2 files changed,
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 93e16a2ffb4..1ca601cac5b 100644
---
The SPARC target only support TCG acceleration. Remove the CONFIG_TCG
definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops:
move to tcg-cpu-ops.h, keep a pointer in CPUClass").
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is
a const structure, so to avoid creating multiple versions of
the same structure, simply changing the has_work() handler,
introduce yet another indirection with a has_work() handler in
PowerPCCPUClass, and ppc_cpu_has_work() method
Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
> Since there is no need to generate a dummy declaration ROM, remove both
> nubus_register_rom() and nubus_register_format_block(). These will shortly be
> replaced with a mechanism to optionally load a declaration ROM from disk to
> allow real
Implement KVM has_work() handler in AccelOpsClass and
remove it from cpu_thread_is_idle() since cpu_has_work()
is already called.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
accel/kvm/kvm-accel-ops.c | 6 ++
softmmu/cpus.c| 2 +-
2 files changed, 7
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7b7b05f1d3a..df8ade9021d 100644
---
We want to make cpu_has_work() per-accelerator. Only declare its
prototype and move its definition to softmmu/cpus.c.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 8 +---
softmmu/cpus.c| 8
2 files changed, 9
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e8edd189bfc..be940ae2246 100644
--- a/target/hppa/cpu.c
Introduce an accelerator-specific has_work() handler.
Eventually call it from cpu_has_work().
Signed-off-by: Philippe Mathieu-Daudé
---
include/sysemu/accel-ops.h | 5 +
softmmu/cpus.c | 9 +++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git
cpu_has_work() is only called from system emulation code.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/include/hw/core/cpu.h
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/avr/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5d70e34dd54..6d51f91ca2c 100644
--- a/target/avr/cpu.c
+++
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13575c14085..abb555a8bdb 100644
---
Implement SysemuCPUOps::has_work() handler for the ARM v7M CPU.
See the comments added in commit 7ecdaa4a963 ("armv7m: Fix
condition check for taking exceptions") which eventually
forgot to implement this has_work() handler:
* ARMv7-M interrupt masking works differently than -A or -R.
*
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/nios2/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1e..9938d7c2919 100644
---
Le 20/09/2021 à 22:01, Laurent Vivier a écrit :
> Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
>> The macfb device is an on-board framebuffer and so is initialised by the
>> system declaration ROM included within the MacOS toolbox ROM.
>>
>> Signed-off-by: Mark Cave-Ayland
>> ---
>>
Restrict has_work() to TCG sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 7 +--
target/arm/cpu_tcg.c | 2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ba0741b20e4..e11aa625a5f 100644
---
On Mon, Sep 20, 2021 at 12:56:40PM +0200, Stefan Reiter wrote:
> Adds support for the "-xS" parameter type, where "-x" denotes a flag
> name and the "S" suffix indicates that this flag is supposed to take an
> arbitrary string parameter.
>
> These parameters are always optional, the entry in the
Restrict has_work() to sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/microblaze/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 15db277925f..36e6e540483 100644
Missing review:
- 0001-target-arm-Implement-arm_v7m_cpu_has_work.patch
- 0005-sysemu-Introduce-AccelOpsClass-has_work.patch
- 0008-accel-tcg-Implement-AccelOpsClass-has_work-as-stub.patch
- 0010-target-arm-Restrict-has_work-handler-to-sysemu-and-T.patch
-
Add TCG target-specific has_work() handler in TCGCPUOps,
and add tcg_cpu_has_work() as AccelOpsClass has_work()
implementation.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 4
accel/tcg/tcg-accel-ops.c | 10 ++
2 files changed, 14 insertions(+)
Restrict has_work() to TCG sysemu.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.c | 6 --
target/i386/tcg/tcg-cpu.c | 8 +++-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
Add new file to target/hexagon/meson.build
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/decode_ext_mmvec.h | 24
target/hexagon/decode.c | 24 +++-
target/hexagon/mmvec/decode_ext_mmvec.c | 236
target/hexagon/meson.build
Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
> Each Nubus slot has an IRQ line that can be used to request service from the
> CPU. Connect the IRQs to the Nubus bridge so that they can be wired up using
> qdev
> gpios accordingly, and introduce a new nubus_set_irq() function that can be
>
Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
> Nubus IRQs are routed to the CPU through the VIA2 device so wire up the IRQs
> using gpios accordingly.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/hw/m68k/q800.c
has_work() is sysemu specific, and Hexagon target only provides
a linux-user implementation. Remove the unused hexagon_cpu_has_work().
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 52
1 file changed, 52 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 006ba74..bd0abc6 100644
--- a/target/hexagon/gen_tcg_hvx.h
+++
On Mon, Sep 20, 2021 at 12:56:41PM +0200, Stefan Reiter wrote:
> It is possible to specify more than one VNC server on the command line,
> either with an explicit ID or the auto-generated ones à la "default",
> "vnc2", "vnc3", ...
>
> It is not possible to change the password on one of these
Le 17/09/2021 à 09:50, Mark Cave-Ayland a écrit :
> Slot 0x9 is reserved for use by the in-built framebuffer whilst only slots
> 0xc, 0xd and 0xe physically exist on the Quadra 800.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c | 9 +
> 1 file changed, 9 insertions(+)
>
>
Restrict has_work() to sysemu.
Signed-off-by: Philippe Mathieu-Daudé
---
target/cris/cpu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index c2e7483f5bd..b2761f8b110 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index eb29566..bcd53d4 100644
--- a/target/hexagon/gen_tcg_hvx.h
+++
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_histogram_input.h | 717
tests/tcg/hexagon/hvx_histogram_row.h | 24 ++
tests/tcg/hexagon/hvx_histogram.c | 88
tests/tcg/hexagon/Makefile.target | 5 +
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