On Sat, Oct 30, 2021 at 11:57 PM Bin Meng wrote:
>
> Add a config option to enable support for native M-mode debug.
> This is disabled by default and can be enabled with 'debug=true'.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
> Changes in v2:
> - change the
On Mon, Nov 1, 2021 at 5:57 PM Anup Patel wrote:
>
> On Mon, Nov 1, 2021 at 12:26 PM Alistair Francis wrote:
> >
> > On Tue, Oct 26, 2021 at 5:01 PM Anup Patel wrote:
> > >
> > > The RISC-V AIA specification extends RISC-V local interrupts and
> > > introduces new CSRs. This patch adds defines
On Tue, Oct 26, 2021 at 6:41 AM Atish Patra wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will
On Tue, Oct 26, 2021 at 6:05 AM Atish Patra wrote:
>
> As per the privilege specification v1.11, mcountinhibit allows to start/stop
> a pmu counter selectively.
>
> Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 2 ++
>
On Tue, Oct 26, 2021 at 6:03 AM Atish Patra wrote:
>
> The PMU counters are supported via cpu config "Counters" which doesn't
> indicate the correct purpose of those counters.
>
> Rename the config property to pmu to indicate that these counters
> are performance monitoring counters. This aligns
On Tue, Oct 26, 2021 at 5:56 AM Atish Patra wrote:
>
> Currently, the predicate function for PMU related CSRs only works if
> virtualization is enabled. It also does not check mcounteren bits before
> before cycle/minstret/hpmcounterx access.
>
> Support supervisor mode access in the predicate
On Tue, Oct 26, 2021 at 6:39 AM Atish Patra wrote:
>
> The predicate function calculates the counter index incorrectly for
> hpmcounterx. Fix the counter index to reflect correct CSR number.
>
> Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c |
On Tue, Nov 02, 2021 at 05:41:10PM -0700, Dongwon Kim wrote:
> I double-checked the patch and also tried to build with --disable-opengl
> but couldn't find any issue. Can you please give me some hint? Like
> build errors you saw. What are changed by the patch are pretty much
> limited to
On Tue, Nov 2, 2021 at 4:22 PM Bin Meng wrote:
>
> On Tue, Nov 2, 2021 at 6:24 PM Anup Patel wrote:
> >
> > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng wrote:
> > >
> > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote:
> > > >
> > > > A hypervsior can optionally take guest external interrupts
Hi Simon
Le mer. 3 nov. 2021 à 02:30, Simon Glass a écrit :
> Hi Tom,
>
> On Tue, 2 Nov 2021 at 11:28, Tom Rini wrote:
> >
> > On Tue, Nov 02, 2021 at 09:00:53AM -0600, Simon Glass wrote:
> > > Hi Tom,
> > >
> > > On Mon, 1 Nov 2021 at 12:07, Tom Rini wrote:
> > > >
> > > > On Mon, Nov 01,
Hi Simon
Le mer. 3 nov. 2021 à 02:21, Simon Glass a écrit :
> Hi François,
>
> On Wed, 27 Oct 2021 at 14:07, François Ozog
> wrote:
> >
> > Hi Simon
> >
> > Le mer. 27 oct. 2021 à 20:23, Simon Glass a écrit :
> >>
> >> Hi François,
> >>
> >> On Wed, 27 Oct 2021 at 09:14, François Ozog
>
On 11/2/21 10:22 AM, Hanna Reitz wrote:
The following changes since commit 8cb41fda78c7ebde0dd248c6afe1d336efb0de50:
Merge remote-tracking branch 'remotes/philmd/tags/machine-20211101' into
staging (2021-11-02 05:53:45 -0400)
are available in the Git repository at:
We will reuse this section of arm_deliver_fault for
raising pc alignment faults.
Signed-off-by: Richard Henderson
---
target/arm/tlb_helper.c | 45 +
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/target/arm/tlb_helper.c
Both single-step and pc alignment faults have priority over
breakpoint exceptions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/debug_helper.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/arm/debug_helper.c
For A64, any input to an indirect branch can cause this.
For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not. This includes the BX instruction but also
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index cec672f229..9c4258ccac 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/pcalign-a64.c | 37 +
tests/tcg/arm/pcalign-a32.c | 46 +++
tests/tcg/aarch64/Makefile.target | 4 +--
tests/tcg/arm/Makefile.target | 4 +++
4
The size of the code covered by a TranslationBlock cannot be 0;
this is checked via assert in tb_gen_code.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ead77e9006..a39456ea98 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@
Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.
Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Create arm_check_ss_active and arm_check_kernelpage.
Reverse the order of the tests. While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d6af5b1b03..ead77e9006 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9559,17
Raise pc alignment faults.
Fix single-step and pc-align priority over breakpoints.
Not yet fixing insn abort priority over breakpoints.
r~
Changes for v4:
* Rebase on master.
* Split some cleanups into new patches.
* No special cases in helper_exception_pc_alignment.
Changes for v3:
*
On 11/2/21 6:52 PM, Warner Losh wrote:
Signed-off-by: Warner Losh
---
bsd-user/x86_64/target_arch_signal.h | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
Reviewed-by: Richard Henderson
r~
On 11/2/21 6:52 PM, Warner Losh wrote:
Signed-off-by: Warner Losh
---
bsd-user/i386/target_arch_signal.h | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
Reviewed-by: Richard Henderson
r~
On 11/2/21 6:52 PM, Warner Losh wrote:
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.
Signed-off-by: Warner Losh
---
bsd-user/i386/target_arch_signal.h | 4
1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 11/2/21 6:52 PM, Warner Losh wrote:
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.
Signed-off-by: Warner Losh
---
bsd-user/x86_64/target_arch_signal.h | 4
1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 11/2/21 6:52 PM, Warner Losh wrote:
CC: Paolo Bonzini
Signed-off-by: Warner Losh
Acked-by: Kyle Evans
Reviewed-by: Richard Henderson
---
configs/targets/arm-bsd-user.mak | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 configs/targets/arm-bsd-user.mak
diff --git
On 11/2/21 6:52 PM, Warner Losh wrote:
Update ucontext to implement sigreturn.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 9 +
1 file changed, 9 insertions(+)
Reviewed-by: Richard Henderson
r~
On 11/2/21 6:52 PM, Warner Losh wrote:
+env->regs[15] = tswap32(gr[TARGET_REG_PC]);
This will be able to crash qemu with an odd pc in thumb mode.
You'd have to artificially create this mcontext of course.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 11/2/21 6:52 PM, Warner Losh wrote:
+/*
+ * Low bit indicates whether or not we're entering thumb mode.
+ */
+cpsr = cpsr_read(env);
+if (ka->_sa_handler & 1) {
+cpsr |= CPSR_T;
+} else {
+cpsr &= ~CPSR_T;
+}
+cpsr_write(env, cpsr, CPSR_T,
On 11/2/21 6:52 PM, Warner Losh wrote:
Arm specific user context structures for signal handling and the closely
related trap frame.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 8
1 file changed, 8 insertions(+)
Reviewed-by: Richard
On 11/2/21 6:52 PM, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 20
1 file changed, 20 insertions(+)
Reviewed-by: Richard Henderson
r~
On 11/2/21 6:52 PM, Warner Losh wrote:
FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is
On 11/2/21 6:52 PM, Warner Losh wrote:
+/*
+ * Thumb mode is encoded by the low bit in the entry point (since ARM can't
+ * execute at odd addresses). When it's set, set the Thumb bit (T) in the
+ * CPSR.
+ */
+if (entry & 0x1) {
+cpsr_write(env, cpsr_read(env) |
On Tue, Nov 2, 2021 at 4:10 PM Eugenio Perez Martin wrote:
>
> On Tue, Nov 2, 2021 at 6:26 AM Jason Wang wrote:
> >
> > On Sat, Oct 30, 2021 at 2:44 AM Eugenio Pérez wrote:
> > >
> > > This allows it to test if the guest has aknowledge an invalid transport
> > > feature for SVQ. This will
On 11/2/21 6:52 PM, Warner Losh wrote:
+case EXCP_UDEF:
+{
+/* See arm/arm/undefined.c undefinedinstruction(); */
+info.si_addr = env->regs[15];
+
+/*
+ * Make sure the PC is correctly aligned. (It should
+
On Tue, Nov 2, 2021 at 4:29 PM Eugenio Perez Martin wrote:
>
> On Tue, Nov 2, 2021 at 7:35 AM Jason Wang wrote:
> >
> >
> > 在 2021/10/30 上午2:35, Eugenio Pérez 写道:
> > > This iova tree function allows it to look for a hole in allocated
> > > regions and return a totally new translation for a
On 11/2/21 6:52 PM, Warner Losh wrote:
target_arch_cpu.h is for CPU loop definitions. Create the file and
define target_cpu_init and target_cpu_reset for arm.
Signed-off-by: Olivier Houchard
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
---
On Tue, Nov 2, 2021 at 7:41 PM Eugenio Pérez wrote:
>
> The -1 assumes that all devices with no cvq have an spare vq allocated
> for them, but with no offer of VIRTIO_NET_F_CTRL_VQ. This is an invalid
> device by the standard, so just stick to the right number of device
> models.
>
> This is not
From: "Rao, Lei"
Remove some unnecessary code to improve the performance of
the filter-rewriter module.
Signed-off-by: Lei Rao
Reviewed-by: Zhang Chen
Reviewed-by: Juan Quintela
---
net/colo-compare.c| 2 +-
net/colo.c| 31 ---
net/colo.h
On Tue, Nov 2, 2021 at 11:52 PM Stefano Garzarella wrote:
>
> Use g_autofree to ensure that `config` is freed when
> vhost_vdpa_get_max_queue_pairs() returns.
>
> Reported-by: Coverity (CID 1465228: RESOURCE_LEAK)
> Fixes: 402378407d ("vhost-vdpa: multiqueue support")
> Signed-off-by: Stefano
1、install re2c。[url：http://re2c.org/index.html]
tar -xvzf re2c-1.0.3.tar.gz
cd re2c-1.0.3/
autoreconf -i -W all
./configure
make& install
2、git clone git://github.com/ninja-build/ninja.git && cd ninja
./configure.py --bootstrap
cp ninja /usr/bin/
[root@aix7 ~]# ninja
Will be changed and sent separately.
Thanks,
Lei
-Original Message-
From: Juan Quintela
Sent: Wednesday, November 3, 2021 12:23 AM
To: Rao, Lei
Cc: Zhang, Chen ; lizhij...@cn.fujitsu.com;
jasow...@redhat.com; zhang.zhanghaili...@huawei.com; lukasstra...@web.de;
dgilb...@redhat.com;
Hi Tom,
On Tue, 2 Nov 2021 at 10:57, Tom Rini wrote:
>
> On Tue, Nov 02, 2021 at 08:59:45AM -0600, Simon Glass wrote:
> > Hi François,
> >
> > On Mon, 1 Nov 2021 at 11:33, François Ozog wrote:
> > >
> > > Hi Simon
> > >
> > > Le lun. 1 nov. 2021 à 17:58, Simon Glass a écrit :
> > >>
> > >> Hi
Hi Tom,
On Tue, 2 Nov 2021 at 11:28, Tom Rini wrote:
>
> On Tue, Nov 02, 2021 at 09:00:53AM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Mon, 1 Nov 2021 at 12:07, Tom Rini wrote:
> > >
> > > On Mon, Nov 01, 2021 at 06:33:35PM +0100, François Ozog wrote:
> > > > Hi Simon
> > > >
> > > > Le
On 11/2/21 9:06 PM, liweiwei wrote:
在 2021/11/3 上午1:56, Richard Henderson 写道:
On 11/1/21 11:11 PM, liweiwei wrote:
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+
Hi François,
On Wed, 27 Oct 2021 at 14:07, François Ozog wrote:
>
> Hi Simon
>
> Le mer. 27 oct. 2021 à 20:23, Simon Glass a écrit :
>>
>> Hi François,
>>
>> On Wed, 27 Oct 2021 at 09:14, François Ozog wrote:
>> >
>> >
>> >
>> > On Wed, 27 Oct 2021 at 16:08, Simon Glass wrote:
>> >>
>> >> Hi
Hi Mark,
On Wed, 27 Oct 2021 at 16:30, Mark Kettenis wrote:
>
> > From: Simon Glass
> > Date: Wed, 27 Oct 2021 12:23:21 -0600
> >
> > Hi François,
> >
> > On Wed, 27 Oct 2021 at 09:14, François Ozog
> > wrote:
> > >
> > >
> > >
> > > On Wed, 27 Oct 2021 at 16:08, Simon Glass wrote:
> > >>
>
On Wed, 3 Nov 2021, Laurent Vivier wrote:
The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e:
Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into
staging (2021-10-30 11:31:41 -0700)
are available in the Git repository at:
在 2021/11/3 上午2:56, Richard Henderson 写道:
On 11/1/21 11:11 PM, liweiwei wrote:
+uint8_t AES_ENC_SBOX[] = {
+ 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
+ 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
+ 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
+ 0xAD, 0xD4, 0xA2, 0xAF, 0x9C,
在 2021/11/3 上午1:56, Richard Henderson 写道:
On 11/1/21 11:11 PM, liweiwei wrote:
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zknd = true;
+
On 11/1/21 7:44 PM, Michael S. Tsirkin wrote:
The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e:
Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into
staging (2021-10-30 11:31:41 -0700)
are available in the Git repository at:
Thanks for your suggestions.
在 2021/11/2 下午11:44, Richard Henderson 写道:
On 11/1/21 11:11 PM, liweiwei wrote:
Signed-off-by: liweiwei
Signed-off-by: wangjunqiang
You managed to get the whole patch description into the subject line.
Please break it up.
OK.
+target_ulong
I double-checked the patch and also tried to build with --disable-opengl
but couldn't find any issue. Can you please give me some hint? Like
build errors you saw. What are changed by the patch are pretty much
limited to virtio-gpu blob case and just one change in common area is
egl_fb_blit
On Mon, Nov 01, 2021 at 04:08:31PM +0100, BALATON Zoltan wrote:
> Suggested-by: Peter Maydell
> Signed-off-by: BALATON Zoltan
Applied to ppc-for-6.2, thanks.
> ---
> hw/ppc/pegasos2.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/pegasos2.c
On Tue, Nov 02, 2021 at 05:29:05PM +0100, Cédric Le Goater wrote:
> Test is wrong and the backend can never updated. It could have led to
> a QEMU crash but since the firmware deactivates flash access if a valid
> layout is not detected, it went unnoticed.
>
> Reported-by: Coverity CID 1465223
>
On Tue, Nov 2, 2021 at 5:35 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 11/2/21 7:27 PM, Warner Losh wrote:
> > This breaks bsd-user building. That’s OK, imho, for two reasons: First
> it only runs ‘hello world’. Second, I’ve updated my patch train which will
> fix this
On Tue, Nov 2, 2021 at 5:37 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 11/2/21 6:52 PM, Warner Losh wrote:
> > Until the signal support is merged from the bsd-user fork, we need stubs
> > for cpu_loop_exit_sigsegv and cpu_loop_exit_sigbus to link. These call
> > abort after
On 11/2/21 6:52 PM, Warner Losh wrote:
Until the signal support is merged from the bsd-user fork, we need stubs
for cpu_loop_exit_sigsegv and cpu_loop_exit_sigbus to link. These call
abort after logging a message. Since singals aren't supported here
yet, this is sufficient.
Signed-off-by:
On 11/2/21 7:27 PM, Warner Losh wrote:
This breaks bsd-user building. That’s OK, imho, for two reasons: First it only
runs ‘hello world’. Second, I’ve updated my patch train which will fix this
(message-id 20211019164447.16359-1-...@bsdimp.com).
If there’s urgency to this, I can pull patch 1
If guest fb is backed by dmabuf (blob-resource), the texture bound to the
old context needs to be recreated in case the egl is re-initialized (e.g.
new window for vc is created in case of detaching/reattaching of the tab)
v2: call egl_dmabuf_release_texutre instead of putting 0 to dmabuf->texture
ing (2021-10-29 19:42:36 -0700)
>> are available in the Git repository at:
>> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211102
>> for you to fetch changes up to 742f07628c0a0bd847b47ee0a0b20c44531e0ba5:
>> linux-user: Handle BUS_ADRALN
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.
Signed-off-by: Warner Losh
---
bsd-user/i386/target_arch_signal.h | 4
1 file changed, 4 deletions(-)
diff --git a/bsd-user/i386/target_arch_signal.h
b/bsd-user/i386/target_arch_signal.h
at:
https://github.com/philmd/qemu.git tags/mips-20211102
for you to fetch changes up to 6f08c9c5316a80a049d4861eaac5844466ba3eba:
Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"
(2021-11-02 14:3
From: Yanan Wang
The expected output string from cpu_slot_to_string() ought to be
like "socket-id: *, die-id: *, core-id: *, thread-id: *", so add
the missing ", " before "die-id". This affects the readability
of the error message.
Fixes: 176d2cda0d ("i386/cpu: Consolidate die-id validity in
CC: Paolo Bonzini
Signed-off-by: Warner Losh
Acked-by: Kyle Evans
Reviewed-by: Richard Henderson
---
configs/targets/arm-bsd-user.mak | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 configs/targets/arm-bsd-user.mak
diff --git a/configs/targets/arm-bsd-user.mak
From: Philippe Mathieu-Daudé
Hardware emulated models don't belong to the TCG MAINTAINERS
section. Move them to the 'HP-PARISC Machines' section.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Helge Deller
Message-Id:
Move the machine context to the CPU state.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 75 +++
1 file changed, 75 insertions(+)
diff --git a/bsd-user/arm/target_arch_signal.h
From: Philippe Mathieu-Daudé
Artist is another device, this one is the Lasi PS/2.
Rename the functions accordingly.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Message-Id: <20210920064048.2729397-2-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/input/lasips2.c | 8
The following changes since commit af531756d25541a1b3b3d9a14e72e7fedd941a2e:
Merge remote-tracking branch 'remotes/philmd/tags/renesas-20211030' into
staging (2021-10-30 11:31:41 -0700)
are available in the Git repository at:
git://github.com/vivier/qemu.git
From: Markus Armbruster
I noticed -cpu help printing enough trailing spaces to make the output
at least 84 characters wide. Looks ugly unless the terminal is wider.
Ugly or not, trailing spaces are stupid.
The culprit is this line in x86_cpu_list_entry():
qemu_printf("x86 %-20s %-58s\n",
An old esurface should be destroyed and set to be NULL when doing
un-tab and re-tab so that a new esurface an context can be created
for the window widget that those will be bound to.
v2: enabling opengl specific routines only when CONFIG_OPENGL is set
Cc: Gerd Hoffmann
Signed-off-by: Dongwon
gd_draw_event shouldn't try to repaint if surface does not exist
for the VC.
Cc: Gerd Hoffmann
Signed-off-by: Dongwon Kim
---
ui/gtk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/ui/gtk.c b/ui/gtk.c
index 8da673c18c..d2892ea6b4 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -778,6 +778,9
Implement set_sigtramp_args to setup the arguments to the sigtramp
calls.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 47 +++
1 file changed, 47 insertions(+)
diff --git a/bsd-user/arm/target_arch_signal.h
FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is defined. This is largely
copied from
Signed-off-by: Warner Losh
---
bsd-user/x86_64/target_arch_signal.h | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/bsd-user/x86_64/target_arch_signal.h
b/bsd-user/x86_64/target_arch_signal.h
index 55f742b0a8..e84aff948c 100644
---
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.
Signed-off-by: Warner Losh
---
bsd-user/x86_64/target_arch_signal.h | 4
1 file changed, 4 deletions(-)
diff --git a/bsd-user/x86_64/target_arch_signal.h
Signed-off-by: Warner Losh
---
bsd-user/i386/target_arch_signal.h | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/bsd-user/i386/target_arch_signal.h
b/bsd-user/i386/target_arch_signal.h
index e262667bda..bf7263c4f8 100644
--- a/bsd-user/i386/target_arch_signal.h
+++
Update ucontext to implement sigreturn.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/bsd-user/arm/target_arch_signal.h
b/bsd-user/arm/target_arch_signal.h
index 3b2f56ffab..3db76c9201
Implement the register copying routines to extract registers from the
cpu for core dump generation.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_reg.h | 60 ++
1 file
Arm specific user context structures for signal handling and the closely
related trap frame.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 8
1 file changed, 8 insertions(+)
diff --git a/bsd-user/arm/target_arch_signal.h
Get the machine context from the CPU state.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_signal.h | 50 +++
1 file changed, 50 insertions(+)
Implement the system call dispatch. This implements all three kinds of
system call: direct and the two indirect variants. It handles all the
special cases for thumb as well.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by:
Defines for registers and stack layout related to signals.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_signal.h | 57 +++
1 file changed, 57 insertions(+)
create mode
Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data
exceptions cause a SIGSEGV.
Signed-off-by: Kyle Evans
Signed-off-by: Olivier Houchard
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_signal.h | 20
1 file changed, 20 insertions(+)
diff --git a/bsd-user/arm/target_arch_signal.h
b/bsd-user/arm/target_arch_signal.h
index 973183d99c..3aaced474b
Implement get_elf_hwcap to get the first word of hardware capabilities.
Signed-off-by: Kyle Evans
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_elf.h | 72 +-
1 file
Basic set of defines needed for arm ELF file activation.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_elf.h | 36 ++
1 file changed, 36 insertions(+)
create mode
Making the vc->gfx.ectx current before handling texture
associated with it
Cc: Gerd Hoffmann
Signed-off-by: Dongwon Kim
---
ui/gtk-egl.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/ui/gtk-egl.c b/ui/gtk-egl.c
index 72ce5e1f8f..7c9629d6cc 100644
--- a/ui/gtk-egl.c
+++
Implement EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and
EXCP_YIELD. The first two generate a signal to the emulated
binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy
nops.
Signed-off-by: Stacey Son
Signed-off-by: Mikaël Urankar
Signed-off-by: Kyle Evans
Various parameters describing the layout of the ARM address space. In
addition, define routines to get the stack pointer and to set the second
return value.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
Implement target_thread_init (to create a thread) and target_set_upcall
(to switch to a thread) for arm.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
---
bsd-user/arm/target_arch_thread.h | 80 +++
1 file
Add a boiler plate CPU loop that does nothing except return an error for
all traps.
Signed-off-by: Sean Bruno
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_cpu.h | 22 ++
1 file
Implement the extended HW capabilities for HWCAP2.
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_elf.h | 22 ++
1 file changed, 22 insertions(+)
diff --git
Implement target_cpu_clone_regs to clone the resister state on a fork.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_cpu.h | 8
1 file changed, 8 insertions(+)
diff --git
target_arch_cpu.h is for CPU loop definitions. Create the file and
define target_cpu_init and target_cpu_reset for arm.
Signed-off-by: Olivier Houchard
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
---
bsd-user/arm/target_arch_cpu.h | 43
The preferred name for the 32-bit arm is now armv7. Update the name to
reflect that. In addition, add Stacey's copyright to this file and
update the include guards to the new convention.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
Copy of the signal trampoline code for arm, as well as setup_sigtramp to
write it to the stack.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_sigtramp.h | 49 +
1 file
Target specific TLS routines to get and set the TLS values.
Signed-off-by: Kyle Evans
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch.h | 28
bsd-user/arm/target_arch_cpu.c
1 - 100 of 540 matches
Mail list logo
