On 5/9/22 19:54, maobibo wrote:
how about put address_space_iocsr as board rather than percpu since there is no
concept
of "cpu package".
"cpu package" works ok as a device on the board.
I don't know if it's possible to have the iocsr address space controlled by the device,
especially since
Hi Zhangfei,
On 2022/5/9 22:24, Zhangfei Gao wrote:
Hi, Alex
On 2022/4/27 上午12:35, Alex Williamson wrote:
On Tue, 26 Apr 2022 12:43:35 +
Shameerali Kolothum Thodi wrote:
-Original Message-
From: Eric Auger [mailto:eric.au...@redhat.com]
Sent: 26 April 2022 12:45
To: Shameerali
在 2022/5/10 10:54, maobibo 写道:
>
>
> 在 2022/5/10 02:25, Richard Henderson 写道:
>> On 5/9/22 13:04, Peter Maydell wrote:
>>> On Mon, 9 May 2022 at 18:56, Richard Henderson
>>> wrote:
I'm not 100% sure how this "Other configuration control register" should
be handled, but
在 2022/5/10 02:25, Richard Henderson 写道:
> On 5/9/22 13:04, Peter Maydell wrote:
>> On Mon, 9 May 2022 at 18:56, Richard Henderson
>> wrote:
>>> I'm not 100% sure how this "Other configuration control register" should be
>>> handled, but
>>> definitely not like this.
>>>
>>> I see you're
Ping
https://patchew.org/QEMU/20220321055618.4026-1-lu@verisilicon.com/
Please help review the patch.
Thanks.
B.R.
-邮件原件-
发件人: Gao, Lu
发送时间: Monday, April 25, 2022 9:35 AM
收件人: Gao, Lu; qemu-devel@nongnu.org
抄送: Wen, Jianxian; Philippe Mathieu-Daudé; Bin Meng; open list:SD (Secure
> -Original Message-
> From: Greg Kurz
> Sent: 2022年5月10日 0:20
> To: Shi, Guohuai
> Cc: Bin Meng ; Christian Schoenebeck
> ;
> qemu-devel@nongnu.org; Meng, Bin
> Subject: Re: [PATCH 5/9] hw/9pfs: Add a 'local' file system backend driver for
> Windows
>
> [Please note: This e-mail is
This feature adds a new register, HCRX_EL2, which controls
many of the newer AArch64 features. So far the register is
effectively RES0, because none of the new features are done.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 20 ++
target/arm/cpu64.c | 1 +
Add HCRX_EL2 with no supported bits, and bit definitions for CPACR*.
Just trying to keep the queue smaller.
r~
Richard Henderson (2):
target/arm: Enable FEAT_HCX for -cpu max
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
target/arm/cpu.h| 64 ---
We had a few CPTR_* bits defined, but missed quite a few.
Complete all of the fields up to ARMv9.2.
Use FIELD_EX64 instead of manual extract32.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 44 +++-
hw/arm/boot.c | 2 +-
target/arm/cpu.c|
On Mon, May 09, 2022, Michael Roth wrote:
> On Fri, Apr 22, 2022 at 06:56:12PM +0800, Chao Peng wrote:
> > Requirements & Gaps
> > -
> > - Confidential computing(CC): TDX/SEV/CCA
> > * Need support both explicit/implicit conversions.
> > * Need support
On 5/9/22 15:57, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/syscall.c| 49 +
linux-user/uname.c | 2 +-
linux-user/user-internals.h | 2 +-
3 files changed, 25
On 5/9/22 15:57, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 202 ++--
linux-user/strace.h | 4 +-
linux-user/syscall.c| 32 +++---
linux-user/uname.c
On 5/9/22 15:57, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
fill_thread_info() takes a pointer to const.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 5/9/22 07:48, Víctor Colombo wrote:
This patch fixes another not-so-clear situation in Power ISA
regarding the inexact bits in FPSCR. The ISA states that:
"""
When Overflow Exception is disabled (OE=0) and an
Overflow Exception occurs, the following actions are
taken:
...
2. Inexact
Hi, Peter.
> Shuuichirou, Itaru: do either of you know the right setting for the A64FX for
> this? If
> you can find what the hardware value of the ICC_CTLR_EL3 or ICC_CTLR_EL1
> register is (more specifically, the PRIBits subfield) that should be enough
> to tell
> us.
The value of the
On Fri, Apr 22, 2022 at 06:56:12PM +0800, Chao Peng wrote:
> Great thanks for the discussions. I summarized the requirements/gaps and the
> potential changes for next step. Please help to review.
Hi Chao,
Thanks for writing this up. I've been meaning to respond, but wanted to
make a bit more
On 5/9/22 18:17, Mark Cave-Ayland wrote:
On 07/05/2022 20:06, Daniel Henrique Barboza wrote:
Hi,
Since the 7.0.0 release cycle we have a desire to use the powernv
emulation with libvirt. To do that we need to enable user creatable
pnv-phb devices to allow more user customization an to
On 5/9/22 07:48, Víctor Colombo wrote:
-static inline void float_inexact_excp(CPUPPCState *env)
+static inline void float_inexact_excp(CPUPPCState *env, bool set_fi)
{
CPUState *cs = env_cpu(env);
-env->fpscr |= FP_FI;
+if (set_fi) {
+env->fpscr |= FP_FI;
+}
On 9/5/22 23:14, Taylor Simpson wrote:
The store width is needed for packet commit, so it is stored in
ctx->store_width. Currently, it is set when a store has a TCG
override instead of a QEMU helper. In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet
Daniel,
I found a way to make the monitor arguments in array type (['uint32']).
And I know how to retrieve monitor values from it but I could not find
how to pass the monitor values when starting qemu. Like,
qemu-system-x86_64 . gtk,gl=on.monitor=
I tried several different things
On 9/5/22 23:14, Taylor Simpson wrote:
Remove encodings guarded by ifdef that is not defined
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/encode_pp.def | 23 ---
1 file changed, 23 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h
This series implements Sstc extension[1] which was ratified recently.
The first patch is a prepartory patches while PATCH 2 adds stimecmp
support while PATCH 3 adds vstimecmp support. This series is based on
on top of upstream commit (faee5441a038).
The series can also be found at
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 7 +++
Historically, The mtimer/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.
Move them to the ACLINT device. This also emulates the real hardware
more closely.
Signed-off-by: Atish Patra
---
On 5/9/22 10:54, Peter Maydell wrote:
@@ -841,6 +841,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at
Hi Cédric,
On 18/3/22 14:28, Cédric Le Goater wrote:
The initial eMMC support from Vincent Palatin was largely reworked to
match the current SD framework. The parameters mimick a real 4GB eMMC,
but it can be set to various sizes.
This adds a new QOM object class for EMMC devices.
Hi Joel,
On 18/3/22 14:28, Cédric Le Goater wrote:
From: Joel Stanley
The userdata size is derived from the file the user passes on the
command line, but we must take into account the boot areas.
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
hw/sd/sd.c | 6 ++
1
On 07/05/2022 20:06, Daniel Henrique Barboza wrote:
Hi,
Since the 7.0.0 release cycle we have a desire to use the powernv
emulation with libvirt. To do that we need to enable user creatable
pnv-phb devices to allow more user customization an to avoid spamming
multiple default devices in the
The test is in tests/tcg/multiarch/float_convd.c
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/float_convd.ref | 988 ++
1 file changed, 988 insertions(+)
create mode 100644 tests/tcg/hexagon/float_convd.ref
diff --git a/tests/tcg/hexagon/float_convd.ref
The store width is needed for packet commit, so it is stored in
ctx->store_width. Currently, it is set when a store has a TCG
override instead of a QEMU helper. In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet commit
that uses the runtime store width.
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target/hexagon/genptr.c | 147 +++
The increment used in :brev tests was causing unaligned addresses
Change the increment and the relevant expected values
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/load_unpack.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
Remove encodings guarded by ifdef that is not defined
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/encode_pp.def | 23 ---
1 file changed, 23 deletions(-)
diff --git a/target/hexagon/imported/encode_pp.def
b/target/hexagon/imported/encode_pp.def
index
VyV operand is only used in the vshuff and vdeal instructions. These
instructions write to both VyV and VxV operands. In the case where
both operands are the same register, we need a separate location for
VyV. We use the existing vtmp field in CPUHexagonState.
Test case added in
On 18/3/22 14:28, Cédric Le Goater wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210624142209.1193073-9-f4...@amsat.org>
Signed-off-by: Cédric Le Goater
---
hw/sd/sd.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
@@
As discussed with Marcelo offlist, KVM notices multiple CPUs being set to the
same value within a small amount of time and keeps them synchronized. This is
the same code that handles TSC synchronization on the destination side of
migration.
Paolo
Il 9 maggio 2022 16:54:00 CEST, Marcelo
On 18/3/22 14:28, Cédric Le Goater wrote:
From: Joel Stanley
Signed-off-by: Joel Stanley
Signed-off-by: Cédric Le Goater
---
hw/sd/sd.c | 28 +---
1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index
On Mon, May 9, 2022 at 4:45 PM Richard Henderson
wrote:
>
> On 5/9/22 10:02, Dr. David Alan Gilbert (git) wrote:
> > diff --git a/roms/skiboot b/roms/skiboot
> > index 24a7eb3596..820d43c0a7 16
> > --- a/roms/skiboot
> > +++ b/roms/skiboot
> > @@ -1 +1 @@
> > -Subproject commit
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/syscall.c| 49 +
linux-user/uname.c | 2 +-
linux-user/user-internals.h | 2 +-
3 files changed, 25 insertions(+), 28 deletions(-)
diff --git
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 202 ++--
linux-user/strace.h | 4 +-
linux-user/syscall.c| 32 +++---
linux-user/uname.c | 2 +-
linux-user/uname.h | 2
From: Philippe Mathieu-Daudé
fill_thread_info() takes a pointer to const.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 61063fd974..ada3b587c0 100644
---
From: Philippe Mathieu-Daudé
Since v1:
- Rebased
v1:
https://lore.kernel.org/qemu-devel/20220306234005.52511-1-philippe.mathieu.da...@gmail.com/
Philippe Mathieu-Daudé (3):
linux-user/elfload: Remove pointless non-const CPUArchState cast
linux-user: Have do_syscall() use CPUArchState*
On 4/5/22 13:03, Stefan Pejic wrote:
From: Dragan Mladjenovic
The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in
nanoMips documentation as opcode[20..16]. It is, however, erroneously
considered as opcode[25..21] in the current QEMU implementation. In
function
Hi Stefan,
On 4/5/22 13:03, Stefan Pejic wrote:
The field ac in nanoMips instruction MTHLIP rs, ac is specified in
nanoMips documentation as opcode[15..14] (2 bits). However, in the
current QEMU code, the corresponding argument passed to the helper
gen_helper_mthlip() has the value of
On 5/9/22 11:04, Peter Maydell wrote:
The unsupported_encoding() macro logs a LOG_UNIMP message and then
generates code to raise the usual exception for an unallocated
encoding. Back when we were still implementing the A64 decoder this
was helpful for flagging up when guest code was using
On 4/5/22 13:04, Stefan Pejic wrote:
From: Dragan Mladjenovic
If both rs and rt are the same register, the nanoMips instruction
BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and
there is no delay slot). This commit provides such behavior. Without
this commit, this scenario
On 4/29/22 05:06, Xiaojuan Yang wrote:
+DEFINE_LOONGARCH_CPU_TYPE("Loongson-3A5000", loongarch_3a5000_initfn),
Follow up on the comments against patch 34, and reading the 3A5000 manual, I see
# On-chip integration of four 64-bit quad-launch superscalar GS464v processor
cores.
Therefore
On 9/5/22 14:41, Daniel P. Berrangé wrote:
When running 'make check' we only get a summary of progress on the
console. Fortunately meson/ninja have saved the raw test output to a
logfile. Exposing this log will make it easier to debug failures that
happen in CI.
Signed-off-by: Daniel P.
From: Philippe Mathieu-Daudé
Except hw/core/irq.c which implements the forward-declared opaque
qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not
using the typedef. Fix this single exception.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/adc/zynq-xadc.c | 4 ++--
On Fri, Apr 29, 2022 at 8:35 AM Anup Patel wrote:
>
> The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
> when "env->priv_ver == 0" (i.e. default v1.10) because the enum
> value of priv spec v1.10 is zero.
>
> Due to above issue, the sifive_u machine will see priv spec v1.12
>
On Wed, May 4, 2022 at 2:53 AM Frank Chang wrote:
>
> Hi Anup,
>
> I found that Atish has already submitted a patch to implement the
> mcountinhibit CSR:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg879349.html
>
Yeah. I think it depends on which series is merged first. The PMU
On 5/9/22 10:02, Dr. David Alan Gilbert (git) wrote:
diff --git a/roms/skiboot b/roms/skiboot
index 24a7eb3596..820d43c0a7 16
--- a/roms/skiboot
+++ b/roms/skiboot
@@ -1 +1 @@
-Subproject commit 24a7eb35966d93455520bc2debdd7954314b638b
+Subproject commit
On 5/9/22 07:53, Stefan Hajnoczi wrote:
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into
staging (2022-05-08 17:03:26 -0500)
are available in the Git repository at:
On Fri, Apr 29, 2022 at 8:20 PM Frank Chang wrote:
> Reviewed-by: Frank Chang
>
> On Fri, Apr 29, 2022 at 11:34 AM Anup Patel
> wrote:
>
>> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
>> the riscv_csrrw_check() function should generate virtual instruction
>> trap instead
Hi,
On Mon, May 02, 2022 at 10:01:41AM -0400, Andrea Bolognani wrote:
> On Mon, May 02, 2022 at 01:46:23PM +0200, Markus Armbruster wrote:
> > Andrea Bolognani writes:
> > >> > The wire protocol would still retain the unappealing
> > >> > name, but at least client libraries could hide the
> > >>
OASIS members and other interested parties,
OASIS and the OASIS Virtual I/O Device (VIRTIO) TC are pleased to announce
that Virtual I/O Device (VIRTIO) Version 1.2 is now available for public
review and comment.
Specification Overview:
This document describes the specifications of the 'virtio'
On 5/9/22 13:04, Peter Maydell wrote:
On Mon, 9 May 2022 at 18:56, Richard Henderson
wrote:
I'm not 100% sure how this "Other configuration control register" should be
handled, but
definitely not like this.
I see you're putting control of this register into loongarch_qemu_read in
554623226f800acf48a2ed568900c1c968ec9a8b:
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into
staging (2022-05-08 17:03:26 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220509
for you to fetch changes up
On Mon, 9 May 2022 at 18:56, Richard Henderson
wrote:
> I'm not 100% sure how this "Other configuration control register" should be
> handled, but
> definitely not like this.
>
> I see you're putting control of this register into loongarch_qemu_read in
> target/loongarch/cpu.c. Which, I suppose
Cc: ACPI maintainers.
I know nothing about ACPI, could one of you help out here?
r~
On 4/29/22 05:07, Xiaojuan Yang wrote:
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS| 2 +
hw/acpi/Kconfig| 4 +
hw/acpi/ls7a.c | 374
On 6.05.2022 07:31, Thomas Huth wrote:
On 05/05/2022 21.36, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This way there is at least some contact point for incoming patches.
We'll see whether the code still gets just a random patch a few times
a year or whether it requires a
On 5/9/22 04:38, yangxiaojuan wrote:
You are not considering CSR[0x420][49], which changes the format of this
mapping.
Thanks very much, I will consider the mapping format by read iocsr[0x420][49]
like this:
static uint64_t map_format(void)
{
LoongArchCPU *cpu;
CPULoongArchState
On 5/9/22 14:53, Cédric Le Goater wrote:
On 5/9/22 19:37, Daniel Henrique Barboza wrote:
On 5/5/22 14:36, Thomas Huth wrote:
Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.
Signed-off-by: Thomas Huth
---
Queued in
On 5/9/22 19:37, Daniel Henrique Barboza wrote:
On 5/5/22 14:36, Thomas Huth wrote:
Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.
Signed-off-by: Thomas Huth
---
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
I think
Signed-off-by: Laurent Vivier
---
include/qemu/sockets.h | 2 ++
net/net.c | 62 ++
2 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/include/qemu/sockets.h b/include/qemu/sockets.h
index 038faa157f59..47194b9732f8 100644
---
On Mon, May 9, 2022 at 6:05 PM Peter Maydell wrote:
>
> The unsupported_encoding() macro logs a LOG_UNIMP message and then
> generates code to raise the usual exception for an unallocated
> encoding. Back when we were still implementing the A64 decoder this
> was helpful for flagging up when
Signed-off-by: Laurent Vivier
---
net/socket-ng.c | 65 ++---
1 file changed, 62 insertions(+), 3 deletions(-)
diff --git a/net/socket-ng.c b/net/socket-ng.c
index aabdd0eed381..d4457f4bc63b 100644
--- a/net/socket-ng.c
+++ b/net/socket-ng.c
@@ -123,8
Signed-off-by: Laurent Vivier
---
net/socket-ng.c | 109
1 file changed, 101 insertions(+), 8 deletions(-)
diff --git a/net/socket-ng.c b/net/socket-ng.c
index 0876a4930389..2c70440a2b57 100644
--- a/net/socket-ng.c
+++ b/net/socket-ng.c
@@
It is less complex to manage special cases directly in
net_socketng_mcast_init() and net_socketng_udp_init().
Signed-off-by: Laurent Vivier
---
net/socket-ng.c | 144
1 file changed, 73 insertions(+), 71 deletions(-)
diff --git a/net/socket-ng.c
"-netdev socket" only supports inet sockets.
It's not a complex task to add support for unix sockets, but
the socket netdev parameters are not defined to manage well unix
socket parameters.
As discussed in:
"socket.c added support for unix domain socket datagram transport"
Copied from socket netdev file and modified to use SocketAddress
to be able to introduce new features like unix socket.
"udp" and "mcast" are squashed into dgram, multicast is detected
according to the IP address type.
"listen" and "connect" modes are changed to "server" and "client".
As
dgram_dst is a sockaddr_in structure. To be able to use it with
unix socket, use a pointer to a generic sockaddr structure.
Signed-off-by: Laurent Vivier
---
net/socket-ng.c | 76 ++---
1 file changed, 46 insertions(+), 30 deletions(-)
diff --git
On 5/9/22 02:29, Thomas Huth wrote:
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into
staging (2022-05-08 17:03:26 -0500)
are available in the Git repository at:
On Mon, 9 May 2022 15:09:46 +
"Shi, Guohuai" wrote:
>
>
> > -Original Message-
> > From: Greg Kurz
> > Sent: 2022年5月9日 22:29
> > To: Bin Meng
> > Cc: Christian Schoenebeck ; qemu-devel@nongnu.org;
> > Shi,
> > Guohuai ; Meng, Bin
> > Subject: Re: [PATCH 5/9] hw/9pfs: Add a
The unsupported_encoding() macro logs a LOG_UNIMP message and then
generates code to raise the usual exception for an unallocated
encoding. Back when we were still implementing the A64 decoder this
was helpful for flagging up when guest code was using something we
hadn't yet implemented. Now we
The Armv8.4 feature FEAT_IDST specifies that exceptions generated by
read accesses to the feature ID space should report a syndrome code
of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED).
The feature ID space is defined to be:
op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7},
On Wed, Apr 13, 2022 at 12:20:54PM +0800, Liu Yiding wrote:
> Refer to 26ec190964 virtiofsd: Do not use a thread pool by default
>
> Signed-off-by: Liu Yiding
> ---
> docs/tools/virtiofsd.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Hi,
Sorry it took so long to apply this!
> -Original Message-
> From: Greg Kurz
> Sent: 2022年5月9日 22:29
> To: Bin Meng
> Cc: Christian Schoenebeck ; qemu-devel@nongnu.org;
> Shi,
> Guohuai ; Meng, Bin
> Subject: Re: [PATCH 5/9] hw/9pfs: Add a 'local' file system backend driver for
> Windows
>
> [Please note: This e-mail is
From: Leonardo Bras
Add property that allows zero-copy migration of memory pages
on the sending side, and also includes a helper function
migrate_use_zero_copy_send() to check if it's enabled.
No code is introduced to actually do the migration, but it allow
future implementations to
From: Leonardo Bras
Since d48c3a0445 ("multifd: Use a single writev on the send side"),
sending the header packet and the memory pages happens in the same
writev, which can potentially make the migration faster.
Using channel-socket as example, this works well with the default copying
mechanism
From: Daniel P. Berrangé
This validates that we correctly handle migration success and failure
scenarios when using TLS with pre shared keys.
Signed-off-by: Daniel P. Berrangé
Message-Id: <20220426160048.812266-4-berra...@redhat.com>
Reviewed-by: Eric Blake
Signed-off-by: Dr. David Alan
From: Daniel P. Berrangé
This validates that we correctly handle multifd migration success
and failure scenarios when using TLS with x509 certificates. There
are quite a few different scenarios that matter in relation to
hostname validation, but we skip a couple as we can assume that
the
From: Leonardo Bras
Even though multifd_send_sync_main() currently emits error_reports, it's
callers don't really check it before continuing.
Change multifd_send_sync_main() to return -1 on error and 0 on success.
Also change all it's callers to make use of this change and possibly fail
From: Leonardo Bras
A lot of places check parameters.tls_creds in order to evaluate if TLS is
in use, and sometimes call migrate_get_current() just for that test.
Add new helper function migrate_use_tls() in order to simplify testing
for TLS usage.
Signed-off-by: Leonardo Bras
Reviewed-by:
From: Leonardo Bras
Add flags to io_writev and introduce io_flush as optional callback to
QIOChannelClass, allowing the implementation of zero copy writes by
subclasses.
How to use them:
- Write data using qio_channel_writev*(...,QIO_CHANNEL_WRITE_FLAG_ZERO_COPY),
- Wait write completion with
From: Daniel P. Berrangé
This validates that we correctly handle multifd migration success
and failure scenarios when using TLS with pre shared keys.
Signed-off-by: Daniel P. Berrangé
Message-Id: <20220426160048.812266-8-berra...@redhat.com>
Reviewed-by: Eric Blake
Signed-off-by: Dr. David
From: Leonardo Bras
Implement zero copy send on nocomp_send_write(), by making use of QIOChannel
writev + flags & flush interface.
Change multifd_send_sync_main() so flush_zero_copy() can be called
after each iteration in order to make sure all dirty pages are sent before
a new iteration is
From: Leonardo Bras
For CONFIG_LINUX, implement the new zero copy flag and the optional callback
io_flush on QIOChannelSocket, but enables it only when MSG_ZEROCOPY
feature is available in the host kernel, which is checked on
qio_channel_socket_connect_sync()
qio_channel_socket_flush() was
From: Daniel P. Berrangé
Various methods in the migration test call 'query_migrate' to fetch the
current status and then access a particular field. Almost all of these
cases expect the migration to be in a non-failed state. In the case of
'wait_for_migration_pass' in particular, if the status is
From: Daniel P. Berrangé
These macros are more suited to the general consumers of certs in the
test suite, where we don't need to exercise every single possible
permutation.
Signed-off-by: Daniel P. Berrangé
Message-Id: <20220426160048.812266-3-berra...@redhat.com>
Reviewed-by: Eric Blake
From: Daniel P. Berrangé
We need to encode just the address bytes, not the whole struct sockaddr
data. Add a test case to validate that we're matching on SAN IP
addresses correctly.
Signed-off-by: Daniel P. Berrangé
Message-Id: <20220426160048.812266-2-berra...@redhat.com>
Reviewed-by: Dr.
From: Daniel P. Berrangé
This validates that we correctly handle migration success and failure
scenarios when using TLS with x509 certificates. There are quite a few
different scenarios that matter in relation to hostname validation.
Signed-off-by: Daniel P. Berrangé
Message-Id:
From: Daniel P. Berrangé
Most of the XBZRLE migration test logic is common with the rest of the
precopy tests, so it can use the helper with just one small tweak.
Reviewed-by: Peter Xu
Signed-off-by: Daniel P. Berrangé
Message-Id: <20220426160048.812266-6-berra...@redhat.com>
Signed-off-by:
From: Daniel P. Berrangé
Most of the multifd migration test logic is common with the rest of the
precopy tests, so it can use the helper without difficulty. The only
exception of the multifd cancellation test which tries to run multiple
migrations in a row.
Reviewed-by: Peter Xu
Signed-off-by:
From: "Dr. David Alan Gilbert"
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into
staging (2022-05-08 17:03:26 -0500)
are available in the Git repository at:
On Thu, Mar 24, 2022 at 06:31:36PM +0100, Paolo Bonzini wrote:
> Some versions of Windows hang on reboot if their TSC value is greater
> than 2^54. The calibration of the Hyper-V reference time overflows
> and fails; as a result the processors' clock sources are out of sync.
>
> The issue is
Hi Alex,
On 5/9/22 15:59, Alex Bennée wrote:
> Eric Auger writes:
>
>> Up to now the virt-machine node contains a virtio-mmio node.
>> However no driver produces any PCI interface node. Hence, PCI
>> tests cannot be run with aarch64 binary.
>>
>> Add a GPEX driver node that produces a pci
Documentation describes 5 new parameters being added regarding SR-IOV:
sriov_max_vfs
sriov_vq_flexible
sriov_vi_flexible
sriov_max_vi_per_vf
sriov_max_vq_per_vf
The description also includes the simplest possible QEMU invocation
and the series of NVMe commands required to enable SR-IOV support.
On Mon, 25 Apr 2022 22:27:01 +0800
Bin Meng wrote:
> From: Guohuai Shi
>
> Add a 9p local file system backend driver to support Windows,
> including open, read, write, close, rename, remove, etc.
>
> All security models are supported. The mapped (mapped-xattr)
> security model is implemented
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