On Tue, 25 Oct 2022 13:25:22 +0100
Peter Maydell wrote:
> On Mon, 17 Oct 2022 at 10:30, Ake Koomsin wrote:
> >
> > When HCR_E2H is set, AT S1E2R and AT S1E2W should translate an
> > address based on both TTBR0_EL2 and TTBR1_EL2.
> >
> > Signed-off-by: Ake Koomsin
> > ---
> >
Hi Connie,
On 10/25/22 6:54 PM, Cornelia Huck wrote:
On Mon, Oct 24 2022, Gavin Shan wrote:
These 3 high memory regions are usually enabled by default, but
s/These 3/The/ ?
Ok.
they may be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't
needed by GICv2. This leads to waste in the
Hi Connie,
On 10/25/22 6:30 PM, Cornelia Huck wrote:
On Mon, Oct 24 2022, Gavin Shan wrote:
After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/tricore/cpu.c | 11 +++
target/tricore/translate.c | 6 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index ab7a1e3a6d..2c54a2825f
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sh4/cpu.c | 16
target/sh4/translate.c | 10 --
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 56c50530da..453268392b 100644
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 3 +++
target/sparc/cpu.c | 1 +
target/sparc/translate.c | 7 +--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index
We missed this function when we introduced tb_page_addr_t.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 2 +-
include/exec/ram_addr.h | 2 --
accel/tcg/tb-maint.c| 13 ++---
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/alpha/cpu.c | 9 +
target/alpha/translate.c | 6 --
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 979a629d59..270ae787b1 100644
---
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 11 +++
target/avr/translate.c | 6 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0d2861179d..c7295b488d 100644
---
There are no users outside of accel/tcg; this function
does not need to be defined in exec-all.h.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h| 5 +
include/exec/exec-all.h | 8
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/xtensa/cpu.c | 10 ++
target/xtensa/translate.c | 6 --
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index cbbe0e84a2..09923301c4
The results of the calls to cpu_get_tb_cpu_state,
current_{pc,cs_base,flags}, are not used.
In tb_invalidate_phys_page, use bool for current_tb_modified.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tb-maint.c | 25 ++---
1 file changed, 2
Use a constant target data allocation size for all pages.
This will be necessary to reduce overhead of page tracking.
Since TARGET_PAGE_DATA_SIZE is now required, we can use this
to omit data tracking for targets that don't require it.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
From: Qi Hu
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch. Additionally, if instruction "B offset" can cover the target
address(target is within ±128MB range), a single "B offset" plus a nop
When PAGE_RESET is set, we are replacing pages with new
content, which means that we need to invalidate existing
cached data, such as TranslationBlocks. Perform the
reset invalidate while we're doing other invalidates,
which allows us to remove the separate invalidates from
the user-only
Use the existing function for clearing target data.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index
This data structure will be replaced for user-only: add accessors.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 22 ++
accel/tcg/cpu-exec.c | 9 +
accel/tcg/tb-maint.c | 29 +++--
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.c | 11 +++
target/microblaze/translate.c | 7 ---
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index
This differs from assert, in that with optimization enabled it
triggers at build-time. It differs from QEMU_BUILD_BUG_ON,
aka _Static_assert, in that it is sensitive to control flow
and is subject to dead-code elimination.
Acked-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/mips/tcg/tcg-internal.h | 3 +++
target/mips/cpu.c | 1 +
target/mips/tcg/translate.c| 8 ++--
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/tcg-internal.h
From: Qi Hu
AArch64 defines the TCG_TARGET_HAS_direct_jump. So the "else" block is
useless in the case of "INDEX_op_goto_tb" in function "tcg_out_op". Add
an assertion and delete these codes for clarity.
Suggested-by: WANG Xuerui
Signed-off-by: Qi Hu
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/m68k/cpu.c | 14 ++
target/m68k/translate.c | 10 --
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 1e902e1ef0..b67ddea2ae
From: Peter Maydell
Commit a82fd5a4ec24d was intended to be a code cleanup, but
unfortunately it has a bug. It moves the initialization of the
TCG cflags from the "start a new vcpu" function to the
thread handler; this is fine when each vcpu has its own thread,
but when we are doing round-robin
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/nios2/cpu.c | 11 +++
target/nios2/translate.c | 6 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 2b28429c08..9a5351bc81 100644
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/riscv/cpu.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e6d9c706bb..d14e95c9dc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
Add a tcg_ops hook to replace the restore_state_to_opc
function call. Because these generic hooks cannot depend
on target-specific types, temporarily, copy the current
target_ulong data[] into uint64_t d64[].
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/tcg-cpu.c | 19 +++
target/i386/tcg/translate.c | 15 ---
2 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/loongarch/cpu.c | 11 +++
target/loongarch/translate.c | 6 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index
These items printf, and could be replaced with proper
tracepoints if we really cared.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 109 --
1 file changed, 109 deletions(-)
diff --git a/accel/tcg/translate-all.c
This function is is never called with a real range,
only for a single page. Drop the second parameter
and rename to tb_invalidate_phys_page.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/translate-all.h | 2 +-
accel/tcg/tb-maint.c | 15 ---
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/rx/cpu.c | 10 ++
target/rx/translate.c | 6 --
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 2f28099723..9003c6e9fe 100644
---
Use qatomic_*, which expands to __atomic_* in preference
to the "legacy" __sync_* functions.
Acked-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
include/qemu/thread.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/qemu/thread.h
When we added the fast path, we initialized page_addr[] early.
These stores in and around tb_page_add() are redundant; remove them.
Fixes: 50627f1b7b1 ("accel/tcg: Add fast path for translator_ld*")
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/tb-maint.c | 3 ---
1
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/ppc/cpu_init.c | 10 ++
target/ppc/translate.c | 6 --
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 763a8431be..335351c226 100644
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/s390x/s390x-internal.h | 4 +++-
target/s390x/cpu.c| 1 +
target/s390x/tcg/translate.c | 7 +--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/s390x/s390x-internal.h
Rename to tb_invalidate_phys_page_unwind to emphasize that
we also detect invalidating the current TB, and also to free
up that name for other usage.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 2 +-
accel/tcg/tb-maint.c | 2 +-
All targets have been updated. Use the tcg_ops target hook
exclusively, which allows the compat code to be removed.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 3 ---
accel/tcg/translate-all.c | 16 ++--
2 files changed, 2
Since the only user, Arm MTE, always requires allocation,
merge the get and alloc functions to always produce a
non-null result. Also assume that the user has already
checked page validity.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 21
Since "target data" is always user-only, move it out of
translate-all.c to user-exec.c.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 50 ---
accel/tcg/user-exec.c | 50 +++
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/cris/cpu.c | 11 +++
target/cris/translate.c | 6 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 22f5c70f39..fb05dc6f9a 100644
---
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hppa/cpu.c | 19 +++
target/hppa/translate.c | 13 -
2 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hexagon/cpu.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index fa6d722555..03221fbdc2 100644
--- a/target/hexagon/cpu.c
+++
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.c | 13 +
target/openrisc/translate.c | 10 --
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 26 ++
target/arm/translate.c | 22 --
2 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 31 +++
accel/tcg/translate-all.c | 31 +--
2 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/accel/tcg/internal.h
Move all of the TranslationBlock flushing and page linking
code from translate-all.c to tb-maint.c.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 55 +++
accel/tcg/tb-maint.c | 735
accel/tcg/translate-all.c
From: Leandro Lupori
Profiling QEMU during Fedora 35 for PPC64 boot revealed that a
considerable amount of time was being spent in
check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on
amd64), even though it was just checking that its queue was empty
and returning, when no
We do not require detection of overlapping TBs here,
so use the more appropriate function.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/translate-all.c
Change from QEMU_BUILD_BUG_ON, which requires ifdefs to avoid
problematic code, to qemu_build_assert, which can use C ifs.
Acked-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/qemu/atomic.h | 16
1 file changed, 8
The following changes since commit e750a7ace492f0b450653d4ad368a77d6f660fb8:
Merge tag 'pull-9p-20221024' of https://github.com/cschoenebeck/qemu into
staging (2022-10-24 14:27:12 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221026
for
Flush translation blocks in bulk, rather than page-by-page.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index
On 10/26/22 10:44, Bin Meng wrote:
../src/tests/qtest/migration-test.c: In function ‘main’:
../src/tests/qtest/migration-test.c:2484:49: error: ‘%s’ directive argument is
null
[-Werror=format-overflow=]
2484 | g_test_message("g_dir_make_tmp on path (%s): %s", tmpfs,
|
This patch enables the direct assignment of a NUMA node to a volatile or
persistent memory region on a CXL type-3 device. This is useful for
testing static mapping for type-3 device memory regions as memory and
leveraging them directly via its NUMA node.
Co-developed-By: Davidlohr Bueso
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
---
hw/cxl/cxl-mailbox-utils.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
Submitted as an extention to the multi-feature branch maintained
by Jonathan Cameron at:
https://gitlab.com/jic23/qemu/-/tree/cxl-2022-10-24
Summary of Changes:
1) E820 CFMW Bug fix.
2) Add CXL_CAPACITY_MULTIPLIER definition to replace magic numbers
3) Multi-Region and Volatile Memory support
Early-boot e820 records will be inserted by the bios/efi/early boot
software and be reported to the kernel via insert_resource. Later, when
CXL drivers iterate through the regions again, they will insert another
resource and make the RESERVED memory area a child.
This RESERVED memory area causes
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been deprecated and will default the
On Wed, Oct 26, 2022 at 7:44 AM Richard Henderson
wrote:
>
> On 10/7/22 01:19, Bin Meng wrote:
> > From: Bin Meng
> >
> > This case was written to use hardcoded /tmp directory for temporary
> > files. Update to use g_dir_make_tmp() for a portable implementation.
> >
> > Signed-off-by: Bin Meng
Hi Eric,
On 10/26/22 12:29 AM, Eric Auger wrote:
On 10/24/22 05:54, Gavin Shan wrote:
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in
Hi Peter and Marc,
On 10/24/22 11:54 AM, Gavin Shan wrote:
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.
(1) One specific
We use the .h.inc extension to include C headers. To be consistent
with the rest of the codebase, rename the C headers using the .def
extension.
IDE/tools using our .editorconfig / .gitattributes will leverage
this consistency.
Philippe Mathieu-Daudé (3):
target/m68k: Rename qregs.def ->
We use the .h.inc extension to include C headers. To be consistent
with the rest of the codebase, rename the C headers using the .def
extension.
IDE/tools using our .editorconfig / .gitattributes will leverage
this consistency.
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/{csfr.def
We use the .h.inc extension to include C headers. To be consistent
with the rest of the codebase, rename the C headers using the .def
extension.
IDE/tools using our .editorconfig / .gitattributes will leverage
this consistency.
Signed-off-by: Philippe Mathieu-Daudé
---
On 10/25/22 22:25, Peter Maydell wrote:
In the pseudocode, E2H is handled by changing the behaviour not
just of the S1E2 ops, but also of the S1E1 ops. If E2H is set:
* the S1E2 ops use the EL2&0 regime, but continue to ignore
PSTATE.PAN
* the S1E1 ops also use the EL2&0 regime, with the
We use the .h.inc extension to include C headers. To be consistent
with the rest of the codebase, rename the C headers using the .def
extension.
IDE/tools using our .editorconfig / .gitattributes will leverage
this consistency.
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/{qregs.def
On 10/7/22 01:19, Bin Meng wrote:
From: Bin Meng
This case was written to use hardcoded /tmp directory for temporary
files. Update to use g_dir_make_tmp() for a portable implementation.
Signed-off-by: Bin Meng
Reviewed-by: Marc-André Lureau
---
Changes in v5:
- Use g_autoptr(GError)
On Tue, Oct 25, 2022 at 2:36 PM Wilfred Mallawa
wrote:
>
> From: Wilfred Mallawa
>
> This patch provides updates to the OpenTitan model to bump to RTL
> version .
>
> A unique change here is the merger of hwip `padctrl` into `pinmux`, to
> reflect this change, any references to `padctrl` are
On 22/10/22 17:04, Bernhard Beschow wrote:
PIIX3 initializes the PIRQx route control registers to the default
values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)
April 1997 manual. PIIX4, however, initializes the routes according to
the Malta™ User’s Manual, ch 6.6, which are
On Mon, Oct 24, 2022 at 1:26 PM Richard Henderson
wrote:
>
> When guest_base != 0, we were not coordinating the usage of
> TCG_REG_TMP0 as base properly, leading to a previous zero-extend
> of the input address being discarded.
>
> Shuffle the alignment check to the front, because that does not
>
On 22/10/22 17:04, Bernhard Beschow wrote:
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 3 ++-
hw/ide/piix.c | 5 +++--
hw/isa/piix4.c| 3 ++-
include/hw/ide/piix.h | 7 +++
4 files changed, 14 insertions(+), 4
On 10/25/22 19:23, Claudio Fontana wrote:
+/*
+ * The cpu state corresponding to 'host_pc' is restored.
+ * When reset_icount is true, current TB will be interrupted and
+ * icount should be recalculated.
+ */
+static void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
+
On Mon, Oct 24, 2022 at 1:26 PM Richard Henderson
wrote:
>
> When guest_base != 0, we were not coordinating the usage of
> TCG_REG_TMP0 as base properly, leading to a previous zero-extend
> of the input address being discarded.
>
> Shuffle the alignment check to the front, because that does not
>
Queued for next pull, thanks!
On Tue, Oct 25, 2022 at 11:06:39PM +0100, Jonathan Cameron wrote:
>
> Hi Michael,
>
> Any chance of this making 7.2? Gregory has identified a bug
> in the Linux kernel support that we've reported (debug marking
> related). I don't think there are any other queries
On 10/25/22 22:43, Paolo Bonzini wrote:
On 10/25/22 01:24, Richard Henderson wrote:
The current use of _Static_assert, via QEMU_BUILD_BUG_ON, requires
the user have #if conditionals to avoid the statement from appearing
in the preprocessed file at all. Introduce a new primitive that
allows
On 10/25/22 23:47, Claudio Fontana wrote:
On 10/25/22 01:24, Richard Henderson wrote:
Use qatomic_*, which expands to __atomic_* in preference
to the "legacy" __sync_* functions.
Signed-off-by: Richard Henderson
---
include/qemu/thread.h | 8
1 file changed, 4 insertions(+), 4
Hi Michael,
Any chance of this making 7.2? Gregory has identified a bug
in the Linux kernel support that we've reported (debug marking
related). I don't think there are any other queries outstanding on this.
I've been holding off on sending other features to focus on
getting this in, but
On Tue, Oct 25, 2022 at 4:24 AM Daniel P. Berrangé wrote:
>
> On Mon, Oct 24, 2022 at 03:53:54PM -0400, John Snow wrote:
> > When key decisions are made about the lifetime of the VM process being
> > managed, there's no log entry. Juxtaposed with the very verbose runstate
> > change logging of
On 10/26/22 07:37, Richard Henderson wrote:
On 10/26/22 06:24, Leandro Lupori wrote:
Profiling QEMU during Fedora 35 for PPC64 boot revealed that a
considerable amount of time was being spent in
check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on
amd64), even though it was just
On 10/26/22 06:24, Leandro Lupori wrote:
Profiling QEMU during Fedora 35 for PPC64 boot revealed that a
considerable amount of time was being spent in
check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on
amd64), even though it was just checking that its queue was empty
and
Also update PowerMac family docs with some more recent info.
Signed-off-by: BALATON Zoltan
---
docs/about/deprecated.rst| 7 +++
docs/system/ppc/powermac.rst | 12
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/docs/about/deprecated.rst
Please solve this CI failure:
c++ -o qemu-system-s390x ...
/usr/bin/ld: libqemu-s390x-softmmu.fa.p/target_s390x_arch_dump.c.o: in
function `arch_sections_add':
/home/gitlab-runner/builds/Y1MP9VSY/0/qemu-project/qemu/build/../target/s390x/arch_dump.c:392:
undefined reference to
On Tue, 25 Oct 2022, BALATON Zoltan wrote:
Since only one week is left until freeze starts I've included some
more patches in this version that I've intended to submit after the
clean ups but we're running out of time now. The last 3 patches could
be squashed together, I've just split these up
OpenBIOS cannot run FCode ROMs yet but it can detect NDRV in VGA card
ROM and add it to the device tree for MacOS. Pass the NDRV this way
instead of via fw_cfg. This solves the problem with OpenBIOS also
adding the NDRV to ati-vga which it does not work with. This does not
need any changes to
I wanted to make sure that the pair elements were not mixed up and
wrote a small test. Feel free to add it to the series.
Ilya Leoshkevich (1):
tests/tcg/s390x: Add clst.c
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/clst.c | 82 +
2 files
On 10/26/22 05:30, Alex Bennée wrote:
void *page_get_target_data(target_ulong address)
{
-PageDesc *p = page_find(address >> TARGET_PAGE_BITS);
-void *ret = p->target_data;
+IntervalTreeNode *n;
+TargetPageDataNode *t;
+target_ulong page, region;
+bool locked;
-
Add a basic test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/clst.c | 82 +
2 files changed, 83 insertions(+)
create mode 100644 tests/tcg/s390x/clst.c
diff --git
On Fri, Oct 21, 2022 at 05:30:00PM +1000, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> target/s390x/helper.h | 2 +-
> target/s390x/tcg/mem_helper.c | 11 ---
> target/s390x/tcg/translate.c | 8 ++--
> 3 files changed, 11 insertions(+), 10
On 10/26/22 01:58, Alex Bennée wrote:
Richard Henderson writes:
Begin weaning user-only away from PageDesc.
Since, for user-only, all TB (and page) manipulation is done with
a single mutex, and there is no virtual/physical discontinuity to
split a TB across discontinuous pages, place all of
On 10/26/22 01:42, Alex Bennée wrote:
Not a problem with this patch but I was a little confused by PAGE_VALID
because its the one "special" flag not documented in cpu-all.h:
/* same as PROT_xxx */
#define PAGE_READ 0x0001
#define PAGE_WRITE 0x0002
#define PAGE_EXEC
On Fri, Oct 21, 2022 at 05:29:59PM +1000, Richard Henderson wrote:
> Pack the quotient and remainder into a single Int128.
> Use the divu128 primitive to remove the cpu_abort on
> 32-bit hosts.
>
> This is the first use of Int128 as a return value.
>
> Signed-off-by: Richard Henderson
On 10/25/22 16:29, Daniel Henrique Barboza wrote:
On 10/21/22 14:01, Leandro Lupori wrote:
Profiling QEMU during Fedora 35 for PPC64 boot revealed that
6.39% of total time was being spent in helper_insns_inc(), on a
POWER9 machine. To avoid calling this helper every time PMCs had
to be
Il mar 25 ott 2022, 16:39 Greg Kurz ha scritto:
> > > -if (logfile && (!need_to_open_file || changed_name)) {
> > > -qatomic_rcu_set(_file, NULL);
>
> Hmm... wait, shouldn't this NULLifying be performed...
>
> > > -if (logfile != stderr) {
> > > +if (logfile) {
> > > +
Add 2 new PMC related HFLAGS:
- HFLAGS_PMCJCE - value of MMCR0 PMCjCE bit
- HFLAGS_PMC_OTHER - set if a PMC other than PMC5-6 is enabled
These flags allow further optimization of PMC5 update code, by
allowing frequently tested conditions to be performed at
translation time.
Signed-off-by:
Changes from v1:
- Turn macro into an inline function
- Rename functions
Leandro Lupori (3):
accel/tcg: Add a quicker check for breakpoints
target/ppc: Add new PMC HFLAGS
target/ppc: Increment PMC5 with inline insns
accel/tcg/cpu-exec.c | 15
target/ppc/cpu.h | 4 ++-
Profiling QEMU during Fedora 35 for PPC64 boot revealed that
6.39% of total time was being spent in helper_insns_inc(), on a
POWER9 machine. To avoid calling this helper every time PMCs had
to be incremented, an inline implementation of PMC5 increment and
check for overflow was developed. This led
Profiling QEMU during Fedora 35 for PPC64 boot revealed that a
considerable amount of time was being spent in
check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on
amd64), even though it was just checking that its queue was empty
and returning, when no breakpoints were set. It turns
On Fri, Oct 21, 2022 at 05:15:32PM +1000, Richard Henderson wrote:
> Change 32-bit tci TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EVEN, to
> force 32-bit values to be aligned to 64-bit. With a small reorg
> to the argument processing loop, this neatly replaces an ifdef for
> CONFIG_TCG_INTERPRETER.
Hi
We are doing some network experiment and found something that we can't
explain well.
We are using qemu+kvm to create a sandbox and use virtio vhost net to setup
the network between guest and host. Then we start to send some traffics
from host to guest and guest to host.
An interesting finding
The following CI failures were reported. I think they may be related
to this pull request:
cc -m64 -mcx16 -Ilibblock.fa.p -I. -I.. -Iqapi -Itrace -Iui
-Iui/shader -Iblock -I/usr/include/p11-kit-1
-I/usr/include/x86_64-linux-gnu -I/usr/include/uuid
-I/usr/include/glib-2.0
On Wed, 2022-10-12 at 18:20 +0200, Pierre Morel wrote:
> In the S390x CPU topology the core_id specifies the CPU address
> and the position of the core withing the topology.
>
> Let's build the topology based on the core_id.
> s390x/cpu topology: core_id sets s390x CPU topology
>
> In the S390x
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