This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.
Signed-off-by: Bin Meng
---
hw/riscv/Makefile.objs | 1
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
Signed-off-by: Bin Meng
---
hw/riscv/Makefile.objs | 2 +-
hw/riscv/sifive_e.c
"linux,phandle" property is optional. Remove all instances in the
sifive_u and virt machine device tree.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 3 ---
hw/riscv/virt.c | 3 ---
2 files changed, 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
ind
It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN
for hfxosccfg register programming.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_e_prci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index acb914d
Hi Fabien,
On Tue, Jul 9, 2019 at 12:31 AM Fabien Chouteau wrote:
>
> Hi Bin,
>
> Thanks for this patch.
>
> I know I am very late to the game but I have a comment here.
>
> On 17/05/2019 17:51, Bin Meng wrote:
> > +/* create PLIC hart
Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create symmetric harts. Exact the
hart realize to a separate routine in preparation for supporting
heterogeneous hart arrays.
Signed-off-by: Bin
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 08d406f..206eccc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -428,6
This updates the UART base address to match the hardware.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b235f29..9f05e09 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv
...",
causing U-Boot fail to find the serial node in DT.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 20dee52..8044166 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree, and updates its compatible string, to
keep in sync with the Linux kernel device tree.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 4 +---
hw/riscv/virt.c | 4 +---
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt. Other machines (sifive_u, spike)
don't do it neither.
Signed-off-by: Bin Meng
---
hw/riscv/virt.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/virt.c b
When CADENCE_GEM_ERR_DEBUG is turned on, there are several
compilation errors in DB_PRINT(). Fix them.
Signed-off-by: Bin Meng
---
hw/net/cadence_gem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index d412085..7516e8f
penSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well.
For Linux, only checked boot log of MACB probe success without error.
Bin Meng (28):
riscv: hw: Remove superfluous "linux,phandle" property
riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
riscv
Hi Alistair,
On Tue, Jul 16, 2019 at 5:33 AM Alistair Francis wrote:
>
> On Sat, Jul 13, 2019 at 8:23 PM Bin Meng wrote:
> >
> > Hi Fabien,
> >
> > On Tue, Jul 9, 2019 at 12:31 AM Fabien Chouteau
> > wrote:
> > >
> > > Hi Bin,
> >
e official name used
by the upstream Linux kernel, and add the management block reg base
& size to the property encoding.
Tested with upstream U-Boot and Linux kernel MACB drivers.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 17 +
include/hw/riscv/sifive_u
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9f05e09..dfcb525 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv
The Linux kernel SiFive UART driver expects an aliases node to be
present in the device tree, from which the driver extracts the port
number from "serial#" in the aliases node.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 16
hw/riscv/virt.c | 24
2 files changed, 20 insertions(+), 20 deletions
d DTS have been updated as well.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 623ee64..08d406f 100644
--- a/hw/riscv/sifive_u.c
+++
Now that we have added PRCI nodes, update existing UART and ethernet
nodes to use PRCI as their clock sources, to keep in sync with the
Linux kernel device tree.
With above changes, the previously handcrafted "/soc/ethclk" node is
no longer needed. Remove it.
Signed-off-by: Bin Meng
The loading of initramfs is currently not supported on 'sifive_u'.
Add the support to make '-initrd' command line parameter useful.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/sifive_u_prci.c | 163 +++
include
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
---
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw/riscv/sifive_e.h | 7 +--
include/hw/riscv/sifive_u.h | 7 +--
3 files changed, 33 insertions(+), 12 deletions
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 23 +++
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 25 insertions(+)
diff
sifive_mmio_emulate() is currently only used in the sifive_e machine
codes. It can be helpful for other machines as well.
Change it to an inline routine and move it to sifive_cpu.h, so that
other machines like sifive_u can use it.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_e.c | 8
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 21 -
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 21 insertions(+), 1 deletion(-)
diff
rt 0, and the second cpu type before delimiter is assigned to
hart 1, and so on.
If the total number of cpu types supplied in "cpu-type" property is
less than number of maximum harts, the last cpu type in the property
will be used to populate remaining harts.
Signed-off-by: Bin Meng
--
On Wed, Aug 7, 2019 at 5:06 AM Philippe Mathieu-Daudé wrote:
>
> On 8/5/19 8:43 AM, Bin Meng wrote:
> > On Mon, Aug 5, 2019 at 2:14 PM Chih-Min Chao
> > wrote:
> >> On Sat, Aug 3, 2019 at 8:27 AM Bin Meng wrote:
> >>>
> >>> Some of the S
On Wed, Aug 7, 2019 at 5:06 AM Philippe Mathieu-Daudé wrote:
>
> On 8/5/19 8:43 AM, Bin Meng wrote:
> > On Mon, Aug 5, 2019 at 2:14 PM Chih-Min Chao
> > wrote:
> >> On Sat, Aug 3, 2019 at 8:27 AM Bin Meng wrote:
> >>>
> >>> Some of the S
When CADENCE_GEM_ERR_DEBUG is turned on, there are several
compilation errors in DB_PRINT(). Fix them.
While we are here, update to use appropriate modifiers in
the same DB_PRINT() call.
Signed-off-by: Bin Meng
---
Changes in v3:
- use PRIx64 as rx_desc_get_buffer() returns uint64_t
- use %u
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
-by: Bin Meng
---
hmp-commands-info.hx | 2 +-
target/riscv/Makefile.objs | 4 +
target/riscv/monitor.c | 227 +
3 files changed, 232 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/monitor.c
diff --git a/hmp-commands-info.hx b/hmp
On Thu, Aug 1, 2019 at 10:16 PM Richard Henderson
wrote:
>
> On 7/31/19 6:53 PM, Bin Meng wrote:
> > I am not sure how (idx * ptesize) could overflow. It represents the
> > offset by a page table which is [0, 4096).
>
> You're right, I mis-read what was going on there.
Hi Palmer,
On Sat, Jul 20, 2019 at 9:47 AM Palmer Dabbelt wrote:
>
> On Fri, 14 Jun 2019 08:15:51 PDT (-0700), bmeng...@gmail.com wrote:
> > This adds a reset opcode for sifive_test device to trigger a system
> > reset for testing purpose.
> >
> > Signed-off-by:
Hi Philippe,
On Sat, Sep 21, 2019 at 4:51 PM Philippe Mathieu-Daudé
wrote:
>
> Hi Bin,
>
> On 9/21/19 7:41 AM, Bin Meng wrote:
> > The "clock-frequency" property of cpu nodes isn't required. Drop it.
> >
> > This is to keep in sync with Linux kernel commit
The "clock-frequency" property of cpu nodes isn't required. Drop it.
This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133031/
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2:
- drop the one in spike and virt ma
U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.
This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133033/
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv
On Sat, Sep 21, 2019 at 6:12 AM Alistair Francis wrote:
>
> On Thu, Sep 19, 2019 at 10:15 PM Bin Meng wrote:
> >
> > On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
> > wrote:
> > >
> > > Add a property that when set to true QEMU will jump from the R
On Sat, Sep 21, 2019 at 6:16 AM Alistair Francis wrote:
>
> On Thu, Sep 19, 2019 at 10:15 PM Bin Meng wrote:
> >
> > On Fri, Sep 20, 2019 at 6:36 AM Alistair Francis
> > wrote:
> > >
> > > Add the CFI01 PFlash to the RISC-V virt board. This is the
On Fri, Sep 20, 2019 at 6:34 AM Alistair Francis
wrote:
>
> Instead of using the DEFINE_MACHINE() macro to define the machine let's
> do it manually. This allows us to specify machine properties.
>
> This patch is no functional change.
>
> Signed-off-by: Alistair Francis
> ---
>
On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
wrote:
>
> There doesn't seem to be details on what QSPI the HiFive Unleashed uses.
IMHO, this sentence should be removed as there are details available.
See the hifive-unleashed-a00.dts.
{
status = "okay";
flash@0 {
On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
wrote:
>
> On reset only a single L2 cache way is enabled, the others are exposed
> as memory that can be used by early boot firmware. This L2 region is
> generally disabled using the WayEnable register at a later stage in the
> boot process. To
On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
wrote:
>
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of DRAM which is the default
> behaviour.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_u.c | 27
hineState *machine)
> #endif
> 0x00028067, /* jr t0 */
> 0x,
> -memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base
> */
> +start_addr, /* start: .dword */
> 0x,
> /* dtb: */
> };
> --
Otherwise,
Reviewed-by: Bin Meng
On Fri, Sep 20, 2019 at 6:36 AM Alistair Francis
wrote:
>
> Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
> from the ARM Virt board and the implementation is based on the ARM Virt
> board. This allows users to specify flash files from the command line.
>
> Signed-off-by:
: %d; priv: "TARGET_FMT_ld"\n", cpu->cpu_index, env->priv);
Since this patch wants to be helpful for debugging, would it make more
sense to print out the priv mode string instead of the number, eg:
priv: M.
But I am fine with just printing out the number.
> +#endif
> log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
> }
Reviewed-by: Bin Meng
Tested-by: Bin Meng
ions.
> hw/riscv/sifive_u.c | 16
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 17 insertions(+)
>
Reviewed-by: Bin Meng
>
> This patch is no functional change.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/virt.c | 30 --
> include/hw/riscv/virt.h | 7 ++-
> 2 files changed, 30 insertions(+), 7 deletions(-)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
/sifive_u.h | 1 +
> 2 files changed, 9 insertions(+)
>
Reviewed-by: Bin Meng
is
> ---
> hw/riscv/sifive_u.c | 44 ++---
> include/hw/riscv/sifive_u.h | 7 +-
> 2 files changed, 37 insertions(+), 14 deletions(-)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis
wrote:
>
> Add a property that when set to true QEMU will jump from the ROM code to
> the start of flash memory instead of DRAM which is the default
> behaviour.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_u.c | 27
On Fri, Sep 27, 2019 at 8:57 AM Alistair Francis
wrote:
>
> If the user supplied pflash to QEMU then change the reset code to jump
> to the pflash base address instead of the DRAM base address.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Bin Meng
> Reviewed-by: P
t;
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/Kconfig| 1 +
> hw/riscv/virt.c | 86 +
> include/hw/riscv/virt.h | 3 ++
> 3 files changed, 90 insertions(+)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
On Tue, Sep 24, 2019 at 1:51 AM Alistair Francis wrote:
>
> On Sat, Sep 21, 2019 at 7:19 PM Bin Meng wrote:
> >
> > On Sat, Sep 21, 2019 at 6:12 AM Alistair Francis
> > wrote:
> > >
> > > On Thu, Sep 19, 2019 at 10:15 PM Bin Meng wrote:
> > >
The "clock-frequency" property of cpu nodes isn't required. Drop it.
This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133031/
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 2 --
include/hw/riscv/sifive_u.h | 1 -
2 files
U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.
This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133033/
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 5 -
1 file changed, 4 insertions(+), 1
On Mon, Nov 11, 2019 at 9:42 PM Anup Patel wrote:
>
> Correct Palmer's email address.
>
> > -Original Message-
> > From: Anup Patel
> > Sent: Monday, November 11, 2019 7:08 PM
> > To: Peter Maydell ; Palmer Dabbelt
> > ; Alistair Francis ; Sagar
> > Karandikar
> > Cc: Atish Patra ;
om 32MB to 64MB to ensure we have a single region that is 32MB.
>
> No QEMU release has include flash in the RISC-V virt machine, so this
> isn't a breaking change.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c
8086:100e
...
BAR1: I/O at 0x [0x003e].
...
It turns out we should set pci_allow_0_address to true to allow 0
PCI address, otherwise pci_bar_address() treats such address as
PCI_BAR_UNMAPPED.
Signed-off-by: Bin Meng
---
hw/riscv/virt.c | 1 +
1 file changed, 1 insertion(+)
On Sat, Nov 16, 2019 at 11:08 PM Bin Meng wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. Whe
sertions(+), 2 deletions(-)
> create mode 100644 gdb-xml/riscv-32bit-virtual.xml
> create mode 100644 gdb-xml/riscv-64bit-virtual.xml
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
If we are in debugger mode, skip the CSR privilege level checking
so that we can read/write all CSRs. Otherwise we get:
(gdb) p/x $mtvec
Could not fetch register "mtvec"; remote failure reply 'E14'
when the hart is currently in S-mode.
Reported-by: Zong Li
Signed-off-by: Bin Meng
--
On Wed, Sep 25, 2019 at 12:49 PM wrote:
>
> From: Guo Ren
>
nits: the title is probably better to be rephrased to: Ignore reserved
bits when calculating PPN for RV64
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They can not be a part of ppn.
> - Change to AND with a mask instead of shifting both directions
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
d riscv_cpu_register_gdb_regs_for_features(CPUState
> *cs)
> }
>
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> - 4096, "riscv-64bit-csr.xml", 0);
> + 240, "riscv-64bit-csr.xml", 0);
> #endif
> }
The change looks good to me.
Reviewed-by: Bin Meng
Hi Jim,
On Tue, Oct 8, 2019 at 5:17 AM Jim Wilson wrote:
>
> On 10/4/19 8:16 AM, Jonathan Behrens wrote:
> > diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
> > index 0d07aaec85..d6d76aafd8 100644
> > --- a/gdb-xml/riscv-32bit-cpu.xml
> > +++ b/gdb-xml/riscv-32bit-cpu.xml
Use the start_addr variable instead of editing reset vector
> - Fix function names
>
> hw/riscv/sifive_u.c | 30 +-
> include/hw/riscv/sifive_u.h | 2 ++
> 2 files changed, 31 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
On Tue, Oct 8, 2019 at 8:18 AM Jonathan Behrens wrote:
>
> This patch enables a debugger to read the current privilege level via a
> virtual
> "priv" register. When compiled with CONFIG_USER_ONLY the register is still
> visible but always reports the value zero.
>
> Signed-off-by: Jonathan
virtualization status
> when switching between VU/VS-modes and M-mode.
>
> Signed-off-by: Jonathan Behrens
> ---
> target/riscv/gdbstub.c | 9 +
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
hangelog V2:
> - Use PRV_H and PRV_S instead of integer literals
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
gt; the warning.
>
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/boot.c | 11 ---
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
Reviewed-by: Bin Meng
Thanks for the patch. I am not sure how I can easily run Coverity to
verify the fix though.
Regards,
Bin
On Wed, Oct 2, 2019 at 10:51 PM Jonathan Behrens wrote:
>
> This patch enables a debugger to read and write the current privilege level
> via
> a special "priv" register. When compiled with CONFIG_USER_ONLY the register is
> still visible but is hardwired to zero.
>
> Signed-off-by: Jonathan
+QEMU developers ML
On Thu, Oct 3, 2019 at 7:37 PM Waseem ALKurdi
wrote:
>
> Dear all,
>
> I'm trying to get mainline U-Boot to boot on mainline QEMU 4.1.0 for the
> 'sabrelite' board, using the configuration 'mx6qsabrelite_defconfig'.
>
> It's not booting at all. Actually, not a single U-Boot
Hi Palmer,
On Thu, Feb 13, 2020 at 1:30 AM Palmer Dabbelt wrote:
>
> The following changes since commit 81a23caf47956778c5a5056ad656d1ef92bf9659:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2020-02-10 17:08:51 +)
>
> are available in the Git
Hi Palmer,
On Mon, Feb 24, 2020 at 9:40 PM Bin Meng wrote:
>
>
> This series advances the roms/opensbi submodule to the v0.6 release,
> and builds and captures platform firmware binaries from that release.
>
> A 32-bit sifive_u bios image has also been added, so that we can
On Sun, Feb 2, 2020 at 9:44 PM Anup Patel wrote:
>
> Currently, TIME CSRs are emulated only for user-only mode. This
> patch add TIME CSRs emulation for privileged mode.
>
> For privileged mode, the TIME CSRs will return value provided
> by rdtime callback which is registered by QEMU
mber. When not given, the default serial number
> 1 is used.
>
> Suggested-by: Bin Meng
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_u.c | 8 +++-
> include/hw/riscv/sifive_u.h | 2 ++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> dif
On Wed, Mar 4, 2020 at 9:37 AM Alistair Francis
wrote:
>
> Split the file into clear machine and SoC sections.
>
Yep, I found functions in this file are a little bit confusing as well ..
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_u.c | 107
Hi Alistair,
On Thu, Mar 5, 2020 at 7:13 AM Alistair Francis wrote:
>
> On Wed, Mar 4, 2020 at 6:47 AM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Wed, Mar 4, 2020 at 9:37 AM Alistair Francis
> > wrote:
> > >
> > > At present
not given, the default serial number
> 1 is used.
>
> Suggested-by: Bin Meng
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_u.c | 8 +++-
> include/hw/riscv/sifive_u.h | 2 ++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Hi Alistair,
On Fri, Mar 6, 2020 at 12:53 AM Alistair Francis wrote:
>
> On Thu, Mar 5, 2020 at 1:31 AM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Thu, Mar 5, 2020 at 7:13 AM Alistair Francis
> > wrote:
> > >
> > > On Wed, Mar
Hi Alistair,
On Tue, Feb 25, 2020 at 5:14 AM Alistair Francis wrote:
>
> On Sun, Feb 16, 2020 at 5:56 AM Bin Meng wrote:
> >
> > At present the board serial number is hard-coded to 1, and passed
> > to OTP model during initialization. Firmware (FSBL, U-Boot) us
, it took 2 minutes 56 seconds to build
the docker image, and 1 minute 24 seconds to generate the
artifacts.zip with the firmware binaries (filesize: 111KiB).
See: https://gitlab.com/lbmeng/qemu/pipelines/120520138
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Bin Meng
---
Changes in v2
' machine.
Two GitLab CI jobs are added to build the OpenSBI firmware binaries.
Changes in v2:
- new patch: Upgrade opensbi from v0.5 to v0.6
- Update the 32-bit sifive_u bios image to OpenSBI v0.6
- new patch: Add GitLab jobs to build OpenSBI firmware binaries
Bin Meng (4):
roms: opensbi: Upgrade
machine. A pre-built
OpenSBI v0.6 image has been added as the default bios for 32-bit
sifive_u machine.
Signed-off-by: Bin Meng
---
Changes in v2:
- Update the 32-bit sifive_u bios image to OpenSBI v0.6
Makefile | 2 +-
pc-bios/opensbi-riscv32-sifive_u
_send_many()
ac5e821 include: Bump-up version to 0.6
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch: Upgrade opensbi from v0.5 to v0.6
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 40984 -> 41280 bytes
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 49160 -> 53760 bytes
Update BIOS_FILENAME to consider 32-bit bios image file name.
Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2: None
hw/riscv/sifive_u.c | 6
Hi Alistair,
On Tue, Mar 3, 2020 at 8:07 AM Alistair Francis wrote:
>
> On Mon, Feb 24, 2020 at 9:02 PM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Tue, Feb 25, 2020 at 5:14 AM Alistair Francis
> > wrote:
> > >
> >
t; > ...
> >
> > It turns out we should set pci_allow_0_address to true to allow 0
> > PCI address, otherwise pci_bar_address() treats such address as
> > PCI_BAR_UNMAPPED.
> >
> > Signed-off-by: Bin Meng
> > ---
> >
> > hw/riscv/virt.c
machine. A pre-built
OpenSBI image (built from commit 3e7d666) has been added as the
default bios for 32-bit sifive_u machine.
Signed-off-by: Bin Meng
---
Makefile | 2 +-
pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 0 -> 49472 bytes
roms/Makef
Update BIOS_FILENAME to consider 32-bit bios image file name.
Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion
Hi Philippe,
On Fri, Feb 21, 2020 at 1:31 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Bin,
>
> On 2/20/20 3:42 PM, Bin Meng wrote:
> > Although the real world SiFive HiFive Unleashed board is a 64-bit
> > hardware configuration, with QEMU it is possible to test 32-bit
> &g
at 10:38 AM Palmer Dabbelt
> >> wrote:
> >>>
> >>> On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng...@gmail.com wrote:
> >>> > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng wrote:
> >>> >>
> >>> >> At present the b
subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng
---
Changes in v2:
- Move setting OTP serial number pro
On Sat, Feb 22, 2020 at 3:51 AM Alistair Francis wrote:
>
> On Thu, Feb 20, 2020 at 6:43 AM Bin Meng wrote:
> >
> > Update BIOS_FILENAME to consider 32-bit bios image file name.
> >
> > Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
> > plus
Hi Philippe,
On Fri, Feb 21, 2020 at 4:54 PM Philippe Mathieu-Daudé
wrote:
>
> On 2/21/20 6:54 AM, Anup Patel wrote:
> > On Fri, Feb 21, 2020 at 8:08 AM Bin Meng wrote:
> >>
> >> Hi Philippe,
> >>
> >> On Fri, Feb 21, 2020 at 1:31 AM Philip
On Sun, Feb 16, 2020 at 9:55 PM Bin Meng wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. Whe
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