Fixed in:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=2c9498c3e44cd5574
** Changed in: qemu
Status: New => Fix Committed
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https://bugs.launchpad.net/bugs/1614521
Title:
Could not reproduce with:
qemu - v2.12.0-865-ge609fa7
host/guest kernel - 4.11
libvirt - 4.4.0
and
qemu - v2.12.0-865-ge609fa7
host kernel - v4.17-rc7-22-g3d661e2
guest kernel - 4.11
libvirt - 4.4.0
So I'd say that this is fixed by:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=0efc914
**
I was able to reproduce this with:
qemu - v2.12.0-813-g5a5c383
host/guest kernel - 4.11
libvirt - 3.9.0
It bisects to:
36c2f8b migration: Delay start of migration main routines
However, the issue did *not* reproduce with:
qemu - v2.12.0-865-ge609fa7
host/guest kernel - 4.11
libvirt - 3.9.0
I see this happening in ppc64le and x86_64 with QEMU
v2.11.0-1684-ga6e0344fa0. The keystrokes are being sent to tty1:
in x86_64:
./v2.11.0-1684-ga6e0344fa0/bin/qemu-system-x86_64 -enable-kvm -m 512
-kernel vmlinuz -initrd initramfs.img -chardev
serial,id=s1,path=/dev/pts/10 -mon chardev=s1 -qmp
** Changed in: qemu
Assignee: (unassigned) => Fabiano Rosas (farosas)
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https://bugs.launchpad.net/bugs/1726733
Title:
‘qemu-img info replication:’ causes segfault
Status in Q
': Unknown protocol 'quorum'
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
---
block/quorum.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/block/quorum.c b/block/quorum.c
index 14333c18aa..cfe484a945 100644
--- a/block/quorum.c
+++ b/block/quorum.c
@@ -1
** Changed in: qemu
Status: New => In Progress
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https://bugs.launchpad.net/bugs/1726733
Title:
‘qemu-img info replication:’ causes segfault
Status in QEMU:
In Progress
Bug
ntation was added to make the above more
explicit.
Fabiano Rosas (5):
block/replication: Remove protocol_name field
block/quorum: Remove protocol-related fields
block/throttle: Remove protocol-related fields
block/blkreplay: Remove protocol-related fields
include/block/block_int: D
'blkreplay:foo': Unknown protocol 'blkreplay'
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
---
block/blkreplay.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/block/blkreplay.c b/block/blkreplay.c
index 61e44a1949..fe5a9b4a98 100755
--- a/block/blkreplay.c
+++ b
gracefully:
$ qemu-img info replication:foo
qemu-img: Could not open 'replication:': Unknown protocol 'replication'
Buglink: https://bugs.launchpad.net/qemu/+bug/1726733
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
---
block/replication.c | 1 -
replication.h | 1 -
2
'throttle:foo': Unknown protocol 'throttle'
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
---
block/throttle.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/block/throttle.c b/block/throttle.c
index 5f4d43d0fc..95ed06acd8 100644
--- a/block/throttle.c
+++ b/block/thro
Clarify that for protocols the brdv_file_open function is used instead
of bdrv_open and that protocol_name is expected to be set.
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
---
include/block/block_int.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include
': Unknown protocol 'quorum'
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
Reviewed-by: Max Reitz <mre...@redhat.com>
---
block/quorum.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/block/quorum.c b/block/quorum.c
index 14333c18aa..cfe484a945 100644
that attempts to invoke this driver using protocol syntax
will fail gracefully:
$ qemu-img info replication:foo
qemu-img: Could not open 'replication:': Unknown protocol 'replication'
Buglink: https://bugs.launchpad.net/qemu/+bug/1726733
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
Re
ntation was added to make the above more
explicit.
v1 -> v2:
- patch 1: updated commit message
- patch 5: improved protocol_name documentation
https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg02998.html
Fabiano Rosas (5):
block/replication: Remove protocol_name field
block/quor
Clarify that:
- for protocols the brdv_file_open function is used instead
of bdrv_open;
- when protocol_name is set, a driver should expect
to be given only a filename and no other options.
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
---
include/block/block_int.h | 8 +
'throttle:foo': Unknown protocol 'throttle'
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
Reviewed-by: Max Reitz <mre...@redhat.com>
---
block/throttle.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/block/throttle.c b/block/throttle.c
index 5f4d43d0fc..95ed0
'blkreplay:foo': Unknown protocol 'blkreplay'
Signed-off-by: Fabiano Rosas <faro...@linux.vnet.ibm.com>
Reviewed-by: Pavel Dovgalyuk <pavel.dovga...@ispras.ru>
Reviewed-by: Max Reitz <mre...@redhat.com>
---
block/blkreplay.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
On 2018-03-12 10:50, Max Reitz wrote:
> A driver doesn't need to be a protocol driver for this, and technically
> a protocol driver doesn't need to set this. Maybe we should rename it
> to "filename_prefix"...?
Yes, something that is closer to the filename string and farther from
the notion of
** Changed in: qemu
Status: In Progress => Fix Committed
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https://bugs.launchpad.net/bugs/1726733
Title:
‘qemu-img info replication:’ causes segfault
Status in QEMU:
Fix
This is addressed by commit:
"f7d6bfc spapr_pci: fail gracefully with non-pseries machine types"
$ ./v2.11.0-1421-g7d84845/bin/qemu-system-ppc64 -S -machine ppce500,accel=tcg
-device spapr-pci-host-bridge
qemu-system-ppc64: -device spapr-pci-host-bridge: spapr-pci-host-bridge needs a
pseries
In the above, 12423 is the main process id and 12430 & 12431 are the
two vcpu threads.
(qemu) info cpus
* CPU #0: thread_id=12430
CPU #1: thread_id=12431
Suggested-by: Murilo Opsfelder Araujo
Signed-off-by: Fabiano Rosas
---
scripts/tracetool/backend/log.py | 2 +-
1 file changed, 1 inser
Alexey Kardashevskiy writes:
> Fabiano,
>
> Are you planning on reposting this any time soon? I am interested in the
> feature. Thanks.
Yes, I'm almost done with v3 of the series. Will probably send it later
this week.
Greg Kurz writes:
> On Tue, 15 Jan 2019 17:37:48 -0200
> Fabiano Rosas wrote:
>
>> A following patch will add support for handling the Special Purpose
>> Registers (SPR) in GDB via gdbstub. For that purpose, GDB needs to be
>> provided with an XML description of
2018-11/msg03738.html
Fabiano Rosas (7):
target/ppc: Move exception vector offset computation into a function
target/ppc: Add ppc_get_trace_int_handler_addr
kvm: support checking for single step capability
kvm-all: Introduce kvm_set_singlestep
target/ppc: Move handling of hard
This will allow architecture-specifc implementations of a fallback
mechanism for single stepping in cases where KVM does not support it
via the KVM_SET_GUEST_DEBUG ioctl.
Signed-off-by: Fabiano Rosas
---
accel/kvm/kvm-all.c | 9 +
accel/stubs/kvm-stub.c | 4
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0ec7ae1ad4..337a3ef8bb 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc
This is in preparation for a refactoring of the kvm_handle_debug
function in the next patch.
Signed-off-by: Fabiano Rosas
---
target/ppc/kvm.c | 47 ---
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc
the handling
of the Emulation Assist Interrupt (breakpoint).
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 5 ++
target/ppc/kvm.c | 180 +--
2 files changed, 178 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index
decide what to do for the platforms that do not have
such support.
Signed-off-by: Fabiano Rosas
---
accel/kvm/kvm-all.c | 7 +++
include/sysemu/kvm.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 4e1de942ce..0dc7a32883 100644
The upcoming single step functionality (KVM HV) needs to write to the
Trace Interrupt handler's address for its mechanism to work. The
address is calculated by applying an offset according to the value of
the Alternate Interrupt Location (AIL) bits in the LPCR register.
Signed-off-by: Fabiano
now to avoid hurting readability.
Signed-off-by: Fabiano Rosas
---
target/ppc/kvm.c | 86
1 file changed, 50 insertions(+), 36 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 96a5895792..c27190d7fb 100644
--- a/target/ppc/kvm.c
ion does that conversion.
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index ade06cc773..bbb468f38d 100644
--- a/target/
nd add comment explaining why
we need it
- patch 2: use gdb_id to find the correct env->spr array's index
https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg00648.html
Fabiano Rosas (3):
target/ppc: Add SPRs XML generation code for gdbstub
target/ppc: Add GDB callbacks
already defined in the machine. This eliminates the need for
several XML files to match each possible ppc machine.
A "group" is defined so that the GDB command `info registers spr` can
be used.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 8 +++
target/ppc/gdbs
This allows reading and writing of SPRs via GDB:
(gdb) p/x $srr1
$1 = 0x82803033
(gdb) p/x $pvr
$2 = 0x4b0201
(gdb) set $pvr=0x4b
(gdb) p/x $pvr
$3 = 0x4b
They can also be shown as a group:
(gdb) info reg spr
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c
atches build independently
https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg02939.html
Fabiano Rosas (3):
target/ppc: Add SPRs XML generation code for gdbstub
target/ppc: Add GDB callbacks for SPRs
target/ppc: Enable reporting of SPRs to GDB
target/ppc/cpu.h| 8 +
already defined in the machine. This eliminates the need for
several XML files to match each possible ppc machine.
A "group" is defined so that the GDB command `info registers spr` can
be used.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 8 +++
target/ppc/gdbs
Fabiano Rosas writes:
> These will be used to let GDB know about PPC's Special Purpose
> Registers (SPR).
>
> They take an index based on the order the registers appear in the XML
> file sent by QEMU to GDB. This index does not match the actual
> location of the registers in
ion does that conversion.
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c | 54 -
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index ade06cc773..9c6c935204 100
This allows reading and writing of SPRs via GDB:
(gdb) p/x $srr1
$1 = 0x82803033
(gdb) p/x $pvr
$2 = 0x4b0201
(gdb) set $pvr=0x4b
(gdb) p/x $pvr
$3 = 0x4b
They can also be shown as a group:
(gdb) info reg spr
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c
David Gibson writes:
>> --- a/target/ppc/kvm.c
>> +++ b/target/ppc/kvm.c
>> @@ -94,6 +94,7 @@ static int cap_ppc_safe_indirect_branch;
>> static int cap_ppc_nested_kvm_hv;
>>
>> static uint32_t debug_inst_opcode;
>> +static target_ulong trace_handler_addr;
>>
>> /* XXX We have a race
David Gibson writes:
>> >> +if (arch_info->address == trace_handler_addr) {
>> >> +cpu_synchronize_state(cs);
>> >> +kvm_remove_breakpoint(cs, trace_handler_addr, 4,
>> >> GDB_BREAKPOINT_SW);
>> >> +
>> >> +cpu_memory_rw_debug(cs, env->spr[SPR_SRR0] - 4, (uint8_t *),
userspace
program inside the guest with GDB.
I'm looking for feedback on the general approach before I develop this
further.
1- PowerISA Section 6.5.15 - Trace Interrupt
2- https://sourceware.org/gdb/onlinedocs/gdb/All_002dStop-Mode.html
Fabiano Rosas (1):
target/ppc: support single stepping w
.
This approach works with both of GDB's 'scheduler-locking' options
(off, step).
Signed-off-by: Fabiano Rosas
---
accel/kvm/kvm-all.c | 10 +++
exec.c | 1 +
include/sysemu/kvm.h | 4 +++
target/arm/kvm.c | 4 +++
target/i386/kvm.c| 4 +++
target/ppc/kvm.c | 65
David Gibson writes:
> On Wed, Nov 21, 2018 at 04:13:45PM -0200, Fabiano Rosas wrote:
>> The PowerISA prescribes that depending on the values of MSR_IR,
>> MSR_DR, MSR_HV and LPCR_AIL, the interrupt vectors might be relocated
>> by specific offsets.
>>
&
The PowerISA prescribes that depending on the values of MSR_IR,
MSR_DR, MSR_HV and LPCR_AIL, the interrupt vectors might be relocated
by specific offsets.
This patch defines macros for these offsets so that they can be used
by another part of the code in a future patch.
Signed-off-by: Fabiano
review
- use extract32 for decoding instruction instead of open-coding
- add more people to CC
https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg03738.html
Fabiano Rosas (3):
target/ppc: Add macro definitions for relocated interrupt vectors
offsets
kvm-all: Introduce kvm_s
.
This approach works with both of GDB's 'scheduler-locking' options
(off, step).
Signed-off-by: Fabiano Rosas
---
target/ppc/kvm.c | 61 +++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 9d0b4f1f3f
This will be used in a future patch to implement an
architecture-specific single step mechanism for POWER.
Signed-off-by: Fabiano Rosas
---
accel/kvm/kvm-all.c | 10 ++
exec.c | 1 +
include/sysemu/kvm.h | 4
target/arm/kvm.c | 4
target/i386/kvm.c
ion does that conversion.
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c | 50 +
1 file changed, 50 insertions(+)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 03f1d34a97..f10a3637d9 100644
--- a/target/
This allows reading and writing of SPRs via GDB:
(gdb) p/x $srr1
$1 = 0x82803033
(gdb) p/x $pvr
$2 = 0x4b0201
(gdb) set $pvr=0x4b
(gdb) p/x $pvr
$3 = 0x4b
They can also be shown as a group:
(gdb) info reg spr
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c
->spr array.
The second patch implements the gdb_{get,set}_spr_reg callbacks along
with the convertion from GDB index to QEMU index.
The third patch enables the functionality.
1- https://sourceware.org/gdb/current/onlinedocs/gdb/Target-Descriptions.html
Fabiano Rosas (3):
target/ppc: Add S
already defined in the machine. This eliminates the need for
several XML files to match each possible ppc machine.
A "group" is defined so that the GDB command `info registers spr` can
be used.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 7 +++
target/ppc/gdbs
This allows reading and writing of SPRs via GDB:
(gdb) p/x $srr1
$1 = 0x82803033
(gdb) p/x $pvr
$2 = 0x4b0201
(gdb) set $pvr=0x4b
(gdb) p/x $pvr
$3 = 0x4b
They can also be shown as a group:
(gdb) info reg spr
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c
already defined in the machine. This eliminates the need for
several XML files to match each possible ppc machine.
A "group" is defined so that the GDB command `info registers spr` can
be used.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu-qom.h| 4 +++
target
atches build independently
https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg02939.html
v3 -> v4:
- patch 1: move gdb_spr_xml into PowerPCCPUClass so that it is
generated only once for all CPUs
http://lists.nongnu.org/archive/html/qemu-ppc/2019-01/msg00357.html
Fabiano Rosas (3):
ion does that conversion.
Signed-off-by: Fabiano Rosas
---
target/ppc/translate_init.inc.c | 54 -
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 710064a25d..f29ac3558a 100
Aravinda Prasad writes:
(...)
> diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
> index df5e85f..cf7b24f 100644
> --- a/target/ppc/kvm_ppc.h
> +++ b/target/ppc/kvm_ppc.h
> @@ -27,6 +27,7 @@ void kvmppc_enable_h_page_init(void);
> void kvmppc_set_papr(PowerPCCPU *cpu);
> int
This is in preparation for a refactoring of the kvm_handle_debug
function in the next patch.
Signed-off-by: Fabiano Rosas
---
target/ppc/kvm.c | 47 ---
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc
Signed-off-by: Fabiano Rosas
Reviewed-by: Alexey Kardashevskiy
---
target/ppc/excp_helper.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 39bedbb11d..beafcf1ebd 100644
--- a/target
arch_info->address directly into functions that only
need the address;
improve indentation by returning early when possible.
https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg04627.html
Fabiano Rosas (5):
target/ppc: Move exception vector offset computation int
now to avoid hurting readability.
Signed-off-by: Fabiano Rosas
Reviewed-by: Alexey Kardashevskiy
---
target/ppc/kvm.c | 86
1 file changed, 50 insertions(+), 36 deletions(-)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 941c4e7523
the handling
of the Emulation Assist Interrupt (breakpoint).
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 16
target/ppc/excp_helper.c | 13 +++
target/ppc/gdbstub.c | 35 +++
target/ppc/kvm.c | 195 +--
4 files changed, 252
decide what to do for the platforms that do not have
such support.
This will allow architecture-specific implementations of a fallback
mechanism for single stepping in cases where KVM does not support it.
Signed-off-by: Fabiano Rosas
---
accel/kvm/kvm-all.c | 16
David Gibson writes:
>> +/* Whether the KVM_SET_GUEST_DEBUG ioctl supports single stepping */
>> +int kvm_has_guestdbg_singlestep(void)
>> +{
>> +/* return kvm_check_extension(kvm_state, KVM_CAP_GUEST_DEBUG_SSTEP); */
>
> I don't see a KVM_CAP_GUEST_DEBUG_SSTEP in either the qemu or kernel
>
David Gibson writes:
>> +/* Whether the KVM_SET_GUEST_DEBUG ioctl supports single stepping */
>> +int kvm_has_guestdbg_singlestep(void)
>> +{
>> +/* return kvm_check_extension(kvm_state, KVM_CAP_GUEST_DEBUG_SSTEP); */
>
> I don't see a KVM_CAP_GUEST_DEBUG_SSTEP in either the qemu or kernel
>
Alexey Kardashevskiy writes:
> Looks good to me, does not break what already works. However I cannot
> debug SLOF real mode and I am not sure why.
>
> (gdb) set endian big
>
> The target is assumed to be big endian
> (gdb) b *0x3f00
>
> Breakpoint 2 at 0x3f00
I think I'm missing the point here.
ate
Regarding the endianness discussion, continue providing the registers
in the target endianness as GBD currently requires this.
http://lists.nongnu.org/archive/html/qemu-ppc/2019-01/msg00498.html
Fabiano Rosas (1):
target/ppc: Enable reporting of SPRs to GDB
target/ppc/cpu-qom.h
tly needs to know the guest endianness in order to
properly print the registers values. This is done automatically by GDB
when provided with the ELF file or explicitly with the `set endian
` command.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu-qom.h| 4 +++
target/ppc/cp
structures (see
"chunk" in https://sourceware.org/glibc/wiki/MallocInternals)
The following error is seen while trying to free int_buf:
"free(): invalid next size (fast)"
Fixes: a324d6f166 "spapr: Support ibm,dynamic-memory-v2 property"
Signed-off-by: Fabiano
David Gibson writes:
> On Thu, Jan 24, 2019 at 06:20:02PM +1100, Alexey Kardashevskiy wrote:
>>
>>
>> On 23/01/2019 04:01, Fabiano Rosas wrote:
>> > These will be used to let GDB know about PPC's Special Purpose
>> > Registers (SPR).
>>
Alexey Kardashevskiy writes:
>
> but this is a register which does not have endianness, the endianness
> appears here because the interface between gdb and qemu is
> uint8_t*==bytestream but this interface should have fixed endianness
> imho (now it is bigendian afaict).
>
> Something is not
Alexey Kardashevskiy writes:
> On 31/01/2019 03:30, Fabiano Rosas wrote:
>> Alexey Kardashevskiy writes:
>>
>>>
>>> but this is a register which does not have endianness, the endianness
>>> appears here because the interface between gdb and qemu is
&
Alexey Kardashevskiy writes:
> On 01/02/2019 08:57, Fabiano Rosas wrote:
>> Alexey Kardashevskiy writes:
>>
>>> On 31/01/2019 03:30, Fabiano Rosas wrote:
>>>> Alexey Kardashevskiy writes:
>>>>
>>>>>
>>>>> but this i
er that would only
happen with more than one VCPU and if 'show scheduler-locking' in GDB is
'off'. And even then, that should not cause any issues, but it is a more
complex scenario so there could be a bug in the code.
> On 20/03/2019 12:42, Alexey Kardashevskiy wrote:
>>
>&g
This is a left-over from "f4ec5e26ed vfio: Add host side DMA window
capabilities", which added support to more than one DMA window.
Signed-off-by: Fabiano Rosas
---
include/hw/vfio/vfio-common.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/include/hw/vfio/vfio-common.h b/
Alexey Kardashevskiy writes:
> It is TCG, a single CPU with a single thread and no matter where I put
Ok, but then none of this code gets executed because it is kvm-only:
qemu/exec.c
void cpu_single_step(CPUState *cpu, int enabled)
{
if (cpu->singlestep_enabled != enabled) {
Shivaprasad G Bhat writes:
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 6c16d2b120..b6e7d04dcf 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -3,11 +3,13 @@
> #include "sysemu/hw_accel.h"
> #include "sysemu/sysemu.h"
> #include "qemu/log.h"
>
Shivaprasad G Bhat writes:
> +/* Create DT entries for cold plugged NVDIMM devices */
> +dimms = nvdimm_get_device_list();
> +for (; dimms; dimms = dimms->next) {
> +NVDIMMDevice *nvdimm = dimms->data;
> +
> +spapr_populate_nvdimm_node(fdt, offset, nvdimm);
> +}
>
Fabiano Rosas writes:
>> +nvdimm = NVDIMM(drc->dev);
>> +if ((offset + numBytesToRead < offset) ||
>> +(nvdimm->label_size < numBytesToRead + offset)) {
>> +return H_P2;
>> +}
>
> Won't the first clause always be fals
Aravinda Prasad writes:
> +/*
> + * Properly set bits in MSR before we invoke the handler.
> + * SRR0/1, DAR and DSISR are properly set by KVM
> + */
> +if (!(*pcc->interrupts_big_endian)(cpu)) {
> +msr |= (1ULL << MSR_LE);
> +}
> +
> +if (env->msr && (1ULL <<
David Gibson writes:
Hi, thanks for the review! My comments below:
> On Wed, Dec 11, 2019 at 04:10:13PM -0300, Fabiano Rosas wrote:
>> The hardware singlestep mechanism in POWER works via a Trace Interrupt
>> (0xd00) that happens after any instruction executes, whenever MSR_SE =
David Gibson writes:
> On Wed, Dec 11, 2019 at 04:10:12PM -0300, Fabiano Rosas wrote:
>> For single stepping (via KVM) of a guest vcpu to work, KVM needs not
>> only to support the SET_GUEST_DEBUG ioctl but to also recognize the
>> KVM_GUESTDBG_SINGLESTEP bit
David Gibson writes:
> On Wed, Dec 11, 2019 at 04:10:11PM -0300, Fabiano Rosas wrote:
>> Signed-off-by: Fabiano Rosas
>
> Generally, imported linux header updates are done as a block, pulling
> qemu up to a specified kernel commit id, rather than just grabbing
> pieces for
|= ppc_excp_vector_offset(cs, ail);
}
Fixes: 2586a4d7a0 ("target/ppc: Move exception vector offset computation into a
function")
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/excp_helper.c b/
decide what to do for the platforms that do not have
such support.
This will allow architecture-specific implementations of a fallback
mechanism for single stepping in cases where KVM does not support it.
Signed-off-by: Fabiano Rosas
---
accel/kvm/kvm-all.c | 14 ++
accel
the handling
of the Emulation Assist Interrupt (breakpoint).
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 16
target/ppc/excp_helper.c | 13 +++
target/ppc/gdbstub.c | 35 +++
target/ppc/kvm.c | 195 +--
4 files changed, 252
Signed-off-by: Fabiano Rosas
---
linux-headers/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 3d9b18f7f8..488f3baf01 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -1000,6 +1000,7 @@ struct
2018-11/msg04269.html
v1:
https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg03738.html
Fabiano Rosas (3):
linux-headers: Update kvm.h for ppc single step capability
kvm-all: Introduce kvm_set_singlestep
target/ppc: support single stepping with KVM HV
accel/kvm/kvm-all.c |
://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fb5924fd
Signed-off-by: Fabiano Rosas
---
hw/virtio/vhost-user-fs.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/hw/virtio/vhost-user-fs.c b/hw/virtio/vhost-user-fs.c
index 455e97beea
They were added in "16415335be Use correct input constant" with a
single use in kvm_arch_pre_run but that function's implementation was
removed by "1e8f51e856 ppc: remove idle_timer logic".
Signed-off-by: Fabiano Rosas
---
target/ppc/kvm.c | 6 --
1 file changed, 6 dele
> This uses the existing kernel address by default.
>
> Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Fabiano Rosas
> ---
> include/hw/ppc/spapr.h | 1 +
> hw/ppc/spapr.c | 38 +++---
> 2 files changed, 32 insertions(+), 7 deletio
ral change.
>
> Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Fabiano Rosas
> ---
> include/hw/ppc/spapr_cpu_core.h | 4 +++-
> hw/ppc/spapr.c | 4 ++--
> hw/ppc/spapr_cpu_core.c | 7 ++-
> hw/ppc/spapr_rtas.c | 2 +-
> 4 f
4_set_isi().. but not in
> other places that we blindly check LPCR[VPM0].
>
> Correct those instances with a new helper to tell if we should be in VRMA
> mode.
>
> Signed-off-by: David Gibson
> Reviewed-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
> ---
> target/pp
SLBE directly from the LPCR when we need it.
>
> Signed-off-by: David Gibson
Reviewed-by: Fabiano Rosas
> ---
> target/ppc/cpu.h| 3 ---
> target/ppc/mmu-hash64.c | 28 ++--
> 2 files changed, 6 insertions(+), 25 deletions(-)
>
> diff --git a/t
David Gibson writes:
> When running guests under a hypervisor, the hypervisor obviously needs to
> be protected from guest accesses even if those are in what the guest
> considers real mode (translation off). The POWER hardware provides two
> ways of doing that: The old way has guest real mode
David Gibson writes:
Hi, just a nitpick, feel free to ignore.
> When in VRMA mode (i.e. a guest thinks it has the MMU off, but the
> hypervisor is still applying translation) we use a special SLB entry,
> rather than looking up an SLBE by address as we do when guest translation
> is on.
>
> We
t
> for 32-bit hypervisor mode 13 years later. Let's stop pretending and just
> remove the stubs.
>
> Signed-off-by: David Gibson
Reviewed-by: Fabiano Rosas
> ---
> target/ppc/cpu.h| 21 +++--
> target/ppc/translate_init.inc.c | 6 +
Since there is no vdso, the Go code goes into the syscall fallback:
MOVDruntime·vdsoClockgettimeSym(SB), R12// Check for VDSO availability
CMP R12, R0
BEQ fallback
(...)
fallback:
ADD $32, R1, R4
SYSCALL $SYS_clock_gettime
MOVD32(R1), R3
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