Fabiano Rosas writes:
> QEMU reports MMU support to the guest via the ibm,architecture-vec-5
> property of the /chosen node. Byte number 26 specifies Radix Table
> Expansions, currently only GTSE (Guest Translation Shootdown
> Enable). This feature determines whether the tlbie
rgs.memory)
File "./scripts/analyze-migration.py", line 539, in read
classdesc = self.section_classes[section_key]
KeyError: ('spapr_iommu', -2147483648)
Signed-off-by: Fabiano Rosas
---
scripts/analyze-migration.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --g
These two were not migrated so the remote end was starting with the
decrementer expired.
I am seeing less frequent crashes with this patch (tested with -smp 4
and -smp 32). It certainly doesn't fix all issues but it looks like it
helps.
Signed-off-by: Fabiano Rosas
---
target/ppc/machine.c
if anyone spots something right
away. I haven't made much progress in debugging the general TCG
migration case so if anyone has any input there as well I'd appreciate
it.
Thanks
Fabiano Rosas (4):
target/ppc: TCG: Migrate tb_offset and decr
spapr: TCG: Migrate spapr_cpu->prod
hw/ppc: T
I'm seeing some stack traces in the migrated guest going through cede
and some hangs at the plpar_hcall_norets so let's make sure everything
related to cede/prod is being migrated just in case.
Signed-off-by: Fabiano Rosas
---
hw/ppc/spapr_cpu_core.c | 1 +
include/hw/ppc
This adds migration support for TCG pseries machines running a KVM-HV
guest.
The state that needs to be migrated is:
- the nested PTCR value;
- the in_nested flag;
- the nested_tb_offset.
- the saved host CPUPPCState structure;
Signed-off-by: Fabiano Rosas
---
(this migrates just fine with L2
When saving the guest "timebase" we look to the first_cpu for its
tb_offset. If that CPU happens to be running a nested guest at this
time, the tb_offset will have the nested guest value.
This was caught by code inspection.
Signed-off-by: Fabiano Rosas
---
hw/ppc/
ing to decouple SPR creation and TCG callback
registration any time soon, so let's rename the header to spr_common
to accomodate the register_*_sprs functions that will be moved out of
cpu_init.c in the following patches.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_init.c
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 68 +++
1 file changed, 11 insertions(+), 57 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 131c2da4c2..ea4ed19bde 100644
--- a/target/ppc
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 43 ---
1 file changed, 24 insertions(+), 19 deletions
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1eef006a04..330b765ba9 100644
--- a/target/ppc/cpu_init.c
+++ b
to take in the future to implement these? Are they only
informative?
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 582 ++
1 file changed, 253 insertions(+), 329 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 41 ++---
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 330b765ba9..29f25e093f 100644
--- a/target/ppc
Now that the 601 was removed, all of our CPUs have a timebase, so that
can be moved into the common function.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 98 ---
1 file changed, 18 insertions(+), 80 deletions
The top level init_proc calls register_generic_sprs but also registers
some other SPRs outside of that function. Let's group everything into
a single place.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 58 ---
1 file
This is just to have 755-specific registers contained into a function,
intead of leaving them open-coded in init_proc_755. It makes init_proc
easier to read and keeps later patches that touch this code a bit
cleaner.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc
This function registers just one SPR and has only two callers, so open
code it.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc
-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 50 ---
1 file changed, 19 insertions(+), 31 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c54f10cb48..131c2da4c2 100644
--- a/target/ppc/cpu_init.c
+++ b
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 975257c19b..638e16c583 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc
The important part of this function is that it applies to non-embedded
CPUs, not that it also applies to the 601. We removed support for the
601 anyway, so rename this function.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 41
register_thrm_sprs | 8 callers
register_usprgh_sprs | 6 callers
register_6xx_7xx_soft_tlb | only 3 callers, but it helps to
keep the soft TLB code consistent.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 14
David Gibson writes:
> On Tue, Feb 15, 2022 at 06:41:47PM -0300, Fabiano Rosas wrote:
>> These will need to be accessed from other files once we move the CPUs
>> code to separate files.
>>
>> Signed-off-by: Fabiano Rosas
>> -
David Gibson writes:
> On Tue, Feb 15, 2022 at 06:41:43PM -0300, Fabiano Rosas wrote:
>> The important part of this function is that it applies to non-embedded
>> CPUs, not that it also applies to the 601. We removed support for the
>> 601 anyway, so rename this functi
Let's leave cpu_init with just generic CPU initialization and
QOM-related functions.
The rest of the SPR registration functions will be moved in the
following patches along with the code that uses them. These are only
the commonly used ones.
Signed-off-by: Fabiano Rosas
Reviewed-by: David
Put the SPR registration macros in a header that is accessible outside
of cpu_init.c. The following patches will move CPU-specific code to
separate files and will need to access it.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 65
The init_proc_755 function is identical to the 745 one except for the
755-specific registers. I think it is worth it to make them share
code.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 711834a4c1..cae4ab69fe 100644
--- a/target/ppc/cpu_init.c
+++ b
We're considering these two to be from different CPU families, so
duplicate some code to keep them separate.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 107 +++---
1 file changed, 91 insertions(+), 16 deletions
These will need to be accessed from other files once we move the CPUs
code to separate files.
The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
moved to a header so I'll deal with them later when splitting this
code between the multiple CPU families.
Signed-off-by: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index cae4ab69fe..c54f10cb48 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc
init_proc_603 is defined after init_proc_e300, so I had to move some
code around to make it work.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 104 +++---
1 file changed, 46 insertions(+), 58 deletions(-)
diff --git
with
in the next series;
- Added a new patch to rename spr_tcg to spr_common.
Patches 23 and 26 still need review.
This series is based on legoater/ppc7.0.
v1:
https://lists.nongnu.org/archive/html/qemu-ppc/2022-02/msg00313.html
Fabiano Rosas (27):
target/ppc: cpu_init: Remove not implemented comments
We're considering these two to be in different CPU families (6xx and
7xx), so keep their SPR registration separate.
The code was copied into register_G2_sprs and the common function was
renamed to apply only to the 755.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc
Move some of the 440 registers that are being repeated in the 440*
CPUs to register_440_sprs.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 100 +++---
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 64 +++
1 file changed, 35 insertions(+), 29 deletions
The G2LE CPU initialization code is the same as the G2. Use the latter
for both.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
---
target/ppc/cpu_init.c | 42 +-
1 file changed, 1 insertion(+), 41 deletions(-)
diff --git a/target/ppc/cpu_init.c
Make sure that every register_*_sprs function only has calls to
spr_register* to register individual SPRs. Do not allow nesting. This
makes the code easier to follow and a look at init_proc_* should
suffice to know what SPRs a CPU has.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Mark Cave-Ayland writes:
> On 24/02/2022 18:58, Fabiano Rosas wrote:
>
>> This series implements the migration for a TCG pseries guest running a
>> nested KVM guest. This is just like migrating a pseries TCG guest, but
>> with some extra state to allow a nested
David Gibson writes:
> On Thu, Feb 24, 2022 at 03:58:15PM -0300, Fabiano Rosas wrote:
>> I'm seeing some stack traces in the migrated guest going through cede
>> and some hangs at the plpar_hcall_norets so let's make sure everything
>> related to cede/prod is being
David Gibson writes:
> On Thu, Feb 24, 2022 at 03:58:16PM -0300, Fabiano Rosas wrote:
>> When saving the guest "timebase" we look to the first_cpu for its
>> tb_offset. If that CPU happens to be running a nested guest at this
>> time, the tb_offset w
David Gibson writes:
> On Thu, Feb 24, 2022 at 03:58:14PM -0300, Fabiano Rosas wrote:
>> These two were not migrated so the remote end was starting with the
>> decrementer expired.
>>
>> I am seeing less frequent crashes with this patch (tested with -smp 4
>> a
Daniel Henrique Barboza writes:
> On 2/15/22 15:33, Cédric Le Goater wrote:
>> On 2/15/22 04:16, Nicholas Piggin wrote:
>>> Here is the rollup of patches in much better shape since the RFC.
>>> I include the 2 first ones unchanged from independent submission
>>> just to be clear that this series
Take powerpc_reset_wakeup and ppc_excp_apply_ail along because these
are specific to BookS as well.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_books.c | 525 +-
target/ppc/excp_helper.c | 531
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_booke.c | 216 ++-
target/ppc/excp_helper.c | 204
3 files changed, 216 insertions(+), 205 deletions(-)
diff --git a/target/ppc/cpu.h b
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_7xx.c | 193 ++-
target/ppc/excp_helper.c | 181
3 files changed, 193 insertions(+), 182 deletions(-)
diff --git a/target/ppc/cpu.h b
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 2 +
target/ppc/cpu_6xx.c | 188 ++-
target/ppc/excp_helper.c | 177 +---
3 files changed, 190 insertions(+), 177 deletions(-)
diff --git a/target/ppc/cpu.h b
Part of our exception logging is using qemu_log_mask and part is using
trace-events. Move the remaining users of '-d int' to the trace-events
infrastructure.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 9 ++---
target/ppc/misc_helper.c | 4 ++--
target/ppc/trace-events | 2
BALATON Zoltan writes:
> On Tue, 1 Mar 2022, Fabiano Rosas wrote:
>> Affects the 405 CPU.
>>
>> This moves init_proc, init_excp and register_*sprs functions that are
>> related to the 40x CPUs (currently only 405) into a separate file.
>>
>> Signed-off-
This replaces the old dump_syscall qemu_log print with a
tracepoint. One immediate effect of this is that we can now avoid
flooding the console with syscall prints when debugging.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 53 ++--
target/ppc
Affects the 405 CPU.
This moves init_proc, init_excp and register_*sprs functions that are
related to the 40x CPUs (currently only 405) into a separate file.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_40x.c | 263 +
target/ppc/cpu_init.c | 250
but we're close to having
only TCG-specific code in it, as the file name implies. I left this
for the next series.
Based on legoater/ppc-7.0
Fabiano Rosas (17):
target/ppc: Add a tracepoint for System Calls
target/ppc: Use trace-events instead of CPU_LOG_INT
target/ppc: Move 40x CPUs code
copying check_pow_hid0 instead of moving it to avoid having to
keep it exposed in a header file;
- I'm also copying vscr_init to avoid having to include
fpu/softfloat.h (due to set_float_rounding_mode) from elsewhere.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_74xx.c | 1167
that comes from linux-headers kvm.h;
- I'm copying check_pow_hid0 instead of moving it to avoid having to
keep it exposed in a header file.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_7xx.c | 896 +
target/ppc/cpu_init.c | 873
in a header file;
- Differently from the previous files, this one contains both 32-bit
and 64-bit code.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_booke.c | 1422
target/ppc/cpu_init.c | 1410 ---
target/ppc
-headers kvm.h;
- I'm copying check_pow_hid0 instead of moving it to avoid having to
keep it exposed in a header file.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_6xx.c | 1146
target/ppc/cpu_init.c | 1129
The next patches will move the powerpc_excp_foo functions into the
proper cpu_foo.c files. This patch makes visible some functions that
are common to all of them.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 5 +
target/ppc/excp_helper.c | 8
2 files changed, 9
intialization. These
are all specific to BookS.
The BookS CPUs are all 64-bits so this new file goes under the
TARGET_PPC64 config.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_books.c | 1770
target/ppc/cpu_init.c | 1761
of simplifying the
init_excp/powerpc_excp relationship since both users of the
POWERPC_EXCP vector addresses are now in the same place.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_40x.c | 150 ++-
target/ppc/excp_helper.c
The defines are not in use and the comment seems to have lost its
purpose, whatever it was.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu_init.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index
Now that all the powerpc_excp* functions are in their appropriate C
files, we can drop the excp_model switch and just use a QOM class
method.
This will allow us to remove the excp_model enum once we've figured
out the last two remaining usages outside of excp_helper.c
Signed-off-by: Fabiano
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_74xx.c| 185 ++-
target/ppc/excp_helper.c | 173
3 files changed, 185 insertions(+), 174 deletions(-)
diff --git a/target/ppc/cpu.h b
Howard Spoelstra writes:
> On Wed, Mar 2, 2022 at 9:11 PM BALATON Zoltan wrote:
>
>> On Wed, 2 Mar 2022, Howard Spoelstra wrote:
>> > Hi all,
>> >
>> > I noticed qemu-system-ppc running OSX guests does not get to the desktop
>> or
>> > does not display the menu bars.
>>
>> Cc-ing the relevant
Nicholas Piggin writes:
> Use KVM_CAP_PPC_AIL_MODE_3 to determine cap-ail-mode-3 support for KVM
> guests. Keep the fallback heuristic for KVM hosts that pre-date this
> CAP.
>
> This is only proposed the KVM CAP has not yet been allocated. I will
> ask to merge the new KVM cap when there are no
Nicholas Piggin writes:
> The spapr virtual hypervisor does not require the hdecr timer.
Why is that? Is this not needed for an emulated powernv running KVM
guests?
> Remove it.
>
> Signed-off-by: Nicholas Piggin
> ---
> hw/ppc/ppc.c| 2 +-
> hw/ppc/spapr_cpu_core.c | 6 +++---
>
Nicholas Piggin writes:
> This implements the nested-hv hcall API for spapr under TCG.
> It's still a bit rough around the edges, concept seems to work.
>
> Some HV exceptions can be raised now in the TCG spapr machine when
> running a nested guest. The main ones are the lev==1 syscall, the
>
Nicholas Piggin writes:
> Invalid or missing partition table entry exceptions should cause HV
> interrupts. HDSISR is set to bad MMU config, which is consistent with
> the ISA and experimentally matches what POWER9 generates.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by
Leandro Lupori writes:
> From: Cédric Le Goater
>
> Check the HID0 bit to send signal, currently modeled as a checkstop.
> The QEMU implementation adds an exit using the GPR[3] value (that's a
> hack for tests)
>
> Signed-off-by: Cédric Le Goater
> Signed-off-by: Leandro Lupori
> ---
>
These are the spapr virtual hypervisor implementation of the nested
KVM API. They only make sense when running with TCG.
Signed-off-by: Fabiano Rosas
---
hw/ppc/spapr_hcall.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b
the hypercall_register_*
functions closer;
- Dropped the more paranoid patch that checked for KVM at every
call. I couldn't convince myself anymore that it was necessary.
v1:
https://lists.nongnu.org/archive/html/qemu-ppc/2022-03/msg00412.html
Fabiano Rosas (2):
spapr: Move
I'm moving this because next patch will add more code under the ifdef
and it will be cleaner if we keep them together.
Also switch the ifdef branches to make it more convenient to add code
under CONFIG_TCG in the next patch.
Signed-off-by: Fabiano Rosas
---
hw/ppc/spapr_hcall.c | 50
:
kvm_handle_papr_hcall 0x3a8
kvm_handle_papr_hcall 0x3ac
kvm_handle_papr_hcall 0x108
kvm_handle_papr_hcall 0x104
kvm_handle_papr_hcall 0x104
kvm_handle_papr_hcall 0x108
Signed-off-by: Fabiano Rosas
---
target/ppc/kvm.c| 2 +-
target/ppc/trace-events | 2 +-
2 files changed, 2
Richard Henderson writes:
> On 3/24/22 13:08, Leandro Lupori wrote:
>> To be able to finish the test and return an exit code to the
>> calling process, the Processor Attention instruction is used.
>> As its behavior is implementation dependent, in QEMU PowerNV
>> it just calls exit with GPR[3]
"Aneesh Kumar K.V" writes:
> David Gibson writes:
>
>> On Mon, Mar 14, 2022 at 07:10:10PM -0300, Fabiano Rosas wrote:
>>> David Gibson writes:
>>>
>>> > On Tue, Mar 08, 2022 at 10:23:59PM -0300, Fabiano Rosas wrote:
>>>
s://gitlab.com/qemu-project/qemu/-/issues/588
>
> Signed-off-by: Matheus Ferst
This patch seems to do the right thing. So:
Reviewed-by: Fabiano Rosas
Now, I'm not sure if the code around it does the right thing. =)
Specifically the else blocks (read_cb == NULL) and (write_cb =
The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc
There's no MSR_HV in the 6xx CPUs.
Also remove the 40x and BookE code.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 24
1 file changed, 24 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e27e1c3c70..734170d4c2 100644
There's no Hypervisor mode in the 6xx, so remove all LPES0 logic.
Also remove BookE IRQ code.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 37 -
1 file changed, 37 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
This code applies only to the 6xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 31 +++
1 file changed, 11 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
worried because
these 32 bit CPUs are quite similar to one another.
Fabiano Rosas (11):
target/ppc: Merge exception model IDs for 6xx CPUs
target/ppc: Introduce powerpc_excp_6xx
target/ppc: Simplify powerpc_excp_6xx
target/ppc: 6xx: Critical exception cleanup
target/ppc: 6xx: Machine
There's no ESR in the 6xx CPUs.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a008115e5f..a195288dda 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
This only applies to the G2s, the other 6xx CPUs will not have this
vector registered.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d855a275ca..e27e1c3c70
POWERPC_EXCP_MEXTBR
POWERPC_EXCP_NMEXTBR
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_TRACE
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 163 +++
1 file changed, 9 insertions(+), 154 deletions(-)
diff --git
u"
> Cc: Laurent Vivier
> Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
Introduce a new powerpc_excp function specific for PowerPC 6xx CPUs
(603, 604, G2, MPC5xx, MCP8xx). This commit copies powerpc_excp_legacy
verbatim so the next one has a clean diff.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 469 +++
1 file
There is no MSR_HV in the 7xx so remove the LPES0 handling.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 37 -
1 file changed, 37 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 4996b96616..5e2c2aa544 100644
There's no MSR_HV in the 7xx.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 24
1 file changed, 24 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 358c3f6206..4996b96616 100644
There is no Hypervisor mode in the 6xx CPUs.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a195288dda..28d9a9a887 100644
--- a/target
The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc
We don't need three separate exception model IDs for the 603, 604 and
G2.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu-qom.h | 8 ++--
target/ppc/cpu_init.c| 18 +-
target/ppc/excp_helper.c | 5 ++---
3 files changed, 13 insertions(+), 18 deletions(-)
diff
Since we've split the exception code by exception model, the exception
model IDs are becoming less useful. These two can be merged.
Signed-off-by: Fabiano Rosas
---
target/ppc/cpu-qom.h | 6 ++
target/ppc/cpu_init.c| 16
target/ppc/excp_helper.c | 2 +-
3 files
There's no ESR in the 7xx.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 5e2c2aa544..8f810f7de5 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs
(740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies
powerpc_excp_legacy verbatim so the next one has a clean diff.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 469
Thre is no HV support in the 7xx.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0bb577b75d..f29f2ecefb 100644
--- a/target/ppc
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 185 ++-
1 file changed, 9 insertions(+), 176 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index df96f620b2..358c3f6206 100644
There is no HV support in the 6xx.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 28d9a9a887..538905c4dd 100644
--- a/target/ppc
This code applies only to the 7xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 26 ++
1 file changed, 6 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index
There is no Hypervisor mode in the 7xx, so no hypercalls.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 21 ++---
1 file changed, 2 insertions(+), 19 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 8f810f7de5..0bb577b75d 100644
This series handles the 7xx family: 740, 745, 750, 750cl, 750cx,
750fx, 750gx and 755.
Fabiano Rosas (10):
target/ppc: Merge 7x5 and 7x0 exception model IDs
target/ppc: Introduce powerpc_excp_7xx
target/ppc: Simplify powerpc_excp_7xx
target/ppc: 7xx: Machine Check exception cleanup
BALATON Zoltan writes:
> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>> This code applies only to the 6xx CPUs, so we can remove the switch
>> statement.
>>
>> Signed-off-by: Fabiano Rosas
>> ---
>> target/ppc/excp_helper.c | 31 +++--
Cédric Le Goater writes:
> On 2/3/22 21:09, Fabiano Rosas wrote:
>
>> This series handles the 6xx family: 603, 604, G2, G2LE,
>
> What about the e300 ? I guess it's only a 603 variant for QEMU.
I forgot to mention.
>> MPC5xx and MPC8xx.
>
> These are linux-use
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