Hi:
Does anybody here have read the network simulation code in qemu and have a
knowledge of how it works and connected to the host network? And how network
tap works in qemu?
so the bugs this
> fixes don't actually affect anything. Previously the offset didn't
> take into account that the write_msk etc are 4 byte fields.
>
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> --
> v3:
> New patch to separate this out from the addition of HDM
udé
> Signed-off-by: Jonathan Cameron
> ---
LGTM. Only one minor comment inline.
Reviewed-by: Fan Ni
> v3: No changes, picked up tags.
> v2: Thanks to Philippe Mathieu-Daudé
> - Expand both enc() and dec() functions to include full set of values
>defined in CXL r3.0
On Mon, Sep 11, 2023 at 12:43:13PM +0100, Jonathan Cameron wrote:
> Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
> and CXL Type 3 end points.
>
> Signed-off-by: Jonathan Cameron
>
> ---
One comment inline, other than that, looks good to me.
> v3: Factor out the
é
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_component.h | 18 ++
> hw/cxl/cxl-component-utils.c | 18 ++
> 2 files changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/include/hw/
On Mon, Sep 04, 2023 at 05:18:47PM +0100, Jonathan Cameron wrote:
> Description of change in previous patch.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 -
> tests/data/acpi/q35/DSDT.cxl
On Mon, Sep 04, 2023 at 05:18:45PM +0100, Jonathan Cameron wrote:
> Addition of QTG in following patch requires an update to the test
> data.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file
wed-by: Philippe Mathieu-Daudé
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> hw/cxl/cxl-host.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
> index 034c7805b3..f0920da956 100644
0, the BW is 100 GB/s. So the
> entry_base_unit should be changed from 1000 to 1024 given the comment notes
> it's 16GB/s for .latency_bandwidth.
>
> Fixes: 882877fc359d ("hw/pci-bridge/cxl-upstream: Add a CDAT table access
> DOE")
> Signed-off-by: Dave Jiang
&g
jian@cn.fujitsu.com__;!!EwVzqGoTKBqv-0DWAJBm!TWHVrdL5Ys7OOFU_w1CJQ5DC6mxu649kYA9GYDJ182CNPuQqpVkWYsB5mlJpVd_BAAmhxCD4Si2CkMERZI7ZE03kPz2c$
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> docs/system/devices/cxl.rst | 8
> 1 file changed, 4 insertions(+), 4
On Mon, Sep 04, 2023 at 05:18:46PM +0100, Jonathan Cameron wrote:
> From: Dave Jiang
>
> Add a simple _DSM call support for the ACPI0017 device to return a fake QTG
> ID value of 0 in all cases. The enabling is for _DSM plumbing testing
> from the OS.
>
> Following edited for readbility only
>
On Fri, Sep 08, 2023 at 01:12:45PM +, J?rgen Hansen wrote:
> On 7/25/23 20:39, Fan Ni wrote:
> > From: Fan Ni
> >
> > Add dynamic capacity extent list representative to the definition of
> > CXLType3Dev and add get DC extent list mailbox command per
&g
On Fri, Sep 08, 2023 at 01:00:16PM +, J?rgen Hansen wrote:
> On 7/25/23 20:39, Fan Ni wrote:
> > From: Fan Ni
> >
> > Per CXL spec 3.0, two mailbox commands are implemented:
> > Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
> > Relea
hilippe Mathieu-Daudé
> ---
Reviewed-by: Fan Ni
> hw/cxl/cxl-device-utils.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
> index 517f06d869..cd0c45a2ed 100644
> --- a/hw/cxl/cxl-device
On Mon, Sep 18, 2023 at 04:02:59PM +0100, Jonathan Cameron wrote:
> These crossed with the previous fix to get rid of examples
> using aarch64 for which support is not yet upstream.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> docs/system/devices/cxl
On Mon, Sep 18, 2023 at 04:02:57PM +0100, Jonathan Cameron wrote:
> From: Dmitry Frolov
>
> According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up
> to 16. This also corresponds to CXL r3.0 spec. So, the fw->target_hbs[]
> array is iterated from 0 to 15. But it is staticaly
: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/mem/cxl_type3.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index c5855d4e7d..ad3f0f6a9d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1,3 +1,
d to enforce that the register storage is of the
> matching size, allowing fixed values to be used for divisors of
> the array indices.
>
> Suggested-by: Michael Tokarev
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> v2: Use switch statements. Note we coudl have renamed
On Fri, Sep 15, 2023 at 06:04:17PM +0100, Jonathan Cameron wrote:
> Done to reduce line lengths where this is used.
> Ext seems sufficiently obvious that it need not be spelt out
> fully.
>
> Signed-off-by: Jonathan Cameron
> Reviewed-by: Philippe Mathieu-Daudé
> ---
On Fri, Sep 15, 2023 at 06:04:18PM +0100, Jonathan Cameron wrote:
> Michael Tsirkin observed that there were some unnecessarily
> long lines in the CXL code in a recent review.
> This patch is intended to rectify that where it does not
> hurt readability.
>
> Reviewed-by: Michael Tokarev
>
On Mon, Sep 25, 2023 at 05:11:08PM +0100, Jonathan Cameron wrote:
> Enables having multiple CCIs per devices. Each CCI (mailbox) has it's own
> state and command list, so they can't share a single structure.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
&g
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_device.h | 5 +++-
> hw/cxl/cxl-device-utils.c | 51 -
> hw/cxl/cxl-mailbox-utils.c | 43 ---
> 3 files changed, 64 insertions(+),
is no longer an opaque structure.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/pci-bridge/cxl_upstream_port.h | 18 ++
> hw/pci-bridge/cxl_upstream.c | 11 +--
> 2 files changed, 19 insertions(+), 10 deletions(
On Mon, Sep 25, 2023 at 04:22:58PM +0100, Jonathan Cameron wrote:
> Rename the version not burried in the macro to cap_h.
The change looks good to me. Just one minor thing. why "version" get
involved here?
Fan
>
> Signed-off-by: Jonathan Cameron
> ---
>
> I had another instance of this in a
t;
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_device.h | 13
> hw/cxl/cxl-mailbox-utils.c | 121 +++-
> 2 files changed, 78 insertions(+), 56 deletions(-)
>
> diff --git a/include/hw/cxl/cxl_devic
ust allow
> for that.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_device.h | 7 +-
> hw/cxl/cxl-events.c | 2 +-
> hw/cxl/cxl-mailbox-utils.c | 222 +---
> 3 files changed, 132 insertions(+)
On Fri, Sep 29, 2023 at 09:50:16AM +0200, Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > On Wed, 27 Sep 2023 19:13:35 +0000
> > Fan Ni wrote:
> >
> >> On Mon, Sep 25, 2023 at 04:22:58PM +0100, Jonathan Cameron wrote:
> >>
> >> >
_ARRAY, CAP_COUNT, cap_count);
> +ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
> +ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1);
> +ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_COUNT, cap_count);
>
> cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1, 2);
> device_reg_init_common(cxl_dstate);
> --
> 2.39.2
>
Reviewed-by: Fan Ni
On Fri, Aug 25, 2023 at 12:42:56PM +0100, Jonathan Cameron wrote:
> On Thu, 24 Aug 2023 13:49:00 -0700
> Fan Ni wrote:
>
> > On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> > > On Tue, 25 Jul 2023 18:39:56 +
> > > Fan Ni
On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> On Tue, 25 Jul 2023 18:39:56 +
> Fan Ni wrote:
>
> > From: Fan Ni
> >
> > Not all dpa range in the dc regions is valid to access until an extent
> > covering the range has been ad
create-region region0
2. ndctl create-namespace -m dax -r region0
3. daxctl reconfigure-device --mode=system-ram --no-online dax0.0
4. daxctl online-memory dax0.0
5. numactl --membind=1 htop
Signed-off-by: Fan Ni
---
hw/cxl/cxl-host.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions
On Fri, Jan 13, 2023 at 09:47:25AM +, Jonathan Cameron wrote:
> On Fri, 13 Jan 2023 00:27:55 +
> Fan Ni wrote:
>
> > For passthrough decoder (a decoder hosted by a cxl component with only
> > one downstream port), its cache_mem_registers field COMMITTED
> > (
On Mon, Nov 28, 2022 at 10:01:57AM -0500, Gregory Price wrote:
> From: Gregory Price
>
> This commit enables each CXL Type-3 device to contain one volatile
> memory region and one persistent region.
>
> Two new properties have been added to cxl-type3 device initialization:
>
On Tue, Jan 24, 2023 at 09:47:20AM +, Jonathan Cameron wrote:
> On Mon, 23 Jan 2023 17:53:24 +
> Fan Ni wrote:
>
> > On Mon, Jan 23, 2023 at 12:17:10PM +, Jonathan Cameron wrote:
> >
> >
> >
> > > Until now, testing using CXL has relied
On Fri, Jan 27, 2023 at 10:01:49AM +, Jonathan Cameron wrote:
> On Thu, 26 Jan 2023 21:57:35 +
> Fan Ni wrote:
>
> > On Wed, Jan 25, 2023 at 03:27:03PM +, Jonathan Cameron wrote:
> >
> > > The CXL r3.0 specification allows for there to be no HDM deco
that it now works. The option is retained
> to allow testing of software that does allow for these HDM decoders to exist,
> once someone writes it.
>
> Reported-by: Fan Ni
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-host.c | 31 +
as been known since the initial QEMU patch
> postings / kernel CXL region support, Fan Ni Ran into it recently reminding
> me that we should solve it.
>
> https://lore.kernel.org/linux-cxl/20230113171044.GA24788@bgt-140510-bm03/
>
> Tree with a large set of patches before this at:
>
address, val, len);
> +pcie_aer_root_write_config(d, address, val, len, root_cmd);
>
> cxl_rp_dvsec_write_config(d, address, val, len);
> }
> --
> 2.37.2
>
>
Reviewed-by: Fan Ni
Linux)
>
> Signed-off-by: Jonathan Cameron
> Reviewed-by: Dave Jiang
> ---
Reviewed-by: Fan Ni
> hw/pci/pcie_aer.c | 10 +-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
> index 909e027d99..103667c368 100644
Device *dev,
> uint32_t addr, uint32_t val, int len,
> uint32_t root_cmd_prev);
>
> +int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err);
> #endif /* QEMU_PCIE_AER_H */
> --
> 2.37.2
>
>
Reviewed-by: Fan Ni
d-off-by: Jonathan Cameron
> Reviewed-by: Dave Jiang
> ---
Reviewed-by: Fan Ni
> hw/pci/pcie_aer.c | 4
> include/hw/pci/pcie_regs.h | 3 +++
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
> index 9a19be44ae..9
g
> ---
Reviewed-by: Fan Ni
> hw/pci-bridge/cxl_root_port.c | 61 +++
> 1 file changed, 61 insertions(+)
>
> diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
> index 00195257f7..7dfd20aa67 100644
> --- a/hw/pci-bridg
wed-by: Dave Jiang
> ---
Reviewed-by: Fan Ni
> hw/mem/cxl_type3.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 217a5e639b..6cdd988d1d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl
we aren't going to yet hit
> an problems with big endian. However it is good to avoid making
> things worse for that support in the future.
>
> Reviewed-by: Dave Jiang
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
more complex
> corners of the kernel code.
>
> Reviewed-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> v4: No change
> ---
> hw/cxl/cxl-mailbox-utils.c | 41 ++
> 1 file changed, 41 insertions(+)
>
&
ect a device on your machine.
>
> Note that the poison list supported is kept short enough to avoid the
> complexity of state machine that is needed to handle the MORE flag.
>
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> ---
> v4:
> - Widen the mask o
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
One minor thing as mentioned below.
&g
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Signed-off-by: Fan Ni
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index
viour so use that for QEMU emulation.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
Tested-by: Fan Ni
The patch passed the tests as shown in previous mailing list discussion:
https://lore.kernel.org/linux-cxl/640276695c8e8_5b27929...@dwillia2-xfh.j
e": "cache-data-parity",
> "header":
> [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
> },
> {
> "type": "internal",
> "header": [ 1, 2, 4]
&g
On Mon, Feb 20, 2023 at 11:46:46AM +, Jonathan Cameron wrote:
> On Fri, 17 Feb 2023 06:08:57 -0500
> Gregory Price wrote:
>
> > On Fri, Feb 17, 2023 at 04:16:17PM +, Jonathan Cameron via wrote:
> > > On Tue, 31 Jan 2023 16:38:47 +
> > > Jonathan Cameron via wrote:
> > >
> > > >
patch 2 for a discussion of why I think we can make this change
> without backwards compatibility issues (basically if it didn't work before
> who are we breaking by making it work?)
>
> Whilst this limitation has been known since the initial QEMU patch
> postings / kernel CXL region suppor
On Mon, Feb 06, 2023 at 05:28:11PM +, Jonathan Cameron wrote:
> Next patch will drop duplicate _UID entry so allow update.
>
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> tests/qtest/bios-table
On Mon, Feb 06, 2023 at 05:28:13PM +, Jonathan Cameron wrote:
> Dropping the ID effects this table in trivial fashion.
>
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> tests/d
On Mon, Feb 06, 2023 at 05:28:12PM +, Jonathan Cameron wrote:
> Noticed as this prevents iASL disasembling the DSDT table.
>
> Reviewed-by: Ira Weiny
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan
On Mon, Feb 06, 2023 at 05:28:07PM +, Jonathan Cameron wrote:
> msix_init_exclusive_bar() can fail, so if it does cleanup the address space.
>
> Reviewed-by: Ira Weiny
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
ted-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/pci-bridge/cxl_downstream.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
> index 3d4e6b59c
d-by: Davidlohr Bueso
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> ---
> v2:
> Change to 256 * MiB and include qemu/units.h (Philippe Mathieu-Daudé)
> ---
> hw/cxl/cxl-mailbox-utils.c | 15 +--
> 1 file changed, 9 insertions(+), 6 deletions(-)
&
Cameron
> ---
Reviewed-by: Fan Ni
> hw/mem/cxl_type3.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 252822bd82..217a5e639b 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@
cel_uuid. Adjust
> cxl_initialize_mailbox() because it can't fail now.
>
> Update specification reference.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
>
Reviewed-by
> Tested-by: Gregory Price
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> ---
> v2: Update comment (Philippe)
> ---
> include/qemu/bswap.h | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff
IDs.
>
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> include/qemu/uuid.h | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/include/qemu/uuid.h b/in
ned-off-by: Gregory Price
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
Tested-by: Fan Ni
Tested a single HB, single RP, single volatile memdev setup (with
kernel volatile patch from Dan), it passed the following ops,
1. cxl list
2. cxl create-region
3. daxctl online-memory
On Tue, Feb 28, 2023 at 11:39:26AM +, Jonathan Cameron wrote:
> Fan Ni has offered to help out with QEMU CXL emulation reviewing.
> Add him as a designated reviewer.
>
> Signed-off-by: Jonathan Cameron
>
Acked-by: Fan Ni
> --
> Thanks to Fan for stepping up a
On Mon, Feb 27, 2023 at 05:03:06PM +, Jonathan Cameron wrote:
> Given the increasing usage of this mailbox return code type, now
> is a good time to switch to QEMU style naming.
>
> Reviewed-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> --
bit host native value.
>
> The use of b, w, l, q as the size specifier is limiting. So "24" was
> used for the size part of the function name.
>
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> ---
> v7:
> -
On Mon, Feb 27, 2023 at 05:03:07PM +, Jonathan Cameron wrote:
> From: Ira Weiny
>
> There are new users of this functionality coming shortly so factor
> it out from the GET_TIMESTAMP mailbox command handling.
>
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Camer
t; if (fread(cdat->buf, file_size, 1, fp) == 0) {
> error_setg(errp, "CDAT: File read failed");
> +fclose(fp);
> return;
> }
>
Good catch.
Reviewed-by: Fan Ni
> --
> 2.37.2
>
>
> No virus found
> Checked by Hillstone Network AntiVirus
On Mon, Apr 03, 2023 at 11:38:22AM +0200, Philippe Mathieu-Daudé wrote:
> Cc'ing CXL maintainers.
>
> On 3/4/23 11:04, Maverickk 78 wrote:
> > Hello,
> >
> > I am trying qemu-system-aarch64 & cxl configuration listed in
> >
> >
On Tue, Mar 21, 2023 at 06:00:11PM +, Jonathan Cameron wrote:
> Not a real problem yet as all supported architectures are
> little endian, but continue to tidy these up when touching
> code for other reasons.
>
> Signed-off-by: Jonathan Cameron
Hi Jonathan,
Did you forget to send the other
n the Set command due to DCD
> being optional. Perform the checks separately.
>
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_device.h | 6 +-
> include/hw/cxl/cxl_events.h | 23
> hw/cxl/cxl-eve
The 05/22/2023 16:09, Jonathan Cameron wrote:
> Following patches will need access to the mailbox return code
> type so move it to the header.
>
> Reviewed-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/
Replace the stubbed out CXL Get/Clear Event mailbox commands with
> commands that operate on the new infrastructure.
>
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
See comments below in cxl_event_insert.
> include/hw/cxl/cxl_device
register block. Wire up the register and initialize the
> event status for each log.
>
> To support CXL 3.0 the version of the device status register block needs
> to be 2. Change the macro to allow for setting the version.
>
> Signed-off-by: Ira Weiny
> Signed-off-
On Mon, Jun 05, 2023 at 10:35:48AM -0700, Ira Weiny wrote:
> Fan Ni wrote:
> > Since the early draft of DCD support in kernel is out
> > (https://urldefense.com/v3/__https://lore.kernel.org/linux-cxl/20230417164126.GA1904906@bgt-140510-bm03/T/*t__;Iw!!EwVzqGoTKBqv-0DWAJBm!RHzXPIcSiG
. However, I can fork the branch and rebase my patch series atop and
share with you the new repo if that helps you move forward your
work.
Let me know your thought.
Fan
>
>
> From: Fan Ni
> Sent: Monday, June 5, 2023 10:51 AM
> To: Ira Weiny
> Cc: qemu-devel@nongnu.org ;
&
The 05/22/2023 16:09, Jonathan Cameron wrote:
> From: Ira Weiny
>
> To facilitate testing provide a QMP command to inject a general media
> event. The event can be added to the log specified.
>
> Signed-off-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
>
> ---
d). That does not
> reduce the usefulness of this more basic generation of the events.
>
> Reviewed-by: Ira Weiny
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> ---
> v7: Expanded docs for qapi and added a lot of cross references to
> the CXL revision 3.0 speci
"transaction-type": 192,
> "channel": 3,
> "rank": 17,
> "nibble-mask": 37421234,
> "bank-group": 7,
> "bank": 11,
> "row": 2,
> "column"
From: Fan Ni
Per CXL spec 3.0, two mailbox commands are implemented:
Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.4.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 253
include/hw
From: Fan Ni
Add dynamic capacity extent list representative to the definition of
CXLType3Dev and add get DC extent list mailbox command per
CXL.spec.3.0:.8.2.9.8.9.2.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 71 +
hw/mem/cxl_type3.c
From: Fan Ni
Based on CXL spec 3.0 Table 8-94 (Identify Memory Device Output
Payload), dynamic capacity event log size should be part of
output of the Identify command.
Add dc_event_log_size to the output payload for the host to get the info.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox
From: Fan Ni
With the change, when setting up memory for type3 memory device, we can
create DC regions
A property 'num-dc-regions' is added to ct3_props to allow users to pass the
number of DC regions to create. To make it easier, other region parameters
like region base, length, and block size
On Tue, Jul 25, 2023 at 08:18:08AM -0700, Ira Weiny wrote:
> Fan Ni wrote:
> > On Thu, May 11, 2023 at 05:56:40PM +0000, Fan Ni wrote:
> >
> > FYI.
> >
> > I have updated the patch series and sent out again.
> >
> > I suggested anyone who are
From: Fan Ni
Not all dpa range in the dc regions is valid to access until an extent
covering the range has been added. Add a bitmap for each region to
record whether a dc block in the region has been backed by dc extent.
For the bitmap, a bit in the bitmap represents a dc block. When a dc
extent
From: Fan Ni
Per cxl spec 3.0, add dynamic capacity region representative based on
Table 8-126 and extend the cxl type3 device definition to include dc region
information. Also, based on info in 8.2.9.8.9.1, add 'Get Dynamic Capacity
Configuration' mailbox support.
Signed-off-by: Fan Ni
From: Fan Ni
Rename mem_size as static_mem_size for type3 memdev to cover static RAM and
pmem capacity, preparing for the introduction of dynamic capacity to support
dynamic capacity devices.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 5 +++--
hw/mem/cxl_type3.c | 8
From: Fan Ni
Since fabric manager emulation is not supported yet, the change implements
the functions to add/release dynamic capacity extents as QMP interfaces.
1. Add dynamic capacity extents:
For example, the command to add two continuous extents (each is 128MB long)
to region 0 (starting
From: Fan Ni
Add (file/memory backed) host backend, all the dynamic capacity regions
will share a single, large enough host backend. Set up address space for
DC regions to support read/write operations to dynamic capacity for DCD.
With the change, following supports are added:
1. add a new
iny-mobl.notmuch/T/#m09983a3dbaa9135a850e345d86714bf2ab957ef6
Fan Ni (9):
hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output
payload of identify memory device command
hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative
and mailbox command support
include
-cxl/20230724162313.34196-1-fan...@samsung.com/T/#t
Thanks,
Fan
> On Sat, 22 Jul 2023 21:52:06 -0700
> Ira Weiny wrote:
>
> > nifan@ wrote:
> > > From: Fan Ni
> > >
> > > The patch series provides dynamic capacity device (DCD) emulation in
> >
On Thu, May 11, 2023 at 05:56:40PM +, Fan Ni wrote:
FYI.
I have updated the patch series and sent out again.
I suggested anyone who are interested in DCD and using this patch series to
use the new series. Quite a few things has been fixed.
https://lore.kernel.org/linux-cxl
From: Fan Ni
Per CXL spec 3.0, two mailbox commands are implemented:
Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.4.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 253
include/hw
-cxl/649da378c28a3_968bb29420@iweiny-mobl.notmuch/T/#t
Fan Ni (9):
hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output
payload of identify memory device command
hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative
and mailbox command support
include/hw/cxl
From: Fan Ni
Not all dpa range in the dc regions is valid to access until an extent
covering the range has been added. Add a bitmap for each region to
record whether a dc block in the region has been backed by dc extent.
For the bitmap, a bit in the bitmap represents a dc block. When a dc
extent
From: Fan Ni
Per cxl spec 3.0, add dynamic capacity region representative based on
Table 8-126 and extend the cxl type3 device definition to include dc region
information. Also, based on info in 8.2.9.8.9.1, add 'Get Dynamic Capacity
Configuration' mailbox support.
Signed-off-by: Fan Ni
From: Fan Ni
Based on CXL spec 3.0 Table 8-94 (Identify Memory Device Output
Payload), dynamic capacity event log size should be part of
output of the Identify command.
Add dc_event_log_size to the output payload for the host to get the info.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox
From: Fan Ni
Add (file/memory backed) host backend, all the dynamic capacity regions
will share a single, large enough host backend. Set up address space for
DC regions to support read/write operations to dynamic capacity for DCD.
With the change, following supports are added:
1. add a new
From: Fan Ni
With the change, when setting up memory for type3 memory device, we can
create DC regions
A property 'num-dc-regions' is added to ct3_props to allow users to pass the
number of DC regions to create. To make it easier, other region parameters
like region base, length, and block size
From: Fan Ni
Since fabric manager emulation is not supported yet, the change implements
the functions to add/release dynamic capacity extents as QMP interfaces.
1. Add dynamic capacity extents:
For example, the command to add two continuous extents (each is 128MB long)
to region 0 (starting
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