From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
---
target/riscv/cpu.c | 4
target/riscv/cpu.h | 4
target/riscv/csr.c | 38 ++
3 files
",
> + "riscv,none");
> +}
> name = riscv_isa_string(>soc[socket].harts[cpu]);
> qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
> g_free(name);
> --
> 2.35.1
>
>
>
Reviewed-by: Frank Chang
letter_exts[] = "IEMAFDQLCBJTPVNH";
>
> What about K?
>
> Why not use IEMAFDQCBKJTPVNH instead?
>
> Alistair
>
The RISC-V ISA Manual (version 20191213) is quite old.
Where "L" was not removed and "K" was not introduced.
It seems Unprivileged spec is not
Hi Tomasz,
Could you please send this patchset to qemu-ri...@nongnu.org, too?
Regards,
Frank Chang
On Thu, Mar 17, 2022 at 6:24 AM Tomasz Jeznach
wrote:
> This is the series of patches to introduce RISC-V IOMMU emulation in QEMU.
>
> The Rivos IOMMU device implementation is based o
notifier:
4576704: arm/boot: split load_dtb() from arm_load_kernel()
ac9d32e: hw/arm/boot: arm_load_kernel implemented as a machine init done
notifier
Regards,
Frank Chang
On Thu, Mar 17, 2022 at 6:24 AM Tomasz Jeznach
wrote:
> Enable rivos-iommu device support in riscv:virt machine emulat
Reviewed-by: Frank Chang
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li wrote:
> for some cases, scale is always equal or less than 0, since lmul is not
> larger than 3
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/insn_trans/trans_rvv.c.
Reviewed-by: Frank Chang
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li wrote:
> LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
> the same helper
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/helper.h
60 ++
> 1 file changed, 60 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddda4906ffb7..937ccdda997b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V C
t; +new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> +g_free(old);
> +old = new;
> +}
> +}
> +
> +*isa_str = new;
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> @@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> +riscv_isa_string_ext(cpu, _str, maxlen);
> return isa_str;
> }
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
IP (1 << IRQ_S_GEXT)
> +#define MIP_LCOFIP (1 << IRQ_PMU_OVF)
>
> /* sip masks */
> #define SIP_SSIP MIP_SSIP
> #define SIP_STIP MIP_STIP
> #define SIP_SEIP
de "exec/exec-all.h"
> #include "tcg/tcg-op.h"
> #include "trace.h"
> #include "semihosting/common-semi.h"
> +#include "cpu.h"
>
Redundant: #include "cpu.h"
Regards,
Frank Chang
> +#include "cpu_bits.h"
h
> },
> +[CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> #endif /* !CONFIG_USER_ONLY */
> };
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 2a48bcf81d3d..d706a97e65c8 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -300,6 +300,9 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> +VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU,
> RV_MAX_MHPMCOUNTERS),
> +VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU,
> RV_MAX_MHPMCOUNTERS),
> +VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU,
> RV_MAX_MHPMEVENTS),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> --
> 2.30.2
>
>
>
Hi Atish,
I encountered the compilation error when compiling user-mode QEMU
checked out from the branch in your repo:
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mhpmevent_val’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mhpmeventh_val’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘pmu_ctrs’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named ‘priv’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mcounteren’
Also, some functions are defined but not used in user-mode QEMU:
error: ‘read_scountovf’ defined but not used [-Werror=unused-function]
error: ‘write_mhpmcounterh’ defined but not used [-Werror=unused-function]
error: ‘write_mhpmcounter’ defined but not used [-Werror=unused-function]
... etc
I think you need to add the #if !defined(CONFIG_USER_ONLY) macros
to prevent using the variables which are available only in system-mode QEMU
and excluding the functions which are called only in system-mode QEMU.
Regards,
Frank Chang
On Fri, Mar 11, 2022 at 2:42 AM Atish Kumar Patra
wrote:
> On Wed, Mar 9, 2022 at 5:47 AM Frank Chang wrote:
> >
> > Atish Patra 於 2022年3月9日 週三 上午8:53寫道：
> >>
> >> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> >> pr
ot;,
> TARGET_LONG_BITS);
> -for (i = 0; i < sizeof(riscv_exts); i++) {
> -if (cpu->env.misa_ext & RV(riscv_exts[i])) {
> -*p++ = qemu_tolower(riscv_exts[i]);
> +for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
> +if (cp
Also, I think "Zifencei" and "Zicsr" should also be covered as well,
and all extensions should follow the order defined in Table 28.11:
https://github.com/riscv/riscv-isa-manual/blob/master/src/naming.tex#L141
"The table also defines the canonical order in which extension nam
;does not permit any"-part is wrong, therefore we should raise a
> store page fault.
>
> In fact, I can't predict what will happen, because the code in
> target/riscv/cpu_helper.c does
> not really prioritize page faults or PMP faults. it returns one of them,
> once they are enco
Typo in patch title:
s/extenstion/extension/g
Regards,
Frank Chang
On Sat, Feb 26, 2022 at 3:45 PM Frank Chang wrote:
>
>
> Atish Patra 於 2022年2月23日 週三 上午6:39寫道：
>
>> The Linux kernel parses the ISA extensions from "riscv,isa" DT
>> property. It used to
On Sun, Mar 6, 2022 at 2:12 PM Atish Kumar Patra
wrote:
>
>
> On Sat, Mar 5, 2022 at 9:36 PM Frank Chang wrote:
>
>> On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra
>> wrote:
>>
>>>
>>>
>>> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stueb
On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra
wrote:
>
>
> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote:
>
>> Hi,
>>
>> Am Donnerstag, 3. März 2022, 19:58:38 CET schrieb Atish Patra:
>> > On Fri, Feb 25, 2022 at 11:46 PM Frank Chang
>> w
},
> +{ "svinval", cpu->cfg.ext_svinval },
> +{ "svnapot", cpu->cfg.ext_svnapot },
>
We still have other sub-extensions, e.g. Zfh, Zba, Zbb, Zbc, Zbs... etc.
Do you mind adding them as well?
Also, I think the order of ISA strings should be alp
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible
From: Frank Chang
This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers.
This patchset is the updated verion of:
https
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time
On Tue, Feb 1, 2022 at 10:34 AM Alistair Francis
wrote:
> On Wed, Jan 26, 2022 at 7:55 PM wrote:
> >
> > From: Frank Chang
> >
> > RISC-V privilege spec defines that mtime is exposed as a memory-mapped
> > machine-mode read-write register. However, as Q
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time
From: Frank Chang
In SPI-mode, CMD58 returns R3 response with the format:
39 32 31 0
++ +---+
| R1 | |OCR|
++ +---+
Where R1
On Tue, Jan 18, 2022 at 10:35 AM wrote:
> From: Frank Chang
>
> In SPI-mode, type B ("cleared on valid command") clear condition is not
> supported, and as the "In idle state" bit in SPI-mode has type A
> ("according to current state") clear condi
From: Frank Chang
In SPI-mode, unlike SD-mode, card status bits: ILLEGAL_COMMAND and
COM_CRC_ERROR have type C ("cleared by read") clear conditions.
Also, type B ("cleared on valid command") clear condition is not
supported in SPI-mode. As the "In idle state&
On Thu, Jan 20, 2022 at 8:05 PM Anup Patel wrote:
> On Thu, Jan 20, 2022 at 1:49 PM Frank Chang
> wrote:
> >
> > On Thu, Jan 20, 2022 at 12:20 AM Anup Patel wrote:
> >>
> >> Hi Frank,
> >>
> >> On Wed, Jan 19, 2022 at 9:07 PM Frank Chang
&
On Thu, Jan 20, 2022 at 12:20 AM Anup Patel wrote:
> Hi Frank,
>
> On Wed, Jan 19, 2022 at 9:07 PM Frank Chang
> wrote:
> >
> > On Wed, Jan 19, 2022 at 11:27 PM Anup Patel wrote:
> >>
> >> From: Anup Patel
> >>
> >> The RISC-V AIA (A
irqs, env->siprio);
> +}
> +
> +/* Check VS-mode interrupts */
> +irqs = pending & env->mideleg & env->hideleg & -vsie;
> +if (irqs) {
> +virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
> +irqs >> 1, env->hviprio);
> +return (virq <= 0) ? virq : virq + 1;
> +}
> +
> +/* Indicate no pending interrupt */
> +return RISCV_EXCP_NONE;
> }
>
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 39b5dbc36b..92536c4a0e 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -92,6 +92,7 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> +VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
>
> VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> @@ -223,6 +224,8 @@ const VMStateDescription vmstate_riscv_cpu = {
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> +VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
> +VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
> VMSTATE_UINTTL(env.pc, RISCVCPU),
> VMSTATE_UINTTL(env.load_res, RISCVCPU),
> VMSTATE_UINTTL(env.load_val, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
; forwarding wired interupts to RISC-V HARTs directly or as MSIs
> (Message Signaled Interupts).
>
> This patch adds device emulation for RISC-V AIA APLIC.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> Reviewed-by: Frank Chang
> ---
> hw/intc/Kconfig
ion.
> + */
> +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child)
> +{
> +RISCVAPLICState *caplic, *paplic;
> +
> +assert(parent && child);
> +caplic = RISCV_APLIC(child);
> +paplic = RISCV_APLIC(parent);
> +
> +assert(paplic->num_irqs == caplic->num_irqs);
> +assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN);
> +
> +caplic->parent = paplic;
> +paplic->children[paplic->num_children] = caplic;
> +paplic->num_children++;
> +}
> +
> +/*
> + * Create APLIC device.
> + */
> +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
> +uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
> +uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent)
> +{
> +DeviceState *dev = qdev_new(TYPE_RISCV_APLIC);
> +uint32_t i;
> +
> +assert(num_harts < APLIC_MAX_IDC);
> +assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size);
> +assert(num_sources < APLIC_MAX_SOURCE);
> +assert(APLIC_MIN_IPRIO_BITS <= iprio_bits);
> +assert(iprio_bits <= APLIC_MAX_IPRIO_BITS);
> +
> +qdev_prop_set_uint32(dev, "aperture-size", size);
> +qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
> +qdev_prop_set_uint32(dev, "num-harts", num_harts);
> +qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1));
> +qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1);
> +qdev_prop_set_bit(dev, "msimode", msimode);
> +qdev_prop_set_bit(dev, "mmode", mmode);
> +
> +sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), _fatal);
> +sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> +
> +if (parent) {
> +riscv_aplic_add_child(parent, dev);
> +}
> +
> +if (!msimode) {
> +for (i = 0; i < num_harts; i++) {
> +CPUState *cpu = qemu_get_cpu(hartid_base + i);
> +
> +qdev_connect_gpio_out_named(dev, NULL, i,
> +qdev_get_gpio_in(DEVICE(cpu),
> +(mmode) ? IRQ_M_EXT :
> IRQ_S_EXT));
> +}
> +}
> +
> +return dev;
> +}
> diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
> new file mode 100644
> index 00..de8532fbc3
> --- /dev/null
> +++ b/include/hw/intc/riscv_aplic.h
> @@ -0,0 +1,79 @@
> +/*
> + * RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_RISCV_APLIC_H
> +#define HW_RISCV_APLIC_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +#define TYPE_RISCV_APLIC "riscv.aplic"
> +
> +typedef struct RISCVAPLICState RISCVAPLICState;
> +DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
> +
> +#define APLIC_MIN_SIZE0x4000
> +#define APLIC_SIZE_ALIGN(__x) (((__x) + (APLIC_MIN_SIZE - 1)) & \
> + ~(APLIC_MIN_SIZE - 1))
> +#define APLIC_SIZE(__num_harts) (APLIC_MIN_SIZE + \
> + APLIC_SIZE_ALIGN(32 * (__num_harts)))
> +
> +struct RISCVAPLICState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +qemu_irq *external_irqs;
> +
> +/*< public >*/
> +MemoryRegion mmio;
> +uint32_t bitfield_words;
> +uint32_t domaincfg;
> +uint32_t mmsicfgaddr;
> +uint32_t mmsicfgaddrH;
> +uint32_t smsicfgaddr;
> +uint32_t smsicfgaddrH;
> +uint32_t genmsi;
> +uint32_t *sourcecfg;
> +uint32_t *state;
> +uint32_t *target;
> +uint32_t *idelivery;
> +uint32_t *iforce;
> +uint32_t *ithreshold;
> +
> +/* topology */
> +#define QEMU_APLIC_MAX_CHILDREN16
> +struct RISCVAPLICState *parent;
> +struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN];
> +uint16_t num_children;
> +
> +/* config */
> +uint32_t aperture_size;
> +uint32_t hartid_base;
> +uint32_t num_harts;
> +uint32_t iprio_mask;
> +uint32_t num_irqs;
> +bool msimode;
> +bool mmode;
> +};
> +
> +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
> +
> +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
> +uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
> +uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent);
> +
> +#endif
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
= { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> @@ -2937,6 +3133,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* VS-Level Interrupts (H-extension with AIA) */
> [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
>
> +/* VS-Level IMSIC Interface (H-extension with AIA) */
> +[CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL,
> rmw_xtopei },
> +
> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
t; index 00..58c2aaa8dc
> --- /dev/null
> +++ b/include/hw/intc/riscv_imsic.h
> @@ -0,0 +1,68 @@
> +/*
> + * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_RISCV_IMSIC_H
> +#define HW_RISCV_IMSIC_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +#define TYPE_RISCV_IMSIC "riscv.imsic"
> +
> +typedef struct RISCVIMSICState RISCVIMSICState;
> +DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC)
> +
> +#define IMSIC_MMIO_PAGE_SHIFT 12
> +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT)
> +#define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) *
> IMSIC_MMIO_PAGE_SZ)
> +
> +#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6
> +#define IMSIC_MMIO_GROUP_MIN_SHIFT 24
> +
> +#define IMSIC_HART_NUM_GUESTS(__guest_bits) \
> +(1U << (__guest_bits))
> +#define IMSIC_HART_SIZE(__guest_bits) \
> +(IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ)
> +#define IMSIC_GROUP_NUM_HARTS(__hart_bits)\
> +(1U << (__hart_bits))
> +#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \
> +(IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits))
> +
> +struct RISCVIMSICState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +qemu_irq *external_irqs;
> +
> +/*< public >*/
> +MemoryRegion mmio;
> +uint32_t num_eistate;
> +uint32_t *eidelivery;
> +uint32_t *eithreshold;
> +uint32_t *eistate;
> +
> +/* config */
> +bool mmode;
> +uint32_t hartid;
> +uint32_t num_pages;
> +uint32_t num_irqs;
> +};
> +
> +DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
> +uint32_t num_pages, uint32_t num_ids);
> +
> +#endif
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
Anup Patel 於 2022年1月18日 週二 上午11:41寫道：
> On Tue, Jan 18, 2022 at 9:04 AM Frank Chang
> wrote:
> >
> > Anup Patel 於 2022年1月17日 週一 下午10:28寫道：
> >>
> >> From: Anup Patel
> >>
> >> The AIA spec defines programmable 8-bit priority for each loca
le (pending) {
> +prio = iprio[irq];
> +if (!prio) {
> +if (irq == extirq) {
> +prio = extirq_def_prio;
> +} else {
> +prio = (riscv_cpu_default_priority(irq) <
> extirq_def_prio) ?
> +
From: Frank Chang
In SPI-mode, type B ("cleared on valid command") clear condition is not
supported, and as the "In idle state" bit in SPI-mode has type A
("according to current state") clear condition, the CURRENT_STATE bits
in an SPI-mode response shoul
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 4 ++--
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 2 +-
target/riscv/translate.c | 2 ++
5 files changed, 7 insertions(+), 4
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2ba22503da..4bca1cd289 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 ++
1 file changed, 18 insertions
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
1 file changed, 25
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0898954c02..33c1df638b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7
From: Frank Chang
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 27
From: Frank Chang
All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 19 +++
1 file changed, 15 insertions
From: Frank Chang
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Frank Chang
Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 5 -
target/riscv/csr.c| 6 +-
target/riscv/translate.c | 2 ++
5 files changed, 16 insertions(+), 2
From: Frank Chang
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++---
1 file changed, 6 insertions(+), 3
From: Frank Chang
In RVV v1.0 spec, several Zve* vector extensions for embedded processors
are defined in Chapter 18.2:
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
This patchset implements Zve32f and Zve64f extensions.
The port
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans
On Tue, Jan 18, 2022 at 6:27 AM Alistair Francis
wrote:
> On Wed, Dec 29, 2021 at 12:34 PM wrote:
> >
> > From: Frank Chang
> >
> > All Zve* extensions support all vector load and store instructions,
> > except Zve64* extensions do not support EEW=64
於 2021年12月29日 週三 上午10:35寫道：
> From: Frank Chang
>
> In RVV v1.0 spec, several Zve* vector extensions for embedded processors
> are defined in Chapter 18.2:
>
> https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
>
>
Anup Patel 於 2021年12月30日 週四 下午8:55寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for wired interrupts called APLIC (Advanced
> Platform Level Interrupt Controller). The APLIC is capabable of
> forwarding wired interupts to RISC-V
;, hmode, read_hstatus,
> write_hstatus },
> [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
> write_hedeleg },
> -[CSR_HIDELEG] = { "hideleg", hmode, read_hideleg,
> write_hideleg },
> +[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL,
> rmw_hideleg },
> [CSR_HVIP]= { "hvip",hmode, NULL, NULL,
> rmw_hvip },
> [CSR_HIP] = { "hip", hmode, NULL, NULL,
> rmw_hip },
> -[CSR_HIE] = { "hie", hmode, read_hie,
> write_hie },
> +[CSR_HIE] = { "hie", hmode, NULL, NULL,
> rmw_hie },
> [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
> write_hcounteren },
> [CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
> write_hgeie },
> [CSR_HTVAL] = { "htval", hmode, read_htval,
> write_htval },
> @@ -1949,7 +2297,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> [CSR_VSSTATUS]= { "vsstatus",hmode, read_vsstatus,
> write_vsstatus},
> [CSR_VSIP]= { "vsip",hmode, NULL,NULL,
> rmw_vsip },
> -[CSR_VSIE]= { "vsie",hmode, read_vsie,
> write_vsie},
> +[CSR_VSIE]= { "vsie",hmode, NULL,NULL,
> rmw_vsie },
> [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec,
> write_vstvec },
> [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
> write_vsscratch },
> [CSR_VSEPC] = { "vsepc", hmode, read_vsepc,
> write_vsepc },
> @@ -1960,6 +2308,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2,
> write_mtval2 },
> [CSR_MTINST] = { "mtinst", hmode, read_mtinst,
> write_mtinst },
>
> +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> +[CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> +[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL,
> rmw_hviph },
> +[CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL,
> rmw_vsieh },
> +[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL,
> rmw_vsiph },
> +
> /* Physical Memory Protection */
> [CSR_MSECCFG]= { "mseccfg", epmp, read_mseccfg, write_mseccfg },
> [CSR_PMPCFG0]= { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index cffc444969..44dca84ded 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -84,7 +84,7 @@ static const VMStateDescription vmstate_hyper = {
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> -VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> +VMSTATE_UINT64(env.hideleg, RISCVCPU),
> VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.htval, RISCVCPU),
> VMSTATE_UINTTL(env.htinst, RISCVCPU),
> @@ -194,10 +194,10 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> -VMSTATE_UINTTL(env.mip, RISCVCPU),
> -VMSTATE_UINT32(env.miclaim, RISCVCPU),
> -VMSTATE_UINTTL(env.mie, RISCVCPU),
> -VMSTATE_UINTTL(env.mideleg, RISCVCPU),
> +VMSTATE_UINT64(env.mip, RISCVCPU),
> +VMSTATE_UINT64(env.miclaim, RISCVCPU),
> +VMSTATE_UINT64(env.mie, RISCVCPU),
> +VMSTATE_UINT64(env.mideleg, RISCVCPU),
> VMSTATE_UINTTL(env.satp, RISCVCPU),
> VMSTATE_UINTTL(env.stval, RISCVCPU),
> VMSTATE_UINTTL(env.medeleg, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
R_HTVAL] = { "htval", hmode, read_htval,
> write_htval },
> [CSR_HTINST] = { "htinst", hmode, read_htinst,
> write_htinst },
> -[CSR_HGEIP] = { "hgeip", hmode, read_zero,
> write_hgeip },
> +[CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL
> },
> [CSR_HGATP] = { "hgatp", hmode, read_hgatp,
> write_hgatp },
> [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
> write_htimedelta },
> [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
> write_htimedeltah },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index ad8248ebfd..76dd0d415c 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -78,8 +78,8 @@ static bool hyper_needed(void *opaque)
>
> static const VMStateDescription vmstate_hyper = {
> .name = "cpu/hyper",
> -.version_id = 1,
> -.minimum_version_id = 1,
> +.version_id = 2,
> +.minimum_version_id = 2,
> .needed = hyper_needed,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> @@ -89,6 +89,8 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.htval, RISCVCPU),
> VMSTATE_UINTTL(env.htinst, RISCVCPU),
> VMSTATE_UINTTL(env.hgatp, RISCVCPU),
> +VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> +VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> VMSTATE_UINT64(env.htimedelta, RISCVCPU),
>
> VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
tion rmw_hip(CPURISCVState *env,
> int csrno,
> static RISCVException read_hie(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -*val = env->mie & VS_MODE_INTERRUPTS;
> +*val = env->mie & HS_MODE_INTERRUPTS;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_hie(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> -target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val &
> VS_MODE_INTERRUPTS);
> +target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val &
> HS_MODE_INTERRUPTS);
> return write_mie(env, CSR_MIE, newval);
> }
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
On Thu, Jan 13, 2022 at 6:45 PM Anup Patel wrote:
> On Wed, Jan 12, 2022 at 8:30 AM Frank Chang
> wrote:
> >
> > On Wed, Jan 12, 2022 at 1:18 AM Anup Patel wrote:
> >>
> >>
> >>
> >> On Mon, Jan 10, 2022 at 6:38 PM Frank Chang
> w
h sluggish response to serial console input and other I/O
> events.
> +*
> +* To solve this, we check and inject interrupt after setting V=1.
> +*/
> +riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> +}
> }
>
> bool riscv_cpu_two_stage_lookup(int mmu_idx)
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
Anup Patel 於 2021年12月30日 週四 下午9:00寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for MSIs (message signal interrupts) called
> IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
> is per-HART device and also suppport
+} else {
> +qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
> +"riscv,cpu-intc");
> + }
> qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller",
> NULL, 0);
> qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
/* VS-Level Interrupts (H-extension with AIA) */
> [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index f027d5e307..376a02a36f 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -103,6 +103,7 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.vscause, RISCVCPU),
> VMSTATE_UINTTL(env.vstval, RISCVCPU),
> VMSTATE_UINTTL(env.vsatp, RISCVCPU),
> +VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
>
> VMSTATE_UINTTL(env.mtval2, RISCVCPU),
> VMSTATE_UINTTL(env.mtinst, RISCVCPU),
> @@ -210,6 +211,8 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mepc, RISCVCPU),
> VMSTATE_UINTTL(env.mcause, RISCVCPU),
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> +VMSTATE_UINTTL(env.miselect, RISCVCPU),
> +VMSTATE_UINTTL(env.siselect, RISCVCPU),
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
interrupts.
> +
> +- aia-guests=nnn
> +
> + The number of per-HART VS-level AIA IMSIC pages to be emulated for a
> guest
> + having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
> + the default number of per-HART VS-level AIA IMSIC pages is 0.
> +
> Running Linux kernel
>
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
u.h b/target/riscv/cpu.h
> index 82272f99fd..0b24c4324b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -362,6 +362,7 @@ struct RISCVCPU {
> bool mmu;
> bool pmp;
> bool epmp;
> +bool aia;
> uint64_t resetvec;
> } cfg;
> };
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL,
> rmw_hviph },
> +[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
> write_hviprio1h },
> +[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
> write_hviprio2h },
> [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL,
> rmw_vsieh },
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL,
> rmw_vsiph },
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 44dca84ded..f027d5e307 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> +
> +VMSTATE_UINTTL(env.hvictl, RISCVCPU),
> VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
>
> VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> --
> 2.25.1
>
>
>
Otherwise,
Reviewed-by: Frank Chang
define VIRT_CPUS_MAX_BITS 3
> +#define VIRT_CPUS_MAX_BITS 9
> #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
> #define VIRT_SOCKETS_MAX_BITS 2
> #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
k),
> + void *rmw_fn_arg)
> +{
> +if (priv <= PRV_M) {
> +env->aia_ireg_rmw_fn[priv] = rmw_fn;
> +env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
> +}
> +}
> +
> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> {
> if (newpriv > PRV_M) {
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
c..1bdd03731f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -344,6 +344,11 @@ static inline bool riscv_feature(CPURISCVState *env,
> int feature)
> return env->features & (1ULL << feature);
> }
>
> +static inline void riscv_set_feature(CPURISCVState *env, int feature)
> +{
> +env->features |= (1ULL << feature);
> +}
> +
> #include "cpu_user.h"
>
> extern const char * const riscv_int_regnames[];
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
> 2))
> +#define IPRIO_DEFAULT_48_63(_i)\
> +(IPRIO_DEFAULT_MMAXIPRIO - (8 + (IPRIO_DEFAULT_L(_i) >> 2)))
> +
> +/* HVICTL bits (AIA) */
> +#define HVICTL_VTI 0x4000
> +#define HVICTL_IID 0x0fff
> +#define HVICTL_IPRIOM 0x0100
> +#define HVICTL_IPRIO 0x00ff
> +#define HVICTL_VALID_MASK \
> +(HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
> +
> #endif
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -75,7 +75,8 @@ enum {
> RISCV_FEATURE_MMU,
> RISCV_FEATURE_PMP,
> RISCV_FEATURE_EPMP,
> -RISCV_FEATURE_MISA
> +RISCV_FEATURE_MISA,
> +RISCV_FEATURE_AIA
> };
>
> #define PRIV_VERSION_1_10_0 0x00011000
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
if (riscv_cpu_virt_enabled(env)) {
> +if (!riscv_cpu_virt_enabled(env)) {
> return RISCV_EXCP_ILLEGAL_INST;
> } else {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
rotection and Translation */
> [CSR_SATP] = { "satp", smode, read_satp,write_satp },
>
> +/* Supervisor-Level Interrupts (AIA) */
> +[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
> +
> /* Supervisor-Level High-Half CSRs (AIA) */
> [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> @@ -2454,6 +2607,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_HVIPRIO1]= { "hviprio1",aia_hmode, read_hviprio1,
> write_hviprio1 },
> [CSR_HVIPRIO2]= { "hviprio2",aia_hmode, read_hviprio2,
> write_hviprio2 },
>
> +/* VS-Level Interrupts (H-extension with AIA) */
> +[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
> +
> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
On Wed, Jan 12, 2022 at 1:18 AM Anup Patel wrote:
>
>
> On Mon, Jan 10, 2022 at 6:38 PM Frank Chang
> wrote:
> >
> > Anup Patel 於 2021年12月30日 週四 下午8:38寫道：
> >>
> >> From: Anup Patel
> >>
> >> The AIA spec defines programmable 8-bit
-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> +[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL,
> rmw_hviph },
> [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
> write_hviprio1h },
> [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
> write_hviprio2h },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
} else if (irq == IRQ_S_GEXT) {
> +iprio = IPRIO_DEFAULT_SGEXT;
> +} else if (irq == IRQ_S_EXT || irq == IRQ_S_TIMER ||
> + irq == IRQ_S_SOFT) {
> +iprio = IPRIO_DEFAULT_S;
> +} else if (irq == IRQ_M_EXT || irq == IRQ_M_TIMER ||
ty
number p.
For a major interrupt that defaults to a higher priority than machine
external interrupts,
setting its priority number to a nonzero value lowers its priority.
For a major interrupt that defaults to a lower priority than machine
external interrupts,
setting its priority number to a nonzero value
space_stl_le(_space_memory, addr,
> + eiid, MEMTXATTRS_UNSPECIFIED, );
> +if (result != MEMTX_OK) {
> +qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for "
> + "hart_index=%d guest_index=%d eiid=%d\n",
&g
SCVAPLICState *aplic,
> +uint32_t irq, bool pending)
> +{
> +uint32_t sourcecfg, sm;
> +
> +if ((irq <= 0) || (aplic->num_irqs <= irq)) {
> + return;
> +}
> +
> +sourcecfg = aplic->sourcecfg[irq];
> +i
ret = -EINVAL;
> +bool set, pend, virt;
> +target_ulong priv, isel, vgein, xlen, nval, wmask;
> +
> +/* Translate CSR number for VS-mode */
> +csrno = aia_xlate_vs_csrno(env, csrno);
> +
> +/* Decode register details from CSR number */
> +virt = set =
From: Frank Chang
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1 file changed, 8 insertions(+), 4 deletions
From: Frank Chang
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
From: Frank Chang
For vector widening and narrowing floating-point instructions, we should
use require_scale_rvf() instead of require_rvf() to check whether the
correspond RVF/RVD is enabled if either source or destination
floating-point operand is double-width of SEW. Otherwise, illegal
From: Frank Chang
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use
On Wed, Dec 29, 2021 at 10:43 AM Frank Chang wrote:
> 於 2021年12月29日 週三 上午10:13寫道：
>
>> From: Frank Chang
>>
>> For vector widening and narrowing floating-point instructions, we should
>> use require_scale_rvf() instead of require_rvf() to check whether the
&g
於 2021年12月29日 週三 上午10:13寫道：
> From: Frank Chang
>
> For vector widening and narrowing floating-point instructions, we should
> use require_scale_rvf() instead of require_rvf() to check whether the
> correspond RVF/RVD is enabled if either source or destination
> floating-point
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5e98860a09..2b54c64f56 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -636,6 +636,7 @@ static Property
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/riscv
From: Frank Chang
Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
---
target/riscv/insn_trans
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 01239620ca..38cd11a8ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -636,6 +636,7 @@ static Property
From: Frank Chang
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
---
target/riscv/insn_trans
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans
101 - 200 of 1327 matches
Mail list logo
