; this is unused (and overridden in pick_nan_muladd).
>
> I think for avoidance of confusion, you should use
>
> if (infzero) {
> float_raise(float_flag_invalid, status);
> }
> return 3; /* default nan */
>
>
> r~
>
Sure, I'll update my patch and resend again.
Thanks
Frank Chang
Alistair Francis 於 2021年4月19日 週一 下午2:28寫道：
> On Mon, Apr 19, 2021 at 4:02 PM wrote:
> >
> > From: Frank Chang
> >
> > Doing a negate (0x0 – 0x8000) using vssub.vv produces
> > an incorrect result of 0x8000 (should saturate to 0x7fff)
>
From: Frank Chang
ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 6 --
1 file changed, 4
From: Frank Chang
Doing a negate (0x0 – 0x8000) using vssub.vv produces
an incorrect result of 0x8000 (should saturate to 0x7fff)
Fix this bug by treating zero as a positive number.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 8
1 file changed, 4
From: Frank Chang
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled
This should be a quick fix, we will run couple tests again to ensure the
fix doesn't break anything. Thanks~
** Changed in: qemu
Assignee: (unassigned) => Frank Chang (frankchang0125)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscri
於 2021年4月1日 週四 下午5:27寫道：
> From: Frank Chang
>
> This patchset add suport of Resumable NMI (RNMI) in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumabl
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 1 +
target/riscv/insn32.decode| 3 ++
.../riscv/insn_trans/trans_privileged.c.inc | 13
target/riscv/op_helper.c | 31 +++
4
From: Frank Chang
This patchset add suport of Resumable NMI (RNMI) in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x350)
* mnepc (0x351
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu_bits.h | 4
target/riscv/cpu_helper.c | 49 +++
2 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a376ede0cc5
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 4 +++
target/riscv/cpu_bits.h | 9 +++
target/riscv/csr.c | 59 +
3 files changed, 72 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Frank Chang
Signed-off-by: Frank Chang
---
hw/riscv/riscv_hart.c | 8 +++
include/hw/riscv/riscv_hart.h | 2 ++
target/riscv/cpu.c| 40 +++
target/riscv/cpu.h| 12 ++-
target/riscv/cpu_bits.h | 6
On Fri, Mar 19, 2021 at 9:29 PM Alistair Francis
wrote:
> On Tue, Mar 9, 2021 at 2:30 AM wrote:
> >
> > From: Frank Chang
> >
> > Signed-off-by: Frank Chang
>
> I had a quick look and this looks fine. I haven't compared it to the
> spec yet though.
>
On Fri, Mar 19, 2021 at 9:30 PM Alistair Francis
wrote:
> On Tue, Mar 9, 2021 at 2:31 AM wrote:
> >
> > From: Frank Chang
> >
> > This patchset add suport of Resumable NMI (RNMI) in RISC-V.
> >
> > There are four new CSRs and one new instruction added to
From: Frank Chang
This patchset add suport of Resumable NMI (RNMI) in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x350)
* mnepc (0x351
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c| 40 +
target/riscv/cpu.h| 16 -
target/riscv/cpu_bits.h | 19 ++
target/riscv/cpu_helper.c | 47
From: Frank Chang
rvv v0.10 adds vector unit-stride mask load/store instructions
(vle1.v, vse1.v), which has:
evl (effective vector length) = ceil(env-vl/8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off
From: Frank Chang
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check
From: Frank Chang
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 5 +
target/riscv/helper
From: Frank Chang
Add the following instructions:
* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 11 ++--
target/riscv/insn_trans/trans_rvv.c.inc
From: Frank Chang
Add the following instructions:
* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 2 +
target/riscv/insn32.decode
From: Frank Chang
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index aa76da9e185..e0f1106d909 100644
--- a/target/riscv/csr.c
+++ b/target
From: Frank Chang
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
--
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Frank Chang
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 14 +
target/riscv/insn32.decode | 8
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c5e65720120
From: Frank Chang
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 27 ++---
target
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.c.inc | 40 +
target/riscv/vector_helper.c| 21 +
4 files
From: Frank Chang
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv
From: Frank Chang
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +
1 file changed, 22 insertions(+), 10 deletions
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.c.inc | 30 +
2 files changed, 32 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6fb85c83278
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/csr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0f1106d909..0082db9cc0c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -209,7 +209,7
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index
From: Frank Chang
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fae5ea3fa63..a593938e5c8 100644
--- a/target/riscv
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 1 +
target/riscv/gdbstub.c | 184 +
3 files changed, 187 insertions(+)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +---
target/riscv/vector_helper.c| 12 ++--
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 7 ---
target/riscv/vector_helper.c| 6 +++---
4 files
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +++---
target/riscv/vector_helper.c| 52
From: Frank Chang
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
Signed-off-by: Frank Chang
--
Perhaps we can remove the probe functions in vector_helper.c
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 22 +-
target/riscv/insn32.decode | 15 ---
target/riscv/insn_trans/trans_rvv.c.inc | 58 +
target/riscv/vector_helper.c| 45
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e11666f16df..c0053cfb828
From: Frank Chang
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 16 +++
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 6 --
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.c.inc | 2 --
target/riscv/vector_helper.c| 7 ---
4 files
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 12 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 18 +-
target/riscv/internals.h| 9 +
3 files changed, 24 insertions
From: Frank Chang
Add the following instructions:
* vlre.v
* vsr.v
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 21
target/riscv/insn32.decode | 22
target/riscv/insn_trans/trans_rvv.c.inc | 69
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c| 4
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.c.inc | 23 ---
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.c.inc | 9 --
target/riscv/vector_helper.c| 205
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 100 +++---
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 36 +++-
target/riscv/insn_trans/trans_rvv.c.inc | 229
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 5622fb23f85..93ed6f54e99 100644
--- a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 53 +
target/riscv/vector_helper.c| 14 ++-
2 files changed, 31 insertions(+), 36 deletions(-)
diff
From: Frank Chang
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 022530697ec..8467dfc84b1 100644
--- a/target/riscv
From: Frank Chang
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 16 ++
target/riscv/insn32.decode
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +-
target/riscv/insn_trans/trans_rvv.c.inc | 30 -
target/riscv
From: Frank Chang
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 732
1 file changed, 499 insertions(+), 233 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 20 ++--
target/riscv/insn_trans
From: Frank Chang
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.c.inc | 25 +
2 files changed, 29 insertions(+)
diff --git
From: Frank Chang
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 10 --
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4 +--
target/riscv/insn_trans/trans_rvv.c.inc | 39 +
target/riscv/internals.h| 5
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv
From: Frank Chang
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed
From: Frank Chang
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.c.inc | 45
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c0053cfb828..a0a47dbceb3
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 5 -
target/riscv/vector_helper.c| 4
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git
From: Frank Chang
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 6 +++---
4 files changed
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
target/riscv/vector_helper.c| 90 ++---
2 files changed, 74 insertions(+), 48 deletions(-)
diff --git a/target/riscv
From: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target
From: Frank Chang
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting
From: Frank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 43 ++---
target/riscv
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 8
1 file changed, 4
From: Frank Chang
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW
From: Frank Chang
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 69 -
target/riscv/translate.c| 33
2 files changed, 90
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 27 +++-
target/riscv/insn32.decode | 14 +++
target/riscv/insn_trans/trans_rvv.c.inc | 33 ---
target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 67
target/riscv/insn32.decode | 21 ++-
target/riscv/insn_trans/trans_rvv.c.inc | 209
target/riscv/vector_helper.c
From: Frank Chang
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 35 +---
target/riscv
From: Frank Chang
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 129 +++---
target/riscv/insn32.decode | 43 +++--
target/riscv/insn_trans/trans_rvv.c.inc | 227 +++-
target/riscv
From: Frank Chang
* Remove VXRM and VXSAT fields from FCSR register as they are only
presented in VCSR register.
* Remove RVV loose check in fs() predicate function.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 13
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c | 21 +
2 files changed, 28 insertions(+)
diff --git a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a156573d281
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 7 +++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 ++-
target/riscv/csr.c| 25
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 10 +-
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Frank Chang
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
The port is available here:
https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7
You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0)
to run with RVV v1.0 instructions.
Note
On Wed, Feb 24, 2021 at 2:24 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 2/23/21 12:19 AM, frank.ch...@sifive.com wrote:
> > From: Frank Chang
> >
> > TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> > commit: c445593, but ot
From: Frank Chang
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 12
From: Frank Chang
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.
If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault inst
>
> The separation between the FIELDs and TB_FLAG_*_MASK is unfortunate, and
> will
> be a continuing source of errors.
>
>
Sure, I will edit it and send out the next version patch.
Thanks,
Frank Chang
>
> r~
>
From: Frank Chang
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 11 ++-
1
On Tue, Jan 26, 2021 at 7:54 AM Alistair Francis
wrote:
> On Tue, Jan 12, 2021 at 2:50 AM wrote:
> >
> > From: Hsiangkai Wang
> >
> > Signed-off-by: Hsiangkai Wang
> > Acked-by: Richard Henderson
> > Signed-off-by: Frank Chang
>
> Thi
On Wed, Jan 20, 2021 at 3:12 AM Alistair Francis
wrote:
> On Tue, Jan 12, 2021 at 1:40 AM wrote:
> >
> > From: Frank Chang
> >
> > This patchset implements the vector extension v1.0 for RISC-V on QEMU.
> >
> > As vector extension specificatio
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 22 ++
target/riscv/translate.c| 6 ++
3 files changed
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 36 +
target/riscv
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