RE: [PATCH v1 23/36] target/riscv: Add hypvervisor trap support

From: Qemu-riscv [mailto:qemu-riscv- > bounces+jiangyifei=huawei@nongnu.org] On Behalf Of Alistair Francis > Sent: Tuesday, December 10, 2019 2:12 AM > To: qemu-devel@nongnu.org; qemu-ri...@nongnu.org > Cc: alistair.fran...@wdc.com; pal...@dabbelt.com; alistai...@gmail.com >

RE: [PATCH RFC 0/9] Add riscv64 kvm accel support

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Friday, March 13, 2020 2:00 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V ri...@nongnu.org>; Anup Patel ; Zhanghailiang > ; Sagar Karandikar > ; Bastian Koppelmann pade

RE: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Tuesday, March 31, 2020 7:19 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; Anup Patel ; > Zhanghailiang ; Sagar Karandikar > ; Bastian Koppelmann > ; Zhangxiaofe

RE: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Tuesday, March 31, 2020 1:17 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V ri...@nongnu.org>; Anup Patel ; Zhanghailiang > ; Sagar Karandikar > ; Bastian Koppelmann pade

RE: [PATCH V3] target/riscv: raise exception to HS-mode at get_physical_address

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Thursday, October 15, 2020 4:22 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: pal...@dabbelt.com; alistair.fran...@wdc.com; > sag...@eec

RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Thursday, October 15, 2020 3:12 AM > To: Richard Henderson > Cc: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org; Zhanghailiang ; > sag...@eecs.berkeley.edu; kbast...@

RE: [PATCH 1/5] target/riscv: Add basic vmstate description of CPU

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Friday, October 2, 2020 1:23 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: Zhanghailiang ; > sag...@eecs.berkeley.edu; kbast...@mail.uni-paderb

RE: [PATCH] target/riscv: raise exception to HS-mode at get_physical_address

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Thursday, October 1, 2020 8:00 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Zhanghailiang > ; Sagar Karandikar > ; Bastian Koppelm

RE: [PATCH 3/5] target/riscv: Add H extention state description

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Friday, October 2, 2020 1:28 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: Zhanghailiang ; > sag...@eecs.berkeley.edu; kbast...@mail.uni-paderb

RE: [PATCH 2/5] target/riscv: Add PMP state description

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Tuesday, October 6, 2020 6:11 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Zhanghailiang > ; Sagar Karandikar > ; Bastian Koppelm

RE: [PATCH V2] target/riscv: raise exception to HS-mode at get_physical_address

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Friday, October 9, 2020 10:34 PM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: Zhanghailiang ; > sag...@eecs.berkeley.edu; kbast...@mail.uni-paderb

RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Saturday, October 10, 2020 9:23 PM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: pal...@dabbelt.com; alistair.fran...@wdc.com; > sag...@eec

RE: [PATCH] target/riscv: raise exception to HS-mode at get_physical_address

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Saturday, September 26, 2020 6:24 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Zhanghailiang > ; Sagar Karandikar > ; Bastian Koppelm

RE: [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit

> -Original Message- > From: Jiangyifei > Sent: Friday, October 23, 2020 5:12 PM > To: qemu-devel@nongnu.org; qemu-ri...@nongnu.org > Cc: pal...@dabbelt.com; alistair.fran...@wdc.com; > sag...@eecs.berkeley.edu; kbast...@mail.uni-paderborn.de; > richard

RE: [PATCH RFC v4 06/15] target/riscv: Support start kernel directly by KVM

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Wednesday, December 9, 2020 6:19 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Zhangxiaofeng (F) > ; Sagar Karandikar > ; open list:Overall ;

RE: [PATCH RFC v4 09/15] target/riscv: Add host cpu type

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Wednesday, December 9, 2020 6:22 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Zhangxiaofeng (F) > ; Sagar Karandikar > ; open list:Overall ;

RE: [PATCH RFC v4 07/15] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Wednesday, December 9, 2020 6:30 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Zhangxiaofeng (F) > ; Sagar Karandikar > ; open list:Overall ;

RE: [PATCH RFC v4 13/15] target/riscv: Introduce dynamic time frequency for virt machine

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Wednesday, December 9, 2020 6:26 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; Zhangxiaofeng (F) > ; Sagar Karandikar > ; open list:Overall ;

RE: [PATCH v2 1/1] target-riscv: support QMP dump-guest-memory

> -Original Message- > From: Andrew Jones [mailto:drjo...@redhat.com] > Sent: Sunday, January 10, 2021 5:39 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org; qemu-ri...@nongnu.org; Zhanghailiang > ; sag...@eecs.berkeley.edu; > kbast...@mail.uni-paderborn

RE: [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled

> -Original Message- > From: Qemu-riscv > [mailto:qemu-riscv-bounces+jiangyifei=huawei@nongnu.org] On Behalf Of > Anup Patel > Sent: Friday, April 30, 2021 12:54 PM > To: Jiangyifei > Cc: Bin Meng ; open list:RISC-V > ; Sagar Karandikar ; > KVM Gener

RE: [PATCH RFC v6 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

> -Original Message- > From: Qemu-riscv > [mailto:qemu-riscv-bounces+jiangyifei=huawei@nongnu.org] On Behalf Of > Alistair Francis > Sent: Thursday, August 19, 2021 2:14 PM > To: Jiangyifei > Cc: Anup Patel ; open list:RISC-V > ; open list:Overall ; >

RE: [PATCH v2 07/12] target/riscv: Support setting external interrupt by KVM

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Monday, December 13, 2021 12:33 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; Anup Patel > ; P

RE: [PATCH v2 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Monday, December 13, 2021 11:20 PM > To: Anup Patel ; Jiangyifei > Cc: Bin Meng ; open list:RISC-V > ; limingwang (A) ; KVM > General ; libvir-l...@redhat.com; Anup Pate

RE: [PATCH v2 06/12] target/riscv: Support start kernel directly by KVM

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Monday, December 13, 2021 12:21 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; Anup Patel > ; P

RE: [PATCH v2 12/12] target/riscv: Support virtual time context synchronization

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Monday, December 13, 2021 11:22 PM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: kvm-ri...@lists.infradead.org; k...@vger.kernel.org; > libvir-l..

RE: [PATCH v1 06/12] target/riscv: Support start kernel directly by KVM

> -Original Message- > From: kvm-riscv [mailto:kvm-riscv-boun...@lists.infradead.org] On Behalf Of > Anup Patel > Sent: Friday, December 3, 2021 2:31 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General >

RE: [PATCH v1 07/12] target/riscv: Support setting external interrupt by KVM

> -Original Message- > From: kvm-riscv [mailto:kvm-riscv-boun...@lists.infradead.org] On Behalf Of > Anup Patel > Sent: Friday, December 3, 2021 5:15 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General >

RE: [PATCH v1 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Friday, December 3, 2021 5:38 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; Anup Patel > ; P

RE: [PATCH v1 12/12] target/riscv: Support virtual time context synchronization

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Sunday, November 21, 2021 6:35 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: bin.m...@windriver.com; limingwang (A) ; > k...@vger.kernel.org; l

RE: [PATCH v1 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

> -Original Message- > From: Philippe Mathieu-Daudé [mailto:philippe.mathieu.da...@gmail.com] > On Behalf Of Philippe Mathieu-Daudé > Sent: Saturday, November 20, 2021 8:25 PM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: bin.m...@wind

RE: [PATCH v1 04/12] target/riscv: Implement kvm_arch_get_registers

> -Original Message- > From: kvm-riscv [mailto:kvm-riscv-boun...@lists.infradead.org] On Behalf Of > Anup Patel > Sent: Friday, December 3, 2021 2:20 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General >

RE: [PATCH v1 05/12] target/riscv: Implement kvm_arch_put_registers

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Friday, December 3, 2021 2:22 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; Anup Patel > ; P

RE: [PATCH v1 03/12] target/riscv: Implement function kvm_arch_init_vcpu

> -Original Message- > From: Richard Henderson [mailto:richard.hender...@linaro.org] > Sent: Sunday, November 21, 2021 6:19 AM > To: Jiangyifei ; qemu-devel@nongnu.org; > qemu-ri...@nongnu.org > Cc: bin.m...@windriver.com; limingwang (A) ; > k...@vger.kernel.org; l

RE: [PATCH v3 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Thursday, January 6, 2022 6:04 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; kvm-ri...@lists.infradead.org; open > list:Overall ; libvir-l...@r

RE: [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM

> -Original Message- > From: Anup Patel [mailto:a...@brainfault.org] > Sent: Thursday, December 23, 2021 2:04 PM > To: Jiangyifei > Cc: QEMU Developers ; open list:RISC-V > ; kvm-ri...@lists.infradead.org; KVM General > ; libvir-l...@redhat.com; Anup Patel > ; P

RE: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Tuesday, January 11, 2022 7:07 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; kvm-ri...@lists.infradead.org; open > list:Overall ; libvir-l...@r

RE: [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Tuesday, January 11, 2022 7:10 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; kvm-ri...@lists.infradead.org; open > list:Overall ; libvir-l...@r

RE: [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Tuesday, January 11, 2022 8:28 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; kvm-ri...@lists.infradead.org; open > list:Overall ; libvir-l...@r