Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Reviewed-by: Ira Weiny
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads, but only via the
mailbox command Get Poison List. So a normal memory read to an address
that is on the poison list will not yet result in a synchronous
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32 bit host native value.
The use of b, w, l, q as the size specifier is limiting. So "24" was
used for
From: Ira Weiny
There are new users of this functionality coming shortly so factor
it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v5: No change.
---
hw/cxl/cxl-device-utils.c | 15 +++
v5: More details in each patch.
- Simpler algorithm to find entry when clearing.
- Improvements to debugability and docs for 24 bit endian functions.
- Use of ROUND_DOWN() to simplify the various alignment questions.
- Use CXL_CACHELINE_SIZE define to explain the mysterious 64 byte
Given the increasing usage of this mailbox return code type, now
is a good time to switch to QEMU style naming.
Reviewed-by: Ira Weiny
Reviewed-by: Fan Ni
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
v5: Picked up Philippe's tag.
---
hw/cxl/cxl-mailbox-utils.c |
On Tue, 14 Mar 2023 07:27:52 +0100
Philippe Mathieu-Daudé wrote:
> On 3/3/23 16:09, Jonathan Cameron wrote:
> > Very simple implementation to allow testing of corresponding
> > kernel code. Note that for now we track each 64 byte section
> > independently. Whilst a valid implementation choice,
This patch and the problem it is trying to resolve will form part of a talk
I will be giving next week at Linaro Connect. https://sched.co/1K85p
So in the spirit of giving people almost no warning... Plus being able to
say the discussion has kicked off here is the simplest solution I could
come
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been
Accessors prefered over direct use of int128_get64() as they
clamp out of range values. None are expected here but
cleaner to always use the accessor than mix and match.
Signed-off-by: Jonathan Cameron
---
v5: New patch to tidy up existing instance before adding more of
them.
- Use
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84
v5: Thanks to Michael Tsirkin for review
- Use memory_region_size() instead of incorrect open coding.
Add a precursor patch tidying up existing uses.
Depends on some of the fix series posted (mostly fuzz).
[PATCH 0/2] hw/cxl: CDAT file handling fixes.
[PATCH v2 0/3] hw/cxl: Fix decoder
On Fri, 21 Apr 2023 03:25:45 -0400
"Michael S. Tsirkin" wrote:
> On Fri, Mar 03, 2023 at 03:28:56PM +, Jonathan Cameron wrote:
> > Whilst I'm an optimist, I suspect this is now 8.1 material because we have
> > 5 CXL patch sets outstanding before it. Current bottleneck being QAPI review
> >
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Reviewed-by: Fan Ni
Tested-by: Fan Ni
Reviewed-by: Dave
Not a real problem yet as all supported architectures are
little endian, but continue to tidy these up when touching
code for other reasons.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
v2:
- Split patch so the memory_region_transaction_* calls are dropped first.
---
Not clear what intent was here, but probably based on a misunderstanding
of what these guards are for.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c
v2:
- Split dropping the transaction guards out as precursor (Phillipe)
- Picked up tags
Issue reported in discussion of:
https://lore.kernel.org/all/20230228224014.1402545-1-fan...@samsung.com/
The committed bit for HDM decoders is expected reset when commit transitions
from 1->0. Whilst
On Fri, 21 Apr 2023 19:14:05 +0530
RAGHU H wrote:
> Hi Jonathan,
>
> The log is from the upstream version.
> I have your repo, I can work on it if you provide some basic details
> like the commit ID.
I tag the latest branch with cxl--MM-DD
https://gitlab.com/jic23/qemu cxl-2023-04-19
From: Raghu H
Currently Qemu CXL emulation support is not availabe on AARCH64 but its
available with qemu x86_64 architecture, updating the document to reflect
the supported platform.
Signed-off-by: Raghu H
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 6 +++---
1 file
From: Raghu H
cxl-type3 memory size is read directly from the provided memory backed end
device. Remove non existent size option
Signed-off-by: Raghu H
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Brice Goglin
Signed-off-by: Brice Goglin
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index f25783a4ec..b65480af6f 100644
---
Some documentation fixes that were on the CXL staging tree that
for upstream now 8.1 cycle has started.
Brice Goglin (1):
docs/cxl: fix some typos
Raghu H (2):
docs/cxl: Remove incorrect CXL type 3 size parameter
docs/cxl: Replace unsupported AARCH64 with x86_64
The failure paths in CDAT file loading did not clear up properly.
Change to using g_auto_free and a local pointer for the buffer to
ensure this function has no side effects on error.
Also drop some unnecessary checks that can not fail.
Cleanup properly after a failure to load a CDAT file.
hieu-Daudé
Suggested-by: Peter Maydell
Suggested-by: Jonathan Cameron via
Signed-off-by: Jonathan Cameron
--
Changes since v5:
- Drop if guard on g_free() as per checkpatch warning.
---
hw/cxl/cxl-cdat.c | 29 -
1 file changed, 8 insertions(+), 21 deletions(-)
diff
I've picked up Hao Zeng's v5 and added a patch to deal with the
issues that Peter pointed out in this area.
On error, the CDAT file handling left resource dangling and didn't
cleanly exit from calling functions. Hao Zeng dealt with closing
the file. The second patch deals with the buffer
ation")
> Signed-off-by: Zeng Hao
> Suggested-by: Philippe Mathieu-Daudé
> Suggested-by: Peter Maydell
> Suggested-by: Jonathan Cameron via
>
> ---
> ChangeLog:
> v4-v5:
> fixes some style issues and keep the protection after using g_free()
> v3
On Thu, 20 Apr 2023 18:07:40 +0530
RAGHU H wrote:
> Hello,
>
> I am using qemu config listed in CXL documentation to emulate CXL device
>
>
> -object
> memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M
> \
> -object
>
On Thu, 20 Apr 2023 16:57:18 +0100
Alex Bennée wrote:
> From: Stefan Weil via
>
> Signed-off-by: Stefan Weil
> Reviewed-by: Richard Henderson
> Acked-by: Jonathan Cameron
> Message-Id: <20230409201828.1159568-1...@weilnetz.de>
> Signed-off-by: Alex Bennée
Thomas already sent a pull
The lifetime of the PCIBridgeWindows instance accessed via the windows pointer
in struct PCIBridge is managed separately from the PCIBridge itself.
Triggered by ./qemu-system-x86_64 -M x-remote -display none -monitor stdio
QEMU monitor: device_add cxl-downstream
In some error handling paths
On Fri, 21 Apr 2023 09:59:57 +0100
Peter Maydell wrote:
> On Fri, 21 Apr 2023 at 09:19, Michael S. Tsirkin wrote:
> >
> > On Thu, Apr 20, 2023 at 03:27:48PM +0100, Jonathan Cameron wrote:
> > > Peter Maydell highlighted an incorrect conversion to TYPE_PXB_DEVICE from
> > > a device that
On Fri, 21 Apr 2023 08:26:43 +0200
Philippe Mathieu-Daudé wrote:
> Hi Jonathan,
>
> On 20/4/23 16:59, Jonathan Cameron via wrote:
> > The lifetime of the PCIBridgeWindows instance accessed via the windows
> > pointer
> > in struct PCIBridge is managed separatel
This was intended to be [RFC] for reasons given below.
+ I failed to CC Thomas who reported the issue. Not my finest hour.
On Thu, 20 Apr 2023 15:59:37 +0100
Jonathan Cameron wrote:
> The lifetime of the PCIBridgeWindows instance accessed via the windows pointer
> in struct PCIBridge is
The lifetime of the PCIBridgeWindows instance accessed via the windows pointer
in struct PCIBridge is managed separately from the PCIBridge itself.
Triggered by ./qemu-system-x86_64 -M x-remote -display none -monitor stdio
QEMU monitor: device_add cxl-downstream
In some error handling paths
Previously, PXB_CXL_DEVICE, PXB_PCIE_DEVICE and PXB_DEVICE all
have PCI_DEVICE as their direct parent but share a common state
struct PXBDev. convert_to_pxb() is used to get the PXBDev
instance from which ever of these types it is called on.
This patch switches to an explicit heirarchy based on
Reproduce issue with
configure --enable-qom-cast-debug ...
qemu-system-x86_64 -display none -machine q35,cxl=on -device pxb-cxl,bus=pcie.0
hw/pci-bridge/pci_expander_bridge.c:54:PXB_DEV: Object 0x5570e0b1ada0 is not
an instance of type pxb
Aborted
The type conversion results in the right
Peter Maydell highlighted an incorrect conversion to TYPE_PXB_DEVICE from
a device that didn't have that a an ancestor type. PXB_DEV() used instead of
PXB_CXL_DEV()/
https://lore.kernel.org/qemu-devel/cafeaca-+de+eelce4ysaw1o-qyd_4w1ra05mgdsu_-3a6d9...@mail.gmail.com/
During the discussion it
On Wed, 19 Apr 2023 17:25:17 +0100
Peter Maydell wrote:
> On Wed, 19 Apr 2023 at 15:50, Jonathan Cameron
> wrote:
> >
> > On Wed, 19 Apr 2023 14:57:54 +0100
> > Jonathan Cameron via wrote:
> >
> > > On Tue, 11 Apr 2023 11:26:16 +0100
>
On Wed, 19 Apr 2023 14:57:54 +0100
Jonathan Cameron via wrote:
> On Tue, 11 Apr 2023 11:26:16 +0100
> Peter Maydell wrote:
>
> > On Wed, 8 Mar 2023 at 01:14, Michael S. Tsirkin wrote:
> > >
> > > From: Jonathan Cameron
> > >
> > > The C
On Tue, 11 Apr 2023 11:26:16 +0100
Peter Maydell wrote:
> On Wed, 8 Mar 2023 at 01:14, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > The CXL r3.0 specification allows for there to be no HDM decoders on CXL
> > Host Bridges if they have only a single root port. Instead, all
On Mon, 17 Apr 2023 15:04:41 +0200
Thomas Huth wrote:
> On 17/04/2023 13.29, Michael S. Tsirkin wrote:
> > On Mon, Apr 17, 2023 at 01:22:51PM +0200, Thomas Huth wrote:
> >> On 11/04/2023 12.26, Peter Maydell wrote:
> >>> On Wed, 8 Mar 2023 at 01:14, Michael S. Tsirkin wrote:
>
>
On Thu, 13 Apr 2023 17:33:28 +0800
Hao Zeng wrote:
> opened file processor not closed,May cause file processor leaks
Patch description needs to say more on how this is fixed.
Perhaps something like:
"Open file descriptor not closed in error paths. Fix by replace
open coded handling of read of
On Thu, 6 Apr 2023 18:58:37 +0530
Raghu H wrote:
> Thanks Jonathan for quick review/comments on earlier patch, as suggested
> splitting into two separate patches
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg952999.html
>
> Removed the unsupported size option for cxl-type3 device,
On Tue, 11 Apr 2023 16:52:58 +0100
Peter Maydell wrote:
> On Mon, 7 Nov 2022 at 22:49, Michael S. Tsirkin wrote:
> >
> > From: Huai-Cheng Kuo
> >
> > The Data Object Exchange implementation of CXL Coherent Device Attribute
> > Table (CDAT). This implementation is referring to "Coherent Device
On Tue, 11 Apr 2023 16:52:58 +0100
Peter Maydell wrote:
> On Mon, 7 Nov 2022 at 22:49, Michael S. Tsirkin wrote:
> >
> > From: Huai-Cheng Kuo
> >
> > The Data Object Exchange implementation of CXL Coherent Device Attribute
> > Table (CDAT). This implementation is referring to "Coherent Device
On Wed, 12 Apr 2023 12:02:47 +0200
Philippe Mathieu-Daudé wrote:
> On 12/4/23 09:16, Hao Zeng wrote:
> > The bug in this code (CID 1507822) is that the
> > check on the return value of fread() is wrong. fread()
> > returns the number of items read or written, so
> > checking for == 0 only
On Sun, 9 Apr 2023 22:18:28 +0200
Stefan Weil wrote:
> Signed-off-by: Stefan Weil
Acked-by: Jonathan Cameron
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/devices/cxl.rst | 2 +-
> 1 file
On Wed, 5 Apr 2023 15:57:38 +0530
Raghu H wrote:
Hi Raghu,
Thanks for tidying this up! (and reporting it in the first place)
A few minor comments for v2.
A better title might be
docs/cxl: Remove incorrect CXL type 3 size parameter.
> cxl device typ3 size is read from the memory backend
On Fri, 17 Mar 2023 16:54:36 +
Jonathan Cameron via wrote:
> Michael Tsirkin raised that we have recently had churn in the bios-tables-test
> and perhaps it was worth factoring some parts of DSDT out as SSDT files.
> This is an attempt to do that for the entries from pxb-pcie an
On Fri, 24 Mar 2023 11:17:50 +0100
Thomas Huth wrote:
> On 07/12/2022 14.26, Thomas Huth wrote:
> > On 07/12/2022 14.21, Jonathan Cameron wrote:
> >> On Mon, 05 Dec 2022 14:59:39 +
> >> Alex Bennée wrote:
> >>
> >>> Jonathan Cameron via
On Mon, 3 Apr 2023 16:03:20 +0530
Maverickk 78 wrote:
> Hi Jonathan
>
> Do you want me to modify the doc(remove size)? I can do that.
That would be great. Also whilst there, a second patch to modify
the architecture to be x86_64 would be good.
Thanks,
Jonathan
>
> Regards
> Raghu
>
> On
On Mon, 3 Apr 2023 14:34:33 +0530
Maverickk 78 wrote:
> Hello,
>
> I am trying qemu-system-aarch64 & cxl configuration listed in
>
> https://www.qemu.org/docs/master/system/devices/cxl.html
>
> qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8
> -cpu max \
> ...
>
On Fri, 24 Mar 2023 04:32:52 +0530
Maverickk 78 wrote:
> Hello Jonathan
>
> Raghu here, I'm going over your cxl patches for past few days, it's very
> impressive.
>
> I want to get involved and contribute in your endeavor, may be bits &
> pieces to start.
>
> If you're specific trivial
On Wed, 22 Mar 2023 16:21:26 +
Fan Ni wrote:
> On Wed, Mar 22, 2023 at 10:33:00AM +, Jonathan Cameron wrote:
> > The hardware clearing the commit bit is not spec compliant.
> > Clearing of committed bit when commit is cleared is not specifically
> > stated in the CXL spec, but is the
Issue reported in discussion of:
https://lore.kernel.org/all/20230228224014.1402545-1-fan...@samsung.com/
The committed bit for HDM decoders is expected reset when commit transitions
from 1->0. Whilst looking at that it was noticed that hardware was resetting
the commit bit which is not an
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Signed-off-by: Jonathan Cameron
---
On Mon, 20 Mar 2023 23:08:31 -0700
Dan Williams wrote:
> While it was a reasonable idea to specify no window restricitions at the
> outset of the CXL emulation support, it turns out that in practice a
> platform will never follow the QEMU example of specifying simultaneous
> support for HDM-H
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Signed-off-by: Jonathan Cameron
---
The hardware clearing the commit bit is not spec compliant.
Clearing of committed bit when commit is cleared is not specifically
stated in the CXL spec, but is the expected (and simplest) permitted
behaviour so use that for QEMU emulation.
Signed-off-by: Jonathan Cameron
---
On Tue, 21 Mar 2023 19:28:02 +
Fan Ni wrote:
> On Tue, Mar 21, 2023 at 06:00:11PM +, Jonathan Cameron wrote:
> > Not a real problem yet as all supported architectures are
> > little endian, but continue to tidy these up when touching
> > code for other reasons.
> >
> > Signed-off-by:
Not a real problem yet as all supported architectures are
little endian, but continue to tidy these up when touching
code for other reasons.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 10 --
hw/mem/cxl_type3.c | 9 ++---
2 files changed, 10
Resending because all but patch 1 seem to have failed to make it out of
our network.
Issue reported in discussion of:
https://lore.kernel.org/all/20230228224014.1402545-1-fan...@samsung.com/
The committed bit for HDM decoders is expected reset when commit transitions
from 1->0. Whilst looking
Not a real problem yet as all supported architectures are
little endian, but continue to tidy these up when touching
code for other reasons.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 10 --
hw/mem/cxl_type3.c | 9 ++---
2 files changed, 10
On Fri, 17 Mar 2023 16:37:20 +
Jonathan Cameron via wrote:
> On Fri, 17 Mar 2023 00:11:10 +0530
> Maverickk 78 wrote:
>
> > Hi
> >
> > I am trying mctp & mctpd with aspeed +buildroot(master) + linux v6.2
> > with Qemu 7.2.
> >
> >
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/DSDT.cxl| Bin 9673 -> 8474 bytes
tests/data/acpi/q35/DSDT.viot | Bin 9470 -> 8429 bytes
tests/data/acpi/q35/SSDT.cxl| Bin 0 -> 1235 bytes
tests/data/acpi/q35/SSDT.viot | Bin 0
The dependencies between the CRS entries and bus numbers due to
PCI eXpander Bridges taking resources from the primary bus make this
a slightly complex dance.
The rules we have to fit into are:
1) FACP is first table in RSDT and points to the DSDT.
2) Thus DSDT is created before FACP
3) SSDT must
Splitting the PXB parts out of DSDT will change these files.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/SSDT.cxl| 0
tests/data/acpi/q35/SSDT.viot | 0
tests/qtest/bios-tables-test-allowed-diff.h | 4
3 files changed, 4 insertions(+)
diff --git
This allows the same code to be used for two purposes.
1) To fill in the crs_range_set as is later used to
generate the actual AML for the primary PCI host bridge.
2) Create the _CRS AML for the PXB bridges.
The separation is need to allow for DSDT to be generated
before an SSDT for any PXB
Michael Tsirkin raised that we have recently had churn in the bios-tables-test
and perhaps it was worth factoring some parts of DSDT out as SSDT files.
This is an attempt to do that for the entries from pxb-pcie and pxb-cxl
PCI root bridges.
The main PCI root bridge and related elements are left
On Fri, 17 Mar 2023 00:11:10 +0530
Maverickk 78 wrote:
> Hi
>
> I am trying mctp & mctpd with aspeed +buildroot(master) + linux v6.2
> with Qemu 7.2.
>
>
> I have added necessary FMAPI related patches into QEMU to support CLX
> switch emulation
>
>
> > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> > index 7e5ad65c1d..d589f78202 100644
> > --- a/include/hw/cxl/cxl_device.h
> > +++ b/include/hw/cxl/cxl_device.h
> > @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> >
On Fri, 3 Mar 2023 15:09:08 +
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
Another case in here of directly accessing MemoryRegion->size.
I'll fix
...
> > +if (vmr) {
> > +if (*dpa_offset < int128_get64(vmr->size)) {
> > +*as = >hostvmem_as;
> > +} else {
> > +*as = >hostpmem_as;
> > +*dpa_offset -= vmr->size;
>
> You can't do math on vmr->size, it's Int128.
> And generally please
On Fri, 3 Mar 2023 22:47:20 -0800
Ira Weiny wrote:
> Jonathan Cameron wrote:
> > Current implementation is very simple so many of the corner
> > cases do not exist (e.g. fragmenting larger poison list entries)
>
> One coding style change at the bottom and I'm still hung up on that loop
>
These events include a copy of the device health information at the
time of the event. Actually using the emulated device health would
require a lot of controls to manipulate that state. Given the aim
of this injection code is to just test the flows when events occur,
inject the contents of the
Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
provides information related to DRAM devices.
Example injection command in QMP:
{ "execute": "cxl-inject-dram-event",
"arguments": {
"path": "/machine/peripheral/cxl-mem0",
"log": "informational",
"flags":
From: Ira Weiny
To facilitate testing provide a QMP command to inject a general media
event. The event can be added to the log specified.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
v4:
* Fix endian conversion on physaddr.
---
hw/mem/cxl_type3.c | 111
From: Ira Weiny
CXL testing is benefited from an artificial event log injection
mechanism.
Add an event log infrastructure to insert, get, and clear events from
the various logs available on a device.
Replace the stubbed out CXL Get/Clear Event mailbox commands with
commands that operate on
From: Ira Weiny
Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
commands. Enable those commands to control interrupts for each of the
event log types.
Skip the standard input mailbox length on the Set command due to DCD
being optional. Perform the checks separately.
Following patches will need access to the mailbox return code
type so move it to the header.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 28
include/hw/cxl/cxl_device.h | 28
2 files changed,
From: Ira Weiny
The device status register block was defined. However, there were no
individual registers nor any data wired up.
Define the event status register [CXL 3.0; 8.2.8.3.1] as part of the
device status register block. Wire up the register and initialize the
event status for each
Whilst I'm an optimist, I suspect this is now 8.1 material because we have
5 CXL patch sets outstanding before it. Current bottleneck being QAPI review
for the RAS error series.
v4 changes: Thanks to Ira and to some feedback I received off list.
- More endian fixes for a future big endian
Current implementation is very simple so many of the corner
cases do not exist (e.g. fragmenting larger poison list entries)
Signed-off-by: Jonathan Cameron
---
v4:
- Fix off by one on check of edge of vmr (cut and paste from similar
but long fixed in the volatile memory series)
- Drop
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the kernel code.
Reviewed-by: Ira Weiny
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads, but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
Kernel patches to use this interface here:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32 bit host native value.
The use of b, w, l, q as the size specifier is limiting. So "24" was
used for
From: Ira Weiny
There are new users of this functionality coming shortly so factor
it out from the GET_TIMESTAMP mailbox command handling.
Signed-off-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v8:
Picked up tag from Fan Ni
---
hw/cxl/cxl-device-utils.c | 15
Given the increasing usage of this mailbox return code type, now
is a good time to switch to QEMU style naming.
Reviewed-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v8: Picked up tag from Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 64
Note there are several series ahead of this one and in particular
the RAS error injection series needs some QAPI review.
The QAPI stuff in this patch is similar but in essence very similar
to what we have in that series.
Whilst I'm an always an optimist, this may well end up as 8.1 material
now.
On Wed, 1 Mar 2023 22:38:26 -0800
Ira Weiny wrote:
> Jonathan Cameron wrote:
> > Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
> > provides information related to DRAM devices.
> >
> > Example injection command in QMP:
> >
> > { "execute": "cxl-inject-dram-event",
> >
> > +memset(out, 0, out_pl_len);
> > +QLIST_FOREACH(ent, poison_list, node) {
> > +uint64_t start, stop;
> > +
> > +/* Check for no overlap */
> > +if (ent->start >= query_start + query_length ||
> > +ent->start + ent->length <= query_start) {
> > +
On Thu, 2 Mar 2023 17:05:22 -0800
Ira Weiny wrote:
> Jonathan Cameron wrote:
> > Current implementation is very simple so many of the corner
> > cases do not exist (e.g. fragmenting larger poison list entries)
> >
> > Signed-off-by: Jonathan Cameron
> > ---
> > v2:
> > - Endian fix
> > ---
> >
On Mon, 27 Feb 2023 17:34:14 +
Jonathan Cameron wrote:
> From: Ira Weiny
>
> To facilitate testing provide a QMP command to inject a general media
> event. The event can be added to the log specified.
>
> Signed-off-by: Ira Weiny
> Link:
>
with lots
> of stuff among them QAPI.
Thanks for the tip. Resent with additional CCs (hopefully to right
people!) and a note that we are looking for qapi review.
With the benefit of hindsight I'd have ordered the series differently
if I'd guessed we'd bottleneck here.
Jonathan
>
&g
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Reviewed-by: Dave Jiang
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big endian. However it is good to avoid making
things
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
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