)
xtensa queue 2013-10-15
Max Filippov (1):
target-xtensa: add in_asm logging
target-xtensa/translate.c | 8
1 file changed, 8 insertions(+)
--
1.8.1.4
On Fri, Sep 27, 2013 at 11:36 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 27/09/2013 20:29, Max Filippov ha scritto:
Hi,
I'm getting said assertion failure debugging linux userspace
application through the qemu gdbstub. The backtrace looks like this:
qemu-system-xtensa: include/qemu
This fixes missing debug feature opcodes of dc233c core variant.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/core-dc233c.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-xtensa/core-dc233c.c b/target-xtensa/core-dc233c.c
index 11acbf3
On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke sebast...@macke.de wrote:
Hi Alex,
I am using a cross-compiling toolchain. It's the easiest way as I have to
compile the image for QEMU anyhow.
http://opencores.org/or1k/OpenRISC_GNU_tool_chain
Then it's just an make make test in the
On Tue, Oct 22, 2013 at 8:15 PM, Sebastian Macke sebast...@macke.de wrote:
On 22/10/2013 9:01 AM, Max Filippov wrote:
On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke sebast...@macke.de
wrote:
Hi Alex,
I am using a cross-compiling toolchain. It's the easiest way as I have to
compile
/archive/html/qemu-devel/2013-09/msg04582.html
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
exec.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 2e31ffc..9150430 100644
--- a/exec.c
+++ b/exec.c
@@ -409,8 +409,10
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
This patch separates the load and store instruction to a
separate function.
The repetition of the source code can be reduced and further
optimizations can be implemented.
In this case it checks for a zero offset and
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
At the moment there are two TLBs. The OpenRISC TLB followed
by the QEMU's own TLB.
At the end of the TLB miss handler a tlb_flush of QEMUs TLB
is executed which is exactly what we want to avoid.
As long as there is no
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
Hi,
This is the second part of the patches to make the openrisc target faster
and more reliable.
Hi Sebastian,
this series doesn't apply cleanly to the current qemu git head,
what tree is it based on?
--
Thanks.
--
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
srf is a boolean variable.
Therefore the instruction should check for != 0 and not for != SR_F
Signed-off-by: Sebastian Macke sebast...@macke.de
---
target-openrisc/translate.c | 2 +-
1 file changed, 1
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de wrote:
Instead of testing the overflow exception dynamically every time
The flag will be reckognized by the tcg as changed code and
will recompile the code with the correct checks.
Signed-off-by: Sebastian Macke
On Wed, Oct 30, 2013 at 1:53 AM, Sebastian Macke sebast...@macke.de wrote:
On 29/10/2013 2:01 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de
wrote:
At the moment there are two TLBs. The OpenRISC TLB followed
by the QEMU's own TLB.
At the end
On Wed, Oct 30, 2013 at 1:36 AM, Sebastian Macke sebast...@macke.de wrote:
On 29/10/2013 1:05 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke sebast...@macke.de
wrote:
Additional this patch solves a severe bug for the softmmu emulation.
The pc has to be saved
On Tue, Sep 10, 2013 at 11:25 AM, Xie Xianshan xi...@cn.fujitsu.com wrote:
hi everyone,
I`m getting the nobody cared disabling IRQ error, when i raised external
interrupts IRQ3 to the Openpic in QEMU.
(Actually, any external interrupts irq i raised can reproduce this error,
but internal
On Wed, Sep 11, 2013 at 12:12 PM, Xie Xianshan xi...@cn.fujitsu.com wrote:
I want to add a new device fpga for e500, and trigger an interrupt IRQ3
while the register BB_INTR_REG which belongs to device fpga is wrote by
the device driver of fpga.
For e500, IRQ3 is an external interrupt irq.
On Thu, Sep 12, 2013 at 11:49 AM, Xie Xianshan xi...@cn.fujitsu.com wrote:
Hi Max,
Thanks for your patience and help.
I`ve tried to do what you said, but the problem doesn`t go away.
And actually i cannot add a new register to the fpga device, because the
fpga device i`m emulating
On Thu, Sep 12, 2013 at 2:51 PM, Xie Xianshan xi...@cn.fujitsu.com wrote:
Dear Max,
Does it mean an IRQ to be edge-triggered?
No, it is a level-sensitive and active-high interrupt.
This is why i tried to use qemu_irq_raise() to trigger IRQ.
Ok, back to your original question:
I`m
got any
measurable performance change. From op,out_asm output most
TBs got longer by 1-4 instructions and all temp indices got
doubled.
---8---
From 73300be7dd6b3d31cbfa45225714d5e43c52f077 Mon Sep 17 00:00:00 2001
From: Max Filippov jcmvb...@gmail.com
Date: Sun, 22 Sep 2013 18:54:53 +0400
Subject
of
cpu_get_phys_page debug in the breakpoint_invalidate:
--- 8 ---
commit cb3f9f90688be062b8a1f12b116f3d48c7ded232
Author: Max Filippov jcmvb...@gmail.com
Date: Fri Sep 27 22:19:16 2013 +0400
exec: fix breakpoint_invalidate when pc may not be translated
This fixes qemu abort with the following
/commits/qom-cpu-11.v3
xtensa parts: Acked-by: Max Filippov jcmvb...@gmail.com
--
Thanks.
-- Max
On Mon, Jul 29, 2013 at 3:01 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On Thu, Jul 11, 2013 at 08:01:19AM +0400, Max Filippov wrote:
On Thu, Jul 11, 2013 at 6:35 AM, Max Filippov jcmvb...@gmail.com wrote:
Hi Peter,
I suddenly found qemu built with debug enabled aborting
(2013-07-29 18:35:45 +0400)
xtensa queue 2013-07-29
Andreas Färber (1):
tests/tcg/xtensa: Fix out-of-tree build
Max Filippov (5):
target-xtensa: add extui
On Mon, Jul 29, 2013 at 7:16 PM, Max Filippov jcmvb...@gmail.com wrote:
Hello Blue/Antony,
Please pull my current target-xtensa patch queue. There's a number of
assorted fixes, new testcase and performance optimization patch.
Changes since 2013-07-21: trivial rebase.
Ping?
The following
On Fri, Aug 9, 2013 at 9:14 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 9 August 2013 18:11, Yaodong Yang yaodong.ya...@gmail.com wrote:
2. how to invoke QEMU with gdb,
because my previous attempt failed. gdb sudo
/usr/local/kvm/bin/qemu-system/x86_64 -s -enable-kvm -hda
This won't
On Fri, Aug 9, 2013 at 11:19 PM, Richard Henderson r...@twiddle.net wrote:
The script massages the output produced for architectures that are
not supported internally by qemu though an external objdump program
for disassembly.
I'd add something like the following to get disassembled hunks with
On Sat, Aug 10, 2013 at 8:42 PM, Richard Henderson r...@twiddle.net wrote:
On 08/10/2013 05:45 AM, Peter Maydell wrote:
Well, it depends. If we're going to dump all the in-tree
disassemblers and always use an external objdump, that's fine.
It's tempting, given that the only internal
On Mon, Oct 28, 2013 at 4:43 AM, Max Filippov jcmvb...@gmail.com wrote:
This fixes qemu abort with the following message:
include/qemu/int128.h:22: int128_get64: Assertion `!a.hi' failed.
which happens due to attempt to invalidate breakpoint by virtual address
for which
.
Max Filippov (2):
exec: fix breakpoint_invalidate when pc may not be translated
target-xtensa: add missing DEBUG section to dc233c config
exec.c | 6 --
target-xtensa/core-dc233c.c | 1 +
2 files
On Mon, Nov 11, 2013 at 8:50 PM, Eric Blake ebl...@redhat.com wrote:
Quick - identify the bug in this code (from ui/curses.c):
static void curses_winch_handler(int signum)
{
struct winsize {
unsigned short ws_row;
unsigned short ws_col;
unsigned short ws_xpixel;
On Wed, Nov 13, 2013 at 11:26 AM, Fardin fardina...@yahoo.com wrote:
Hi everyone,
My question might look very stupid but the answer would really help me.
I am working on Android emulator which is using QEMU. I need to print out
the value of env-cp15.c13_fcse everytime the void
android
emulator only for ARM.
You can add
#include elf.h
into cputlb.c and then decide based on ELF_MACHINE symbol, like
#if ELF_MACHINE == EM_ARM
On Wed, Nov 13, 2013 at 1:59 AM, Max Filippov jcmvb...@gmail.com wrote:
On Wed, Nov 13, 2013 at 11:26 AM, Fardin fardina...@yahoo.com wrote:
Hi
Hi Varad,
On Mon, Nov 18, 2013 at 5:49 PM, Varad Gautam varadgau...@gmail.com wrote:
Hi! I'm new here, and am working on my first bug. I have posted a patch
for Bug#603872 [1]. It's incomplete right now, but please have a look and
tell me if I'm headed in the right direction. (I don't know if
On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber afaer...@suse.de wrote:
Max,
Am 29.06.2013 22:01, schrieb Andreas Färber:
Register a CPU type per core registered. Save the XtensaConfig in
XtensaCPUClass instead of CPUXtensaState.
Prepares for storing per-class GDB register count.
On Sat, Jul 6, 2013 at 10:01 PM, Max Filippov jcmvb...@gmail.com wrote:
On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber afaer...@suse.de wrote:
Max,
Am 29.06.2013 22:01, schrieb Andreas Färber:
Register a CPU type per core registered. Save the XtensaConfig in
XtensaCPUClass instead
From: Andreas Färber afaer...@suse.de
Signed-off-by: Andreas Färber afaer...@suse.de
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure | 5 +++--
tests/tcg/xtensa/Makefile | 20 +++-
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git
On Sat, Jul 6, 2013 at 10:45 PM, Andreas Färber afaer...@suse.de wrote:
Hi Max,
Am 06.07.2013 20:01, schrieb Max Filippov:
On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber afaer...@suse.de wrote:
Am 29.06.2013 22:01, schrieb Andreas Färber:
Register a CPU type per core registered. Save
On Sat, Jul 6, 2013 at 11:12 PM, Andreas Färber afaer...@suse.de wrote:
Am 06.07.2013 20:39, schrieb Max Filippov:
On Sat, Jul 6, 2013 at 10:01 PM, Max Filippov jcmvb...@gmail.com wrote:
On Sat, Jul 6, 2013 at 4:55 PM, Andreas Färber afaer...@suse.de wrote:
Am 29.06.2013 22:01, schrieb Andreas
it works, so for xtensa part
Acked-by: Max Filippov jcmvb...@gmail.com
My question about having configuration pointer cached in the env
still remains though.
--
Thanks.
-- Max
Hi Andreas,
commit c52a6b67c1d7c6fc9fb2e3ba988d7b978e1487d3
Author: Andreas Färber afaer...@suse.de
Date: Fri May 17 17:49:10 2013 +0200
gdbstub: Simplify find_cpu()
Use qemu_get_cpu() and CPUState::env_ptr.
Reviewed-by: Richard Henderson r...@twiddle.net
Signed-off-by:
On Tue, Jul 9, 2013 at 12:42 PM, Andreas Färber afaer...@suse.de wrote:
Am 09.07.2013 09:39, schrieb Michael Tokarev:
Ping?
Have you tested -semihosting? The xtensa test image on the Wiki uses
-nographic, but semihosting content always seems to go to stdout without
going through a chardev
On Wed, Jul 10, 2013 at 1:47 AM, Andreas Färber afaer...@suse.de wrote:
Hi Max,
Am 09.07.2013 01:37, schrieb Max Filippov:
commit c52a6b67c1d7c6fc9fb2e3ba988d7b978e1487d3
Author: Andreas Färber afaer...@suse.de
Date: Fri May 17 17:49:10 2013 +0200
gdbstub: Simplify find_cpu
Hi Peter,
I suddenly found qemu built with debug enabled aborting with an assertion on
one of xtensa tests:
qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel
./test_sr.tst
QEMU 1.4.50 monitor - type 'help' for more information
(qemu) QEMU 1.4.50 monitor - type 'help' for
On Thu, Jul 11, 2013 at 6:35 AM, Max Filippov jcmvb...@gmail.com wrote:
Hi Peter,
I suddenly found qemu built with debug enabled aborting with an assertion on
one of xtensa tests:
qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel
./test_sr.tst
QEMU 1.4.50 monitor
Explicitly mark cases where we are deliberately falling through to the
following code.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/op_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 4c41de0..834fe90
) qemu-system-xtensa: tcg/tcg.c:1673: temp_save: Assertion
`s-temps[temp].val_type == 2 || s-temps[temp].fixed_reg' failed.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff
)
Andreas Färber (1):
tests/tcg/xtensa: Fix out-of-tree build
Max Filippov (5):
target-xtensa: add extui unit test
target-xtensa: add fallthrough markers
target-xtensa: avoid double-stopping at breakpoints
target-xtensa: don't generate dead code to access invalid
.
Also don't check env-exception_taken directly from the
gen_intermediate_code_internal, instead allocate and use TB flag
XTENSA_TBFLAG_EXCEPTION.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h | 4
target-xtensa/op_helper.c | 3 +++
target-xtensa/translate.c | 3
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
tests/tcg/xtensa/Makefile | 1 +
tests/tcg/xtensa/test_extui.S | 26 ++
2 files changed, 27 insertions(+)
create mode 100644 tests/tcg/xtensa/test_extui.S
diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa
This lowers time spent in helper_window_check as reported by perf top
from ~8% to ~0.15% accelerating register-intensive tests by ~20%.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 33 +
1 file changed, 25 insertions(+), 8
From: Andreas Färber afaer...@suse.de
Signed-off-by: Andreas Färber afaer...@suse.de
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure | 5 +++--
tests/tcg/xtensa/Makefile | 20 +++-
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git
After the commit 182735e cpu: Make first_cpu and next_cpu CPUState
we can no longer blindly use cpu-next_cpu-env_ptr to get CPUArchState
of the next CPU, as the next_cpu is NULL in the last CPU.
This fixes segfault caused by gdb command 'info threads'.
Signed-off-by: Max Filippov jcmvb
On Mon, Jul 22, 2013 at 2:54 PM, Andreas Färber afaer...@suse.de wrote:
Am 22.07.2013 07:24, schrieb Max Filippov:
After the commit 182735e cpu: Make first_cpu and next_cpu CPUState
we can no longer blindly use cpu-next_cpu-env_ptr to get CPUArchState
of the next CPU, as the next_cpu is NULL
Command dumps valid ITLB and DTLB entries.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
hmp-commands.hx|2 +-
monitor.c |4 +-
target-xtensa/cpu.h|1 +
target-xtensa/helper.c | 67
4 files changed, 71
TLB_TEMPLATE macro specifies TLB geometry in the core configuration.
Make TLB_TEMPLATE available for region protection core variants,
defining 1 way ITLB and DTLB with 8 entries each.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/overlay_tool.h | 18 --
1
In qemu-1.0:hw/loader.c, load_elf() calls load_elf64() or load_elf32().
But where is the function definition/body of load_elf32()?
It is in hw/elf_ops.h:190
static int glue(load_elf, SZ)(const char *name, int fd,
uint64_t (*translate_fn)(void *, uint64_t),
I'm adding a new target to qemu, now, I'm writing mmu simulation, but
it make me confused.
When TLB miss occurred, I can't seperate DTLB miss from ITLB miss.
I implemented it like this from target-xtensa:
if (rw 2)
HANDLE DTLB MISS
else
HANDLE ITLB MISS
I guess that you mean qemu
When stopping the guest with -S before it booted, gdb will interrupt it
while it is still in 16-bit real mode. Later on, when Linux runs, the
guest is in 64-bit protected mode. gdb is not prepared for such a
switch. All you can do:
Try
set arch i386:x86-64
in the GDB prompt.
--
Thanks.
--
Hi.
During qemu-system-x86_64 startup there are odd calls to apic_set_irq
with vector_num=0.
I observe the following call sequence: PIT reset
Breakpoint 1, apic_set_irq (s=0x89e3e18, vector_num=0, trigger_mode=0)
at /home/jcmvbkbc/ws/xtensa/qemu-xtensa/hw/apic.c:424
424 {
(gdb) bt
#0
-by: Max Filippov jcmvb...@gmail.com
---
configure |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/configure b/configure
index 6c77fbb..580cd4d 100755
--- a/configure
+++ b/configure
@@ -2200,7 +2200,7 @@ cat $TMPC EOF
int main(void)
{
-int efd = eventfd(0, 0
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively;
- ITLB/DTLB way 6 attr field is set to 3 on reset.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/helper.c |2 +-
target-xtensa/overlay_tool.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff
I oprofiled QEMU with some workloads, i.e. SPECjbb on Ubuntu Linux, i
see QEMU spent about 60 - 70% of the time in the code cache ( code
cache size is 256MB ). but I want to know which TB takes the most
amount of time.
I doubt that it's possible to profile TB code by external tools without
Do you have a static libgthread-2.0? (ie /usr/lib/libgthread-2.0.a or
equivalent).
Nope, this is what I have:
/usr/lib64/libgthread.so
/usr/lib64/libgthread-2.0.so
/usr/lib64/libgthread-1.2.so.0
/usr/lib64/libgthread-1.2.so.0.0.10
*but*, just downloaded the source rpm and looked at
So, somebody at Fedora doesn't like static (.a) files very much, it
seems. I could easily correct this, enable static building and have these
installed, I think.
There's glib2-static in Fedora:
$ rpm -ql glib2-static
/usr/lib64/libgio-2.0.a
/usr/lib64/libglib-2.0.a
It fails some other way ):
$ make V=1
gcc -m64 -D_FORTIFY_SOURCE=2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64
-D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef
-Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing
-fstack-protector-all -Wendif-labels
Even though I executed ./configure --target-list=arm-linux-user
armeb-linux-user --disable-kvm --disable-strip --disable-xen --disable-spice
--disable-werror --disable-sdl --disable-vnc --disable-bluez
--disable-check-utests --disable-smartcard --disable-usb-redir --static the
Did configure reported 'usb net redir' as 'no'?
Could you try configure and build in a clean directory?
[mr-4@test1 qemu-1.0-rc3]$ ./configure --target-list=arm-linux-user
armeb-linux-user --disable-kvm --disable-strip --disable-xen --disable-spice
--disable-werror --disable-sdl
--*dir) option pattern precede --{en,dis}able-usb-redir) patterns in the
option analysis switch, making the latter options have no effect.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configure b
/usr/lib/gcc/x86_64-redhat-linux/4.6.1/../../../../lib64/libglib-2.0.a(gmem.o):(.note.stapsdt+0x24):
undefined reference to `glib_mem__alloc_semaphore'
/usr/lib/gcc/x86_64-redhat-linux/4.6.1/../../../../lib64/libglib-2.0.a(gmem.o):(.note.stapsdt+0x7c):
undefined reference to
Is there any solution to this?
Traditional: it may be fixed in the mainline already, F15 has version
2.28.8, whereas mainline tip is 2.31.2.
However nothing in the git log suggests that.
FWIW Ubuntu Oneiric has glib2 2.30.0 and doesn't seem to have this problem.
Just compiled, built and
In fact, what cases is this supposed to be matching? All
the documented --thingydir options are handled explicitly
earlier in the case statement.
Paolo, you added this case in commit 6bde81cb0, but the
commit message doesn't give any rationale; what's it for?
There were some --*dir that
that overrides
directories for their distribution.
Replace --*dir with exact option names.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure | 24 ++--
1 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index f033438..3154307 100755
that overrides
directories for their distribution.
Replace --*dir with exact option names.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
v2 - v3 changes: add --htmldir
---
configure | 26 --
1 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
that overrides
directories for their distribution.
Replace --*dir with exact option names.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
v2 - v3 changes: add --htmldir
v3 - v4 changes: collapse cases, include rationale into the configure
---
configure | 10 --
1 files changed, 8 insertions
Also all the registers which are pushed to the stack,
r3, r4, r5, r6, r7, lr are cleared to zero
That is odd. I wonder if the processor is resetting for some reason.
Another other possibility is stack pointer pointing to a region w/o
underlying physical memory.
--
Thanks.
-- Max
Breakpoint 7, cpu_arm_exec (env=0x102033200) at ~/qemu-0.15.0/cpu-exec.c:557
557 next_tb = tcg_qemu_tb_exec(env, tc_ptr);
(gdb) p/x env-regs
$13 = {0x4002c00c, 0x20, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0,
0x0, 0x30, 0x10007fa8, 0x560d, 0x560c}
(gdb) s
558
This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt
from HPCN Lab KICS UET Lahore.
Shouldn't 'Signed-off-by' lines for mentioned persons be present in
the relevant patches if this is a team work?
--
Thanks.
-- Max
Misgenerated code might not be an issue now since we have tested our
framework
in LLVM-only mode. I think the problem still is about the link/unlink stuff.
The first problem I have while lowering the threshold is the broken one
generate
a few traces (2, actually) that a work one doesn't.
There's no attachment in this mail. I can try to help you resolving it
if you provide more information.
Sorry about that, see the attachment please. What kind of information you
want
to know?
If your code is available online I can try it myself, the question is
where is it hosted then.
If
I found this in HACKING:
Please note that NULL check for the g_malloc result is redundant and
that g_malloc() call with zero size is not allowed.
So we have:
1. You should not request 0 bytes from g_malloc().
I think this was related to qemu_malloc() and Anthony's sed run
).
67882fd177389527510eb36b3f7712011a835545 is the first bad commit
commit 67882fd177389527510eb36b3f7712011a835545
Author: Max Filippov jcmvb...@gmail.com
Date: Tue Sep 6 03:55:28 2011 +0400
target-xtensa: implement narrow instructions
Instructions with op0 = 8 are 2 bytes long, others are 3 bytes long
is the first bad commit
commit 67882fd177389527510eb36b3f7712011a835545
Author: Max Filippov jcmvb...@gmail.com
Date: Tue Sep 6 03:55:28 2011 +0400
target-xtensa: implement narrow instructions
Instructions with op0 = 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max
This series adds support for Tensilica Xtensa target.
Overall RFC - PATCH changes:
- implement TB chaining;
- replace stray printfs with qemu_logs;
- consolidate big endianness support with corresponding little endianness
counterparts;
- removed gdbstub patch from this series, will post a
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
configure| 12 +++-
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
3 files changed, 13 insertions(+), 1 deletions(-)
create mode 100644 default-configs/xtensa
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- remove cpu_reset from cpu_xtensa_init;
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c|4 ++
elf.h |2
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target|1 +
hw
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 110 -
1 files
Instructions with op0 = 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- put gen_exit_tb
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- optimize SEXT from bits 7 and 15;
---
target-xtensa
is in separate patch.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |8 ++
target-xtensa/helper.c|1 +
target-xtensa/helpers.h |8 ++
target-xtensa/op_helper.c | 185 +
target-xtensa/translate.c | 146
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index d27a47c..41ac4f2
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 95
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- make NSA/NSAU helpers;
- optimize shifts for 5 bit wide SAR;
---
target-xtensa/cpu.h |4 +
target-xtensa
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- extract common
looping code verifies actual LEND value.
Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- add
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 60 -
1 files changed, 59 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 7deda1b..8933e5a 100644
--- a/target
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- use -semihosting to implement SIMCALL;
- fix
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
RFC - PATCH changes:
- add XTENSA_TBFLAG_LITBASE, use it in L32R;
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1
or uregnames are considered valid.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 47 +++-
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target
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