The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_clint.c | 9
After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target
The sifive_u machine already marks its ROM readonly. This fixes
the remaining boards.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 9 +
hw/riscv/spike.c | 18 ++
hw/riscv
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target
more complex
trap handling code).
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
c: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
Signed-off-by: Michael Clark
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
---
target/riscv/cpu.c | 123 ++---
1 file changed, 69 insertions(+), 54 deletions(-)
diff --git a/target/ris
f the
device-tree size is exceeded. e.g. large bootargs.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20
hw/riscv/spike.c| 16 +++-
hw/riscv/virt.c | 13 +
3
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
Signed-off-by: Michael Clark
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7..c3a029a 100644
--- a/target/riscv
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 2
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1dcbdbe..cd337ab 100644
--- a/target/riscv/cpu.h
These fields are marked WARL in the specification so illegal
writes are silently dropped.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 26 +-
1 file changed, 13 insertions(+), 13
Koppelmann
Signed-off-by: Palmer Dabbelt
Signed-off-by: Michael Clark
---
target/riscv/helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index b2e3f45..0d802a8 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -489,6
On Thu, Mar 22, 2018 at 2:56 AM, Philippe Mathieu-Daudé
wrote:
> Hi Michael,
>
> On 03/20/2018 07:25 PM, Michael Clark wrote:
> > The following changes since commit f1a63fcfcd92c88be8942b5ae71aef
> 9749a4f135:
> >
> > Update version for v2.12.0-rc0 rele
On Mon, Mar 19, 2018 at 2:39 PM, Michael Clark wrote:
>
>
> On Mon, Mar 19, 2018 at 12:42 PM, Richard W.M. Jones
> wrote:
>
>> On Mon, Mar 19, 2018 at 11:35:51AM -0700, Michael Clark wrote:
>> > The RISC-V post-merge spec conformance and cleanup series has had
On Thu, Mar 22, 2018 at 3:17 PM, DJ Delorie wrote:
> "Richard W.M. Jones" writes:
> > DJ, am I remembering correctly that you tried the test case on the
> > HiFive evaluation board and it didn't demonstrate the bug?
>
> I tested it on the vc707 board, without seeing the bug.
>
> I can test other
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1dcbdbe..cd337ab 100644
--- a/target/riscv/cpu.h
disseasembler:
https://github.com/michaeljclark/riscv-meta/
commit/4a6b2f3898430768acfe201405224d2ea31e1477
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Peter Maydell
Signed-off-by: Michael Clark
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
Signed-off-by: Michael Clark
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7..c3a029a 100644
--- a/target/riscv
more complex
trap handling code).
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target
eries
Michael Clark (26):
RISC-V: Make virt create_fdt interface consistent
RISC-V: Replace hardcoded constants with enum values
RISC-V: Make virt board description match spike
RISC-V: Use ROM base address and size from memmap
RISC-V: Remove identity_translate from load_elf
RISC-V: Mar
are mutually exclusive, as the E extension
will be added to the RISC-V port in the future.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 1 +
2 files changed, 2 insertions(+), 1
Koppelmann
Signed-off-by: Palmer Dabbelt
Signed-off-by: Michael Clark
---
target/riscv/helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index b2e3f45..0d802a8 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -489,6
The sifive_u machine already marks its ROM readonly. This fixes
the remaining boards.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 9 +
hw/riscv/spike.c | 18 ++
hw/riscv
Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target
checks from ternary operator to if statements
- Improves page walker comments
- No measurable performance impact on dd test
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 2 --
target/riscv/helper.c | 59
f the
device-tree size is exceeded. e.g. large bootargs.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20
hw/riscv/spike.c| 16 +++-
hw/riscv/virt.c | 13 +
3
On Fri, Mar 23, 2018 at 3:20 AM, Peter Maydell
wrote:
> On 20 March 2018 at 22:25, Michael Clark wrote:
> > -BEGIN PGP SIGNED MESSAGE-
> > Hash: SHA1
> >
> > The following changes since commit f1a63fcfcd92c88be8942b5ae71aef
> 9749a4f135:
> >
> >
comment, checkpatch warnings fixed, and a conditional to only enable the
behaviour if mttcg is enabled (as uniprocessor mstatus.FS apepars to be
okay).
Thanks,
Michael
On Wed, Mar 21, 2018 at 1:46 PM, Michael Clark wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Th
On Sat, Mar 24, 2018 at 11:54 AM, Michael Clark wrote:
> Hi Peter,
>
> I did actually have the full `riscv-qemu-2.12-fixes-v5` tag in the second
> PR. See below.
>
> It was the v4 pull request prior to this where I made the mistake of not
> including the series version in
On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote:
> This change is a workaround for a bug where mstatus.FS
> is not correctly reporting dirty when MTTCG and SMP are
> enabled which results in the floating point register file
> not being saved during context switches. This a cr
On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote:
> - Inline PTE_TABLE check for better readability
> - Improve readibility of User page U mode and SUM test
> - Disallow non U mode from fetching from User pages
> - Add reserved PTE flag check: W or W|X
> - Add misaligned PP
On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote:
> The sifive_u machine already marks its ROM readonly. This fixes
> the remaining boards.
>
> Cc: Sagar Karandikar
> Cc: Bastian Koppelmann
> Signed-off-by: Michael Clark
> Signed-off-by: Palmer Dabbelt
> --
On Sat, Mar 24, 2018 at 12:45 PM, Michael Clark wrote:
>
>
> On Sat, Mar 24, 2018 at 11:13 AM, Michael Clark wrote:
>
>> The sifive_u machine already marks its ROM readonly. This fixes
>> the remaining boards.
>>
>> Cc: Sagar Karandikar
>> Cc: Bas
These fields are marked WARL in the specification so illegal
writes are silently dropped.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 26 +-
1 file changed, 13 insertions(+), 13
Cc: Peter Maydell
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 1fdde90..d345688 100644
--- a/target/riscv/op_helper.c
+++ b/ta
This patch adds an experimental RISC-V TCG backend.
We have been dogfooding the RISC-V QEMU front-end with Fedora
to develop a RISC-V TCG backend. The RISC-V TCG backend can
be built inside of the QEMU RISC-V 'virt' machine using
the Fedora stage 4 disk image:
- https://fedoraproject.org/wiki/Arc
This is essentially dead-code elimination. Support for more
local interrupts will be added in a future revision, as they
will be defined in a future version of the Privileged ISA
specification.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer
On Sat, Mar 24, 2018 at 2:25 PM, Peter Maydell
wrote:
> On 24 March 2018 at 18:13, Michael Clark wrote:
> > Remove a potential buffer overflow (not seen in practice).
> > Perhaps cpu_physical_memory_write already has bound checks.
>
> cpu_physical_memory_write() writes
On Sat, Mar 24, 2018 at 2:23 PM, Peter Maydell
wrote:
> On 24 March 2018 at 18:13, Michael Clark wrote:
> > The sifive_u machine already marks its ROM readonly. This fixes
> > the remaining boards.
> >
> > Cc: Sagar Karandikar
> > Cc: Bastian Koppelmann
On Sun, Mar 25, 2018 at 8:03 AM, Peter Maydell
wrote:
> On 24 March 2018 at 18:13, Michael Clark wrote:
> > This is a series of bug fixes and code cleanups that we would
> > like to get in before the QEMU 2.12 release. We are respinning
> > v6 of this series to include two
On Mon, Mar 26, 2018 at 12:16 PM, Laurent Vivier wrote:
> No code change, only move code from main.c to
> riscv/cpu_loop.c.
>
> Signed-off-by: Laurent Vivier
>
Reviewed-by: Michael Clark
> ---
> linux-user/main.c | 101 +-
>
On Sun, Mar 25, 2018 at 5:47 AM, Peter Maydell
wrote:
> On 25 March 2018 at 00:23, Michael Clark wrote:
> >
> >
> > On Sat, Mar 24, 2018 at 2:23 PM, Peter Maydell >
> > wrote:
> >>
> >> On 24 March 2018 at 18:13, Michael Clark wrote:
> >&
On Mon, Mar 26, 2018 at 11:07 AM, Michael Clark wrote:
>
>
> On Sun, Mar 25, 2018 at 8:03 AM, Peter Maydell
> wrote:
>
>> On 24 March 2018 at 18:13, Michael Clark wrote:
>> > This is a series of bug fixes and code cleanups that we would
>> > like to get
On Mon, Mar 26, 2018 at 4:14 PM, Michael Clark wrote:
>
>
> On Mon, Mar 26, 2018 at 11:07 AM, Michael Clark wrote:
>
>>
>>
>> On Sun, Mar 25, 2018 at 8:03 AM, Peter Maydell
>> wrote:
>>
>>> On 24 March 2018 at 18:13, Michael Clark wrote:
&g
2 # 0x6db2c
0x000ddb30: 3acf80e7 jalrra,t6,940
0x000ddb34: d10ff06f j -2800 # 0xdd044
0x000ddb38: 000de537 lui a0,909312
0x000ddb3c: a435051b addiw a0,a0,-1469
0x000ddb40: d08ff06f j
On Tue, Mar 27, 2018 at 3:52 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 03/25/2018 05:24 AM, Michael Clark wrote:
> > Running with `-d in_asm,op,op_opt,out_asm` is very helpful
> > for debugging. Note: due to a limitation in QEMU, the backend
&g
On Tue, Mar 27, 2018 at 2:42 AM, Peter Maydell
wrote:
> On 26 March 2018 at 19:07, Michael Clark wrote:
> > On Sun, Mar 25, 2018 at 8:03 AM, Peter Maydell >
> > wrote:
> >> Hi. It looks to me like a fair number of these patches
> >> are already revie
On Tue, Mar 27, 2018 at 11:39 AM, Michael Clark wrote:
>
> I will divide the series up into 3 branches, and move through them in
> order of priority, with correctness ahead of tidyness:
>
> 1). riscv-qemu-2.12-critical-fixes
> 2). riscv-qemu-2.13-bug-fixes
> 3). riscv-qe
This series includes changes that are considered release critical,
such as floating point register file corruption under SMP Linux.
Michael Clark (1):
RISC-V: Workaround for critical mstatus.FS MTTCG bug
target/riscv/op_helper.c | 19 +--
1 file changed, 17 insertions(+), 2
Tested-by: Richard W.M. Jones
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e34715d..7281b98 100644
--- a/target/riscv/op_helper.c
+++ b/ta
This series includes changes that are considered important.
i.e. correct user-visible bugs that are exercised by common
operations such as -cpu list or -d in_asm
Michael Clark (2):
RISC-V: Convert cpu definition to future model
RISC-V: Fix incorrect disassembly for addiw
disas/riscv.c
disseasembler:
https://github.com/michaeljclark/riscv-meta/
commit/4a6b2f3898430768acfe201405224d2ea31e1477
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Peter Maydell
Signed-off-by: Michael Clark
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
ndikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Signed-off-by: Michael Clark
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
---
target/riscv/cpu.c | 123 ++---
1 file changed, 69 insertions(+), 54 deletions(-)
diff --git a/ta
On Tue, Mar 27, 2018 at 3:17 PM, Philippe Mathieu-Daudé
wrote:
> Cc'ing Alex and Richard.
>
> On 03/27/2018 04:54 PM, Michael Clark wrote:
> > This change is a workaround for a bug where mstatus.FS
> > is not correctly reporting dirty when MTTCG and SMP are
> &
This series includes changes that are considered release critical,
such as floating point register file corruption under SMP Linux.
v2
- reverted to Richard W.M. Jone's original, more conservative fix
- reworded comment to be more concise and more general
Michael Clark (1):
RISC-V: Worka
Koppelmann
Cc: Peter Maydell
Cc: Alex Bennée
Cc: Richard Henderson
Cc: Philippe Mathieu-Daudé
Tested-by: Richard W.M. Jones
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/riscv
Koppelmann
Cc: Peter Maydell
Cc: Alex Bennée
Cc: Richard Henderson
Cc: Philippe Mathieu-Daudé
Tested-by: Richard W.M. Jones
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/riscv
Hi Richard,
Thanks! I'll test this tomorrow morning and we can choose whether to
include your proper fix or the workaround.
I think we have time assuming we send out PRs tomorrow.
Given our important fixes have review including either this fix by tomorrow
or the workaround, and Philippe has revi
On Tue, Mar 27, 2018 at 5:35 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 03/28/2018 01:43 AM, Michael Clark wrote:
> > > +if ((ct & TCG_CT_CONST_N12) && val >= -2047 && val <= 2047) {
> >
> > +2048?
>
Ye
On Tue, Mar 27, 2018 at 7:22 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> Writes to the FP register file mark the register file as dirty.
>
> Signed-off-by: Richard Henderson
> ---
> target/riscv/op_helper.c | 25 +
> target/riscv/translate.c | 40 ++
On Wed, Mar 28, 2018 at 10:36 AM, Michael Clark wrote:
>
>
> On Tue, Mar 27, 2018 at 7:22 PM, Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
>> Writes to the FP register file mark the register file as dirty.
>>
>> Signed-off-by: Ric
On Tue, Mar 27, 2018 at 7:22 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> Since it was my patch that broke FP state tracking in the
> first place, I feel obligated to fix it again.
>
> Mark mstatus[fs] as dirty whenever we write to the file.
> This can be optimized by only doing
disseasembler:
https://github.com/michaeljclark/riscv-meta/
commit/4a6b2f3898430768acfe201405224d2ea31e1477
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Peter Maydell
Signed-off-by: Michael Clark
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
disas
anges that are considered important.
i.e. correct user-visible bugs that are exercised by common
operations such as -cpu list (CPU model changes) or -d in_asm
(fix for disassembly of addiw)
--------
Michael Clark (2):
RISC-V: Convert cpu
ndikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Signed-off-by: Michael Clark
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
---
target/riscv/cpu.c | 123 ++---
1 file changed, 69 insertions(+), 54 deletions(-)
diff --git a/ta
enderson
>
Reviewed-by: Michael Clark
---
> target/riscv/cpu.h | 6 +++---
> target/riscv/translate.c | 10 +-
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 41e06ac0f9..d201dd3e90 100644
On Tue, Mar 27, 2018 at 7:22 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> Writes to the FP register file mark the register file as dirty.
>
> Signed-off-by: Richard Henderson
>
Reviewed-by: Michael Clark
Tested-by: Michael Clark
> ---
> targe
Koppelmann
Cc: Peter Maydell
Cc: Alex Bennée
Cc: Richard Henderson
Cc: Philippe Mathieu-Daudé
Tested-by: Richard W.M. Jones
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
target/riscv/op_helper.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions
QEMU 2.13.
--------
Michael Clark (1):
RISC-V: Workaround for critical mstatus.FS bug
target/riscv/op_helper.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
On Fri, Mar 30, 2018 at 12:11 AM, Alex Bennée
wrote:
>
> Michael Clark writes:
>
> > On Tue, Mar 27, 2018 at 3:17 PM, Philippe Mathieu-Daudé >
> > wrote:
> >
> >> Cc'ing Alex and Richard.
> >>
> >> On 03/27/2018 04:54 PM, Michael C
Thanks,
Michael.
On Thu, Mar 29, 2018 at 10:26 AM, Michael Clark wrote:
> The following changes since commit 47d3b60858d90ac8a0cc3a72af7f95
> c96781125a:
>
> Merge remote-tracking branch
> 'remotes/riscv/tags/riscv-qemu-2.12-important-fixes'
> into stagi
On Sun, Apr 1, 2018 at 11:49 AM, Richard W.M. Jones
wrote:
> On Fri, Mar 30, 2018 at 10:08:23AM -0700, Michael Clark wrote:
> > Hi Peter,
> >
> > I had tested Richard's proper fix but we didn't have a PR or the required
> > Reviewed-by and Signed-off-by so I
Currently the device-tree create_device_tree function
returns the size of the allocated device tree buffer
however there is no way to get the actual amount of
buffer space used by the device-tree.
14ec3cbd7c1e31dca4d23f028100c8f43e156573 increases
the FDT_MAX_SIZE to 1 MiB. This creates an issue
f
On Sat, Apr 28, 2018 at 4:17 AM, Alistair Francis
wrote:
> On Thu, Apr 26, 2018 at 10:34 PM Michael Clark wrote:
>
>
>
> > On Fri, Apr 27, 2018 at 5:22 PM, Michael Clark wrote:
>
>
>
> >> On Fri, Apr 27, 2018 at 4:48 AM, Alistair Francis >
> wrot
On Fri, May 4, 2018 at 8:56 AM, Alistair Francis
wrote:
> On Wed, Apr 25, 2018 at 5:02 PM Michael Clark wrote:
>
> > * Add user-mode CSR defininitions.
> > * Reorder CSR definitions to match the specification.
> > * Change H mode interrupt comment to 'reserve
On Sat, May 5, 2018 at 8:12 AM, Alistair Francis
wrote:
> Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
>
> We leave the SoC, RAM, device tree and reset/fdt loading as part of the
> machine. All the other device creation has been moved to the SoC.
>
There is a tiny prob
On Sat, May 5, 2018 at 11:54 AM, Alistair Francis
wrote:
> On Fri, May 4, 2018 at 4:44 PM Alistair Francis
> wrote:
>
> > On Thu, May 3, 2018 at 6:45 PM Michael Clark wrote:
>
>
>
> > > On Sat, Apr 28, 2018 at 4:17 AM, Alistair Francis <
> alistai...@gma
the uin32_t terminator. See here:
int fdt_resize(void *fdt, void *buf, int bufsize)
{
...
headsize = fdt_off_dt_struct(fdt);
tailsize = fdt_size_dt_strings(fdt);
if ((headsize + tailsize) > bufsize)
return -FDT_ERR_NOSPACE;
...
return 0;
}
>
> > thanks
> > -- PMM
> >
>
FYI - I've dropped this patch to qemu/include/sysemu/device_tree.h
and qemu/device_tree.c in favor of calling fdt_pack() and fdt_totalsize().
On Sun, May 6, 2018 at 9:59 AM, Michael Clark wrote:
>
>
> On Sat, May 5, 2018 at 11:48 PM, David Gibson > wrote:
>
>> On
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw
eral code cleanups
* Replacing hard-coded constants with enums
* Dead-code elimination
This is an incremental pull that contains 20 reviewed changes out
of 38 changes currently queued in the qemu-2.13-for-upstream branch.
--------
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 2
Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Fr
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed
Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 02cbcea2b731..95889f23b94d 100644
--- a/target
plete unnecessary.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/riscv_hart.c | 6 --
hw/riscv/sifive_e.c | 25 -
hw/
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by
ses generate
illegal instructions when the privileged ISA <= v1.9.1
- Makes mscounteren and mucounteren CSR accesses generate
illegal instructions when the privileged ISA >= v1.10
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Mich
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv
elt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/op_helper.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 101dac1ee8dc..f45ac7306c38 100644
--- a/target/ri
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Cc: Peter Maydell
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
Reviewed-by: Philippe
that that the device tree fits in the assigned
ROM space using the new qemu_fdt_totalsize(void *fdt)
interface, adding a bounds check and error message. This
can detect truncation.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
are mutually exclusive, as the E extension
will be added to the RISC-V port in the future.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 1
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b
) fields is to drop writes to unsupported bits.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv
more complex
trap handling code).
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/op_helper.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target
401 - 500 of 699 matches
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