[PATCH v32 07/13] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 1123 1 file changed, 1123 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v32 06/13] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik --- target/avr/translate.c | 542 + 1 file changed, 542

[PATCH v32 08/13] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 174 + 1 file changed, 174 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 19540634df..21ba6004ee

[PATCH v32 09/13] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 21ba6004ee

[PATCH v32 13/13] target/avr: Add tests

serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/Makefile.include | 2 ++ tests/acceptance/machine_avr6.py | 36 tests/boot-serial-test.c | 10

[PATCH v32 05/13] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW Signed-off-by: Michael Rolnik --- target/avr/translate.c | 811 + 1 file changed, 811 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 53c9892a60..3eaa3e5099 100644 --- a/target/avr

Re: [PATCH v39 03/22] target/avr: Add instruction decoding

Hi Aleksandar. please explain. On Sat, Dec 21, 2019 at 1:18 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Wednesday, December 18, 2019, Michael Rolnik wrote: > >> This includes: >> - encoding of all 16 bit instructions >> -

Re: [PATCH v39 15/22] target/avr: Add example board configuration

Hi Igor. I don't find where machine->ram is defined. Regards, Michael Rolnik On Fri, Dec 20, 2019 at 11:51 AM Igor Mammedov wrote: > On Wed, 18 Dec 2019 23:03:22 +0200 > Michael Rolnik wrote: > > > A simple board setup that configures an AVR CPU to run a give

[PATCH v39 13/22] target/avr: Add limited support for 16 bit timer peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v39 09/22] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 68 ++ 1 file changed, 68 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index e303a1f4cc..46cbcc9305 100644

[PATCH v39 08/22] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 235 + 1 file changed, 235 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v39 06/22] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 530

[PATCH v39 10/22] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v39 07/22] target/avr: Add instruction translation - Data Transfer Instructions

This includes: - MOV, MOVW - LDI, LDS LDX LDY LDZ - LDDY, LDDZ - STS, STX STY STZ - STDY, STDZ - LPM, LPMX - ELPM, ELPMX - SPM, SPMX - IN, OUT - PUSH, POP - XCH - LAS, LAC LAT Signed-off-by: Michael Rolnik --- target/avr/translate.c | 986

[PATCH v39 12/22] target/avr: Add limited support for USART peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v39 21/22] target/avr: Add Avocado test

The test is based on https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. it also demostrates that timer and IRQ are working Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested

[PATCH v39 16/22] target/avr: Add section about AVR into QEMU documentation

Signed-off-by: Michael Rolnik --- qemu-doc.texi | 51 +++ 1 file changed, 51 insertions(+) diff --git a/qemu-doc.texi b/qemu-doc.texi index eea91a2d1e..c169ab9357 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1742,6 +1742,7 @@ differences

[PATCH v39 20/22] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/boot-serial-test.c | 10 ++ tests/Makefile.include | 2 ++ 2 files changed, 12 insertions(+) diff --git a/tests

[PATCH v39 19/22] target/avr: Update build system

Make AVR support buildable Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- configure | 7 +++ default-configs/avr-softmmu.mak | 5 + target/avr/Makefile.objs| 34 + 3

[PATCH v39 15/22] target/avr: Add example board configuration

, AddressSpace *as, bool load_rom, symbol_fn_t sym_cb); /** load_elf_ram: diff --git a/hw/avr/sample.c b/hw/avr/sample.c new file mode 100644 index 00..4fdbc17f1c --- /dev/null +++ b/hw/avr/sample.c @@ -0,0 +1,293 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik

[PATCH v39 02/22] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/helper.h | 29 target/avr/helper.c | 347 2 files changed, 376

[PATCH v39 22/22] target/avr: Update MAINTAINERS file

Include AVR maintaners in MAINTAINERS file Signed-off-by: Michael Rolnik --- MAINTAINERS | 21 + 1 file changed, 21 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 740401bcbb..9ed886106a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,27 @@ S

[PATCH v39 01/22] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov Tested

[PATCH v39 18/22] target/avr: Add machine none test

Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- tests/machine-none-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c index 5953d31755..3e5c74e73e 100644 --- a/tests/machine-none

[PATCH v39 14/22] target/avr: Add dummy mask device

Signed-off-by: Michael Rolnik --- include/hw/misc/avr_mask.h | 47 hw/misc/avr_mask.c | 112 + hw/misc/Kconfig| 3 + hw/misc/Makefile.objs | 2 + 4 files changed, 164 insertions(+) create mode 100644 include/hw

[PATCH v39 17/22] target/avr: Register AVR support with the rest of QEMU

Add AVR related definitions into QEMU Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic include/disas/dis-asm.h --- qapi/machine.json | 3 ++- include/disas/dis-asm.h| 19 +++ include/sysemu/arch_init.h | 1

[PATCH v39 11/22] target/avr: Add instruction disassembly function

, r24 0x04c2: RET ... ``` Signed-off-by: Michael Rolnik Suggested-by: Richard Henderson Suggested-by: Philippe Mathieu-Daudé Suggested-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/cpu.h | 1 + target/avr/cpu.c

[PATCH v39 04/22] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 143 + 1 file changed, 143 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b

[PATCH v39 05/22] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 714

[PATCH v39 00/22] QEMU AVR 8 bit cores

lines from target/avr/translate.c file 9. set number of interrupt lines to 64 10. determine cpu type by reading ELF flags 11. update license of all new files to be LGPL 12. udpate QEMU documentation changes since v38 1. rebase 2. add examples of AVR emulator invokation into the QEMU doc 3. reorder in

[PATCH v39 03/22] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/insn.decode | 183 + 1 file changed, 183 insertions(+) create mode 100644 target

[PATCH v38 02/22] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/helper.h | 29 target/avr/helper.c | 347 2 files changed, 376

[PATCH v38 00/22] QEMU AVR 8 bit cores

remove empty lines from target/avr/translate.c file 9. set number of interrupt lines to 64 10. determine cpu type by reading ELF flags 11. update license of all new files to be LGPL 12. udpate QEMU documentation Michael Rolnik (22): target/avr: Add outward facing interfaces and core CPU logic targe

[PATCH v38 05/22] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 734

[PATCH v38 03/22] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/insn.decode | 194 + 1 file changed, 194 insertions(+) create mode 100644 target

[PATCH v38 11/22] target/avr: Add instruction disassembly function

, r24 0x04c2: RET ... ``` Signed-off-by: Michael Rolnik Suggested-by: Richard Henderson Suggested-by: Philippe Mathieu-Daudé Suggested-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/cpu.h | 1 + target/avr/cpu.c

[PATCH v38 01/22] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov Tested

[PATCH v38 06/22] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 537

[PATCH v38 10/22] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v38 09/22] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 174 + 1 file changed, 174 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index d8d8f11933..68025112ff

[PATCH v38 04/22] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 143 + 1 file changed, 143 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b

[PATCH v38 12/22] target/avr: Add limited support for USART peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v38 14/22] target/avr: Add dummy mask device

Signed-off-by: Michael Rolnik --- include/hw/misc/avr_mask.h | 47 hw/misc/avr_mask.c | 112 + hw/misc/Kconfig| 3 + hw/misc/Makefile.objs | 2 + 4 files changed, 164 insertions(+) create mode 100644 include/hw

Re: [PATCH v38 00/22] QEMU AVR 8 bit cores

I hope I did not miss anything. On Sun, Dec 8, 2019 at 8:39 PM Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. > However I was able to execute simple code with fu

[PATCH v38 08/22] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 243 + 1 file changed, 243 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v38 18/22] target/avr: Add machine none test

Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- tests/machine-none-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c index 5953d31755..3e5c74e73e 100644 --- a/tests/machine-none

[PATCH v38 15/22] target/avr: Add example board configuration

/avr/sample.c b/hw/avr/sample.c new file mode 100644 index 00..6574733b57 --- /dev/null +++ b/hw/avr/sample.c @@ -0,0 +1,293 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms

[PATCH v38 17/22] target/avr: Register AVR support with the rest of QEMU

Add AVR related definitions into QEMU Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- qapi/machine.json | 3 ++- include/disas/dis-asm.h| 6 ++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ 4 files

[PATCH v38 07/22] target/avr: Add instruction translation - Data Transfer Instructions

This includes: - MOV, MOVW - LDI, LDS LDX LDY LDZ - LDDY, LDDZ - STS, STX STY STZ - STDY, STDZ - LPM, LPMX - ELPM, ELPMX - SPM, SPMX - IN, OUT - PUSH, POP - XCH - LAS, LAC LAT Signed-off-by: Michael Rolnik --- target/avr/translate.c | 861

[PATCH v38 20/22] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/boot-serial-test.c | 10 ++ tests/Makefile.include | 2 ++ 2 files changed, 12 insertions(+) diff --git a/tests

[PATCH v38 22/22] target/avr: Update MAINTAINERS file

Include AVR maintaners in MAINTAINERS file Signed-off-by: Michael Rolnik --- MAINTAINERS | 21 + 1 file changed, 21 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5e5e3e52d6..9ab7ed0865 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,27 @@ S

[PATCH v38 21/22] target/avr: Add Avocado test

The test is based on https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. it also demostrates that timer and IRQ are working Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested

[PATCH v38 16/22] target/avr: Add section about AVR into QEMU documentation

Signed-off-by: Michael Rolnik --- qemu-doc.texi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/qemu-doc.texi b/qemu-doc.texi index 3ddf5c0a68..cea1008800 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1757,6 +1757,7 @@ differences are mentioned in the following sections

[PATCH v38 13/22] target/avr: Add limited support for 16 bit timer peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v38 19/22] target/avr: Update build system

Make AVR support buildable Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- configure | 7 +++ default-configs/avr-softmmu.mak | 5 + target/avr/Makefile.objs| 34 + 3

Re: [PATCH v38 11/22] target/avr: Add instruction disassembly function

You are right. See at the bottom of the file. There is a comment about it Sent from my cell phone, please ignore typos On Tue, Dec 10, 2019, 6:21 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Monday, December 9, 2019, Michael Rolnik wrote: > >>

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

, 2020 at 5:31 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Fri, Feb 21, 2020 at 12:04 PM Michael Rolnik wrote: > > > > Hi all. > > > > How is it going? > > > > Regards, > > Michael. > > > > Michael, > >

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

Hi all. are there any action items for me? Regards, Michael Rolnik On Thu, Feb 27, 2020 at 10:38 AM Michael Rolnik wrote: > Hi all. > > I don't see how the fact that some MCUs have an instruction and some don't > within same AVR family. > Think about gnu binutils (not GCC) t

Re: [PATCH rc2 00/25] target/avr merger

Just one patch attached. Thanks. On Fri, Jan 24, 2020 at 2:49 PM Philippe Mathieu-Daudé wrote: > On 1/24/20 12:41 PM, Michael Rolnik wrote: > > Tested-by: Michael Rolnik mailto:mrol...@gmail.com>> > > Thanks a lot! > > > The only thing I want to change i

Re: [PATCH rc2 14/25] target/avr: Add section about AVR into QEMU documentation

Hi Thomas. I will fix it. thanks. Michael Rolnik On Fri, Jan 24, 2020 at 9:14 AM Thomas Huth wrote: > On 24/01/2020 01.51, Philippe Mathieu-Daudé wrote: > > From: Michael Rolnik > > > > Signed-off-by: Michael Rolnik > > Message-Id: <20200118191416.19934-16-mro

Re: [PATCH rc2 00/25] target/avr merger

Tested-by: Michael Rolnik The only thing I want to change is instead of -kernel put -bios in qemu-doc.texi file. Should I send a new series? On Fri, Jan 24, 2020 at 2:51 AM Philippe Mathieu-Daudé wrote: > This is the AVR port from Michael release (merge) candidate 2. > > Si

Re: [PATCH rc3 02/30] target/avr: Introduce AVR CPU class object

Hi all. As for now I have no plans to add support for AVR 32 bit CPU. If there are requests I might consider it. When I started to implement AVR 8 bit CPU I added that `#ifndef CONFIG_USER_ONLY` as other CPUs did, so I guess they could be removed. Regards, Michael Rolnik On Mon, Jan 27, 2020

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

Thanks for you help guys. On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > Co-developed-

Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic

Hi Joaquin. `AVR_FEATURE_1_BYTE_PC` is used in `gen_push_ret` function (target/avr/translate.c) Regards, Michael Rolnik On Sun, Jan 26, 2020 at 2:15 PM Joaquin de Andres wrote: > Hi! In this mail I only checked the general code and one of the listed > features for the different types

Re: [PATCH rc1 00/24] target/avr merger

merge it now. > > Thomas > > -- Best Regards, Michael Rolnik

Re: [PATCH rc3 02/30] target/avr: Introduce AVR CPU class object

Sounds good. Sent from my cell phone, please ignore typos On Wed, Jan 29, 2020, 5:12 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Wed, Jan 29, 2020 at 1:20 PM Sarah Harris wrote: > > > > Hi, > > > > I think I've found a minor bug: the stack pointer should be initialised >

Re: [PATCH rc4 00/29] target/avr merger

flags" was redone to reflect the original intent that was lost in > >>transalation between multiple autors > >> - Patch "hw/avr: Add helper to load raw/ELF firmware binaries" was > >>corrected only in one line to rectify type of "e_flags"

Re: [PATCH rc5 01/32] target/avr: Add basic parameters of the new platform

Tested-by: Michael Rolnik On Fri, Feb 7, 2020 at 3:58 AM Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > [AM: Split a

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

Sounds good to me. On Tue, Jan 28, 2020 at 3:49 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Tuesday, January 28, 2020, Michael Rolnik wrote: > >> Hi all. >> >> I am totally lost in the email. >> Are there any action i

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

Hi all. I am totally lost in the email. Are there any action items for me / someone else ? Regards, Michael Rolnik On Mon, Jan 27, 2020 at 10:54 AM Michael Rolnik wrote: > Thanks for you help guys. > > On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic < > aleksandar.mar

Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic

/config/avr/avr-devices.c Have a look here https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-mcus.def. you can see that not all xmega support RMW instructions. so whenever QEMU has atxmega128d4 implemented, atxmega128d4 model it will have to remove RMW feature. Regards, Michael Rolnik

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

Hi all. How is it going? Regards, Michael. On Mon, Feb 10, 2020 at 9:39 AM Michael Rolnik wrote: > Hi all. > > When I decided to implement AVR 8 bit CPU support for QEMU I found this > document > <http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruct

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

c/config/avr/avr-devices.c <https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c> file and when a specific MCU is created it will set / reset CPU features relevant to it. I hope this helps. Best Regards, Michael Rolnik On Sat, Feb 8, 2020 at 9:35 AM A

[PATCH v41 04/21] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 751

[PATCH v41 03/21] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 172 + 1 file changed, 172 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b

[PATCH v41 08/21] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 68 ++ target/avr/insn.decode | 9 ++ 2 files changed, 77 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v41 17/21] target/avr: Add machine none test

Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- tests/qtest/machine-none-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c index 5953d31755..3e5c74e73e 100644

[PATCH v41 05/21] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 533

[PATCH v41 12/21] hw/avr: Add limited support for 16 bit timer peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v41 09/21] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v41 11/21] hw/avr: Add limited support for USART peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v41 20/21] target/avr: Add Avocado test

The test is based on https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. it also demostrates that timer and IRQ are working Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested

[PATCH v41 15/21] target/avr: Add section about AVR into QEMU documentation

Signed-off-by: Michael Rolnik --- qemu-doc.texi | 51 +++ 1 file changed, 51 insertions(+) diff --git a/qemu-doc.texi b/qemu-doc.texi index 39f950471f..515aacfae9 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1741,6 +1741,7 @@ differences

[PATCH v41 00/21] QEMU AVR 8 bit cores

der instructions to match AVR documentation 4. fix elf loader function bug introduced by prev version changes since v39 1. rename target/avr to hw/avr for hw related commits 2. spread instruction decoding commit 3. add frequency parameter to AVR timer changes since v40 1. rebase 2. remove not n

[PATCH v41 14/21] hw/avr: Add example board configuration

, AddressSpace *as, bool load_rom, symbol_fn_t sym_cb); /** load_elf_ram: diff --git a/hw/avr/sample.c b/hw/avr/sample.c new file mode 100644 index 00..95094a8d6c --- /dev/null +++ b/hw/avr/sample.c @@ -0,0 +1,295 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik

[PATCH v41 18/21] target/avr: Update build system

Make AVR support buildable Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- configure | 7 +++ default-configs/avr-softmmu.mak | 5 + target/avr/Makefile.objs| 34 + 3

[PATCH v41 19/21] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth tests/Makefile.include --- tests/qtest/boot-serial-test.c | 10 ++ tests/qtest/Makefile.include | 2 ++ 2 files changed, 12

[PATCH v41 16/21] target/avr: Register AVR support with the rest of QEMU

Add AVR related definitions into QEMU Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic include/disas/dis-asm.h --- qapi/machine.json | 3 ++- include/disas/dis-asm.h| 19 +++ include/sysemu/arch_init.h | 1

[PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov Tested

[PATCH v41 21/21] target/avr: Update MAINTAINERS file

Include AVR maintaners in MAINTAINERS file Signed-off-by: Michael Rolnik --- MAINTAINERS | 21 + 1 file changed, 21 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 55d3642e6c..c70d77b1ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,15 @@ S

[PATCH v41 10/21] target/avr: Add instruction disassembly function

, r24 0x04c2: RET ... ``` Signed-off-by: Michael Rolnik Suggested-by: Richard Henderson Suggested-by: Philippe Mathieu-Daudé Suggested-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/cpu.h | 1 + target/avr/cpu.c

[PATCH v41 13/21] hw/avr: Add dummy mask device

This is a simple device of just one register, whenver this register is written it calls qemu_set_irq function for each of 8 bits/IRQs.. It is used to implement AVR Power Reduction Signed-off-by: Michael Rolnik --- include/hw/misc/avr_mask.h | 47 hw/misc/avr_mask.c

[PATCH v41 07/21] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 241 + target/avr/insn.decode | 14 +++ 2 files changed, 255

[PATCH v41 06/21] target/avr: Add instruction translation - Data Transfer Instructions

This includes: - MOV, MOVW - LDI, LDS LDX LDY LDZ - LDDY, LDDZ - STS, STX STY STZ - STDY, STDZ - LPM, LPMX - ELPM, ELPMX - SPM, SPMX - IN, OUT - PUSH, POP - XCH - LAS, LAC LAT Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé

[PATCH v41 02/21] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/helper.h | 29 target/avr/helper.c | 347 2 files changed, 376

Re: [PATCH v3 0/8] hw/avr: Introduce the Arduino boards

Sure, no problem. On Mon, Jan 20, 2020 at 12:50 AM Philippe Mathieu-Daudé wrote: > Hi Michael, > > On 12/30/19 7:17 PM, Michael Rolnik wrote: > > Hi Philippe. > > > > Thank you for joining the effort. > > Could you test this series? > > Are you OK if we

Re: [PATCH v4 00/18] hw/avr: Introduce few Arduino boards

/{avr_usart.h => atmel_usart.h} (93%) > rename include/hw/misc/{avr_mask.h => atmel_power.h} (89%) > rename include/hw/timer/{avr_timer16.h => atmel_timer16.h} (92%) > create mode 100644 hw/avr/arduino.c > create mode 100644 hw/avr/atmel_atmega.c > delete mode 100644 hw/avr/sample.c > rename hw/char/{avr_usart.c => atmel_usart.c} (99%) > rename hw/misc/{avr_mask.c => atmel_power.c} (97%) > rename hw/timer/{avr_timer16.c => atmel_timer16.c} (98%) > > -- > 2.21.1 > > -- Best Regards, Michael Rolnik

Re: [PATCH v40 00/21] QEMU AVR 8 bit cores

Hi all, any news? Regards, Michael Rolnik On Sun, Dec 29, 2019 at 1:52 PM Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. > However I was able to execute

[PATCH v40 19/21] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/boot-serial-test.c | 10 ++ tests/Makefile.include | 2 ++ 2 files changed, 12 insertions(+) diff --git a/tests

[PATCH v40 14/21] hw/avr: Add example board configuration

, AddressSpace *as, bool load_rom, symbol_fn_t sym_cb); /** load_elf_ram: diff --git a/hw/avr/sample.c b/hw/avr/sample.c new file mode 100644 index 00..95094a8d6c --- /dev/null +++ b/hw/avr/sample.c @@ -0,0 +1,295 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik

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