Memory barriers are supposed to do something on BookE systems, these
were probably just missed during MTTCG enablement, maybe no targets
support SMP. Either way, add proper BookE implementations.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/misc-impl.c.inc | 4 ++--
1 file changed, 2
instruction exceptions
when using new POWER10 sync variants that add new fields, after this
the instructions are accepted and are implemented as supersets of
the new behaviour, as intended.
Signed-off-by: Nicholas Piggin
---
target/ppc/insn32.decode | 7 ++
target/ppc/translate.c
On Thu May 2, 2024 at 6:32 PM AEST, Cédric Le Goater wrote:
> Hello Nick,
>
>
> >>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> >>> index 5869aac89a..eb9dbc62dd 100644
> >>> --- a/hw/ppc/pnv.c
> >>> +++ b/hw/ppc/pnv.c
> >>> @@ -1642,6 +1642,8 @@ static void pnv_chip_power9_realize(DeviceState
> >>>
On Wed Apr 24, 2024 at 7:30 PM AEST, Cédric Le Goater wrote:
> This helper routine uses the machine definition, sockets, cores and
> threads, to loop on all CPUs of the machine. Replace CPU_FOREACH()
> with it.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Nicholas Piggin
On Thu May 2, 2024 at 6:47 PM AEST, Cédric Le Goater wrote:
> On 5/1/24 14:39, Nicholas Piggin wrote:
> > On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le Goater wrote:
> >> Hello Nick,
> >>
> >> On 4/17/24 13:02, Nicholas Piggin wrote:
> >>> T
On Sat Apr 27, 2024 at 12:32 AM AEST, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> > with Power11 being the newest supported Power processor in QEMU.
>
> This is too early. We should merge Power11 su
ned-off-by: Nicholas Piggin
---
include/hw/ppc/spapr.h | 1 +
hw/ppc/spapr.c | 1 +
hw/ppc/spapr_caps.c| 1 +
3 files changed, 3 insertions(+)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 4aaf23d28f..f6de3e9972 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/p
On Fri May 3, 2024 at 3:44 PM AEST, Cédric Le Goater wrote:
> On 5/3/24 06:51, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 6:47 PM AEST, Cédric Le Goater wrote:
> >> On 5/1/24 14:39, Nicholas Piggin wrote:
> >>> On Wed Apr 17, 2024 at 9:25 PM AEST, Cédric Le G
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The helper_rac function is defined but not used, remove it.
>
> Fixes: 005b69fdcc (target/ppc: Remove PowerPC 601 CPUs)
> Signed-off-by: BALATON Zoltan
Reviwed-by: Nicholas Piggin
> ---
> target/ppc/helper.h |
er and avoid computing it when not needed.
>
> Signed-off-by: BALATON Zoltan
Reviwed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
>
er and avoid computing it when not needed.
>
> Signed-off-by: BALATON Zoltan
Reviwed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 25 -
> 1 file changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/pp
te
ctx->prot even if the lookup failed, but it already does that in
some cases so... no issue.
If this was more widely used API we'd rather change it to never
update *prot on failure, but okay we can do this.
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
>
.
Hopefully the compiler should be able to work it out, but IMO it
reads better with your change.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The default case will catch this and abort the same way and there is
> still a warning about it in ppc_tlb_invalidate_all() so drop these
> from mmu_common.c to simplify this code.
Reviewed-by: Nicholas Piggin
>
>
y */
if (env->nb_BATs != 0) {
int ret = get_bat_6xx_tlb(env, ctx, eaddr, access_type);
if (ret >= 0) {
return ret;
}
}
Otherwise,
Reviewed-by: Nicholas Piggin
> +/* Perform segment based translation when no BATs matched */
> pr =
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Rename to ppc6xx_tlb_get_bat() to match other similar names in the
> same file.
>
> Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 6 +++---
> 1 file changed, 3 inser
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> BookE does not have real mode so split off and handle it first in
> get_physical_address_wtlb() before checking for real mode for other
> MMU models.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The real mode handling is identical in the remaining switch cases.
> Split off these common real mode cases into a separate conditional to
> leave only the else branches in the switch that are different.
>
Reviewed-by: Nic
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function just does two assignments and and unnecessary check that
> is always true so inline it in the only caller left and remove it.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> --
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 25 +
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
> diff --git a/target/ppc/mmu_com
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Fix several qemu_log_mask() calls that are misindented.
Acked-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 42 -
> 1 file chan
nt i, j, ways, ret = -1;
>
> for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
> -int ways = booke206_tlb_ways(env, i);
Don't need to bring the ways variable into a larger scope I think?
Otherwise,
Reviewed-by: Nicholas Piggin
> -
> +ways = booke206_tlb_ways(env, i);
static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr
> eaddr,
> *protp = ctx.prot;
> *psizep = TARGET_PAGE_BITS;
> return true;
> +} else if (!guest_visible) {
> +return false;
> }
Acked-by: Nicholas Piggin
>
> -if
cess so using MMU_DATA_LOAD here seems wrong so replace it with
> access_type here as well that yields the same result. This also makes
> these calls the same as the data access branch further down.
Looks right.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> --
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function is not used from any other files so make it static and
> fix the maybe used uninitialised warnings this has uncovered.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/internal.h | 5 +
> target/ppc/mmu_common.c |
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This type is only used within mmu_common.c. Move its definition from
> internal.h to there.
This can be squashed with the previous patch unexport the
remaining user.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BA
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
> pp_check() in mmu_common.c. Rename the latter to ppc_pte_prot() and
> merge with ppc_hash32_pp_prot() to remove duplicated code.
>
> Signed-off-by: BALATON Zoltan
> ---
>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
Nice.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 180 ++--
> 1 file ch
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function is no longer called for BookE MMU model so remove parts
> related to it. This has uncovered a few may be used uninitialised
> warnings that are also fixed.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c |
Will review this if we can get -4 case removed...
Don't know if I'm too keen on doing the fetch branch first
and asymmetric (if vs switch) checking of ret in the fetch
vs data cases. I think with -4 case removed things will
look much nicer.
Thanks,
Nick
On Thu May 2, 2024 at 9:43 AM AEST, BALATO
What do you think about adding mmu-book3e.c instead?
Thanks,
Nick
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 300
> 1 file changed, 150 insertions(+), 150 deletions(-)
>
> d
he_line_size);
> qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
>cpu->env.icache_line_size);
> -if (cpu->env.id_tlbs) {
> +if (cpu->env.tlb_type == TLB_6XX) {
Want to just add the standard comment here?
/* 6xx h
_74xx(CPUPPCState *env)
> return 0;
> }
>
> +static void init_tlbs_4xx(CPUPPCState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> +env->nb_tlb = 64;
> +env->nb_ways = 1;
> +env->tlb_type = TLB_EMB;
> +#endif
> +}
e200 isn't 4xx though is it? Call it i
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This series does some further clean up mostly around BookE MMU to
> untangle it from other MMU models. It also contains some other changes
> that I've come up with while working on this. The first 3 patches are
> from the last exception ha
On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > What do you think about adding mmu-book3e.c instead?
>
> I have considered that but found that some functions have to be in the
> same file and declared static for the
this ancient hardware and focus on newer CPUs and platforms.
>
> Signed-off-by: Cédric Le Goater
Acked-by: Nicholas Piggin
> ---
> v2: fixed header line
>
> docs/about/deprecated.rst | 8
> hw/ppc/ppc405_boards.c| 1 +
> 2 files changed, 9 insertions(+
On Wed May 8, 2024 at 2:02 AM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> >> This flag for split instruction/data TLBs is only set for 6xx soft TLB
> >> MMU model and not used o
r so no need to keep these separate functions and
> combining them simplifies the caller allowing further restructuring.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 26 --
> 1 file changed, 12 insertion
return -3;
> +}
Function is already inconsistent with assigning ret and falling
through to the return ret at the end vs returning immediately, so
okay since you're tidying it up.
Reviewed-by: Nicholas Piggin
> +/* Page address translation */
> +
>prot, ret);
> /* Update page flags */
> pte_update_flags(ctx, &env->tlb.tlb6[best].pte1, ret, access_type);
> }
> +#if defined(DUMP_PAGE_TABLES)
> +if (qemu_loglevel_mask(CPU_LOG_MMU)) {
> +CPUState *cs = env_cpu(env);
> +
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Return directly, which is simpler than dragging a return value through
> multpile if and else blocks.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc
On Wed May 8, 2024 at 9:40 AM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> >> This function is no longer called for BookE MMU model so remove parts
> >> related to it. This has
ile.
If you add a /* quiet used uninitialized warning */ or similar comment
on the memset then.
Reviewed-by: Nicholas Piggin
If you respin you could, put the prot fixes as their own patch but
pretty minor thing if you can't be bothered.
>
> Signed-off-by: BALATON Zoltan
> --
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> As BookE never returns -4 we can drop BookE from the direct store case
> in ppc_jumbo_xlate().
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 7 +--
> 1 file
ion from mmu-hash32.c would stop the compiler
> inlining it which results in slightly lower performance.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/internal.h | 35
>
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> This function is no longer called for BookE MMU model so remove parts
> related to it. This has uncovered a few may be used uninitialised
> warnings that are also fixed.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Move setting error_code that appears in every case out in front and
> hoist the common fall through case for BOOKE206 as well which allows
> removing the nested switches.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by:
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Merge the code fetch and data access cases in a common switch.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 50 +
> 1 file changed, 20 insertions(+), 30 deletions(-)
>
> dif
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
Okay for now but we should split into a new file soon.
Acked-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 226
> 1 file changed, 113 insert
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> The value is only used once so no need to introduce a local variable
> for it.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu-radix64.c | 5 ++---
> 1 file changed, 2 inser
sed once. We can drop the local variable and calculate
> it when needed, which makes these checks using it similar to other
> places with such checks.
Sure, why not.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu-hash32.c | 7 ++-
&
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Checking if a page protection bit is set for a given access type is a
> common operation. Add a macro to avoid repeating the same check at
> multiple places and also avoid a function call. As this relies on
> access type and page protecti
On Wed May 8, 2024 at 10:14 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back bu
On Thu May 9, 2024 at 1:17 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:14 AM AEST, BALATON Zoltan wrote:
> >> Most exceptions are raised with nip pointing to the faulting
> >> instruction but the sc instr
On Thu May 9, 2024 at 1:23 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> >> Checking if a page protection bit is set for a given access type is a
> >> common operation. Add a m
On Thu May 9, 2024 at 1:25 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> >> Move setting error_code that appears in every case out in front and
> >> hoist the common fall t
On Thu May 9, 2024 at 9:33 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote:
> >> On Tue, 7 May 2024, Nicholas Piggin wrote:
> >>> What do you think about adding mmu-book
On Thu May 9, 2024 at 9:35 AM AEST, BALATON Zoltan wrote:
> On Wed, 8 May 2024, Nicholas Piggin wrote:
> > On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> >> Checking if a page protection bit is set for a given access type is a
> >> common operation. Add a m
t; called in ppc_cpu_reset_hold() so likely we never get here but to make
> sure add a case to ppc_xlate() to the same effect.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 12 ++--
> 1 file changed, 2 insertions(+), 10 deleti
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Move the debug logging within ppc6xx_tlb_check() from after its only
> call to simplify the caller.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc
ret = -1;
> -raddr = (hwaddr)-1ULL;
> +*prot = 0;
This is still doing some sneaky used-uninit things which I would
rather not without a comment, but okay we can try untangle things
more after this series.
Reviewed-by: Nicholas Piggin
> pr = FIELD_EX64(env->msr, MSR, P
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> mmubooke_get_physical_address() only uses the raddr and prot fields
> from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> targe
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> mmubooke206_get_physical_address() only uses the raddr and prot fields
> from mmu_ctx_t. Pass these directly instead of using a ctx struct.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> --
in this file.
get_physical_address_wtlb and mmu_ctx_t is becoming basically 6xx
specific after this. Nice.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/internal.h | 17 +
> target/ppc/mmu_common.c | 17 ++---
> 2 files
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Merge the code fetch and data access cases in a common switch.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 52 -
>
On Thu May 9, 2024 at 9:36 AM AEST, BALATON Zoltan wrote:
> Add a new mmu-booke.c file for BookE and related MMU bits from
> mmu_common.c.
>
Nice work.
Acked-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/cpu.h| 4 -
> target/p
.
This requires a linkage between adu and lpc, which allows adu to
perform memory access in the lpc space.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 7 +++
include/hw/ppc/pnv_lpc.h | 5 +++
hw/ppc/pnv.c | 4 ++
hw/ppc/pnv_adu.c | 95
XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 25 +
include/hw/ppc
u-lpc link
- Renamed funcions to pnv_lpc_opb_ prefix rather than pnv_opb_lpc_
- Removed the unnecessary ADU class
Thanks,
Nick
Nicholas Piggin (2):
ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
ppc/pnv: Implement ADU access to LPC space
include/hw/ppc/pnv_adu.h | 32 ++
incl
psi#0:lpc_serirq_mux1
Whereas they previously turn up on lpchc.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_lpc.h | 12 -
hw/ppc/pnv.c | 38 +--
hw/ppc/pnv_lpc.c | 100 +++
3 files changed, 136 insertions(+), 14 deletions(-)
ing, and actually I did catch some
of these (the SPR size one) when running kvm-unit-tests with TCG. I
ported it to powernv too. I wonder if we should merge pnv-test into
kvm-unit-tests.
> > Signed-off-by: Nicholas Piggin
> > ---
> > target/ppc/excp_helper.c | 27 +++
On Fri Mar 24, 2023 at 11:39 PM AEST, Fabiano Rosas wrote:
> Nicholas Piggin writes:
>
> > This optional behavior was removed from the ISA in v3.0, see
> > Summary of Changes preface:
> >
> > Data Storage Interrupt Status Register for Alignment Interrupt:
implement finer details of SPR implementation (e.g.,
not all bits implemented as simple read/write storage).
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c| 18 +-
target/ppc/helper_regs.c | 2 +-
target/ppc/misc_helper.c | 4 ++--
target/ppc/power8-pmu.c | 2
The hypervisor emulation assistance interrupt modifies HEIR to
contain the value of the instruction which caused the exception.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c| 23 +++
target/ppc/excp_helper.c | 12
The CTRL register is able to write bit zero, and that is reflected in a
bit field in the register that reflects the state of all threads in the
core.
TCG does not implement SMT, so this just requires mirroring that bit into
the first bit of the thread state field.
Signed-off-by: Nicholas Piggin
by the Alignment interrupt.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Use insns_flags instead of excp_model [Fabiano review]
target/ppc/excp_helper.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
ISA v3.1 introduced prefix instructions. Among the changes, various
synchronous interrupts report whether they were caused by a prefix
instruction in (H)SRR1.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Use insns_flags instead of excp_model [Fabiano review]
target/ppc/excp_helper.c | 32
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Removed big endian ifdef [Fabiano review]
- Acaually use need_byswap helper
On Wed Mar 29, 2023 at 3:51 PM AEST, Michael Neuling wrote:
> Nick,
>
> > +case POWERPC_EXCP_HV_EMU:
> > +env->spr[SPR_HEIR] = insn;
> > +if (is_prefix_excp(env, insn)) {
> > +uint32_t insn2 = ppc_ldl_code(env, env->nip + 4);
> > +env->spr[SPR_HEIR] |= (u
I get a crash running a powerpc64 TCG machine on x86.
It can be triggered by booting a custom vmlinux patched to use powerpc
prefix instructions and pcrel addressing, I don't know if that's related
or coincidence. I can give Linux patches or a vmlinux file to reproduce
if needed, or I can test pat
On Fri Apr 7, 2023 at 7:02 PM AEST, Nicholas Piggin wrote:
> I get a crash running a powerpc64 TCG machine on x86.
>
> It can be triggered by booting a custom vmlinux patched to use powerpc
> prefix instructions and pcrel addressing, I don't know if that's related
> o
("target/ppc: Avoid tcg_const_* in translate.c")
> > Reported-by: Nicholas Piggin
> > Reviewed-by: Anton Johansson
> > Signed-off-by: Richard Henderson
>
> Looks good:
>
>https://gitlab.com/legoater/qemu/-/pipelines/831847446
>
> I have a PR ready for
On Fri May 5, 2023 at 8:54 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > @@ -1593,12 +1713,14 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
> > return H_PARAMETER;
> > }
> >
> > -s
On Fri May 5, 2023 at 9:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > Arguably this is just shuffling around register accesses, but one nice
> > thing it does is allow the exit to save away the L2 state then switch
> > the e
On Fri May 5, 2023 at 9:09 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > Create spapr_nested.c for the nested HV implementation (modulo small
> > pieces in MMU and exception handling).
> >
> This separation of nested code in it
On Sat Apr 29, 2023 at 12:30 AM AEST, Fabiano Rosas wrote:
> Vaibhav Jain writes:
>
> > Hi Fabiano,
> >
> > Thanks for looking into this patch and apologies for the delayed reponse.
> > Fabiano Rosas writes:
> >
> >> Narayana Murty N writes:
> >>
> >>> On PPC64 the HILE(Hypervisor Interrupt Litt
On Tue May 9, 2023 at 7:51 PM AEST, Harsh Prateek Bora wrote:
> On Thu, Mar 23, 2023 at 12:22:37PM +1000, Nicholas Piggin wrote:
> > The hypervisor emulation assistance interrupt modifies HEIR to
> > contain the value of the instruction which caused the exception.
> >
> &
implement finer details of SPR implementation (e.g.,
not all bits implemented as simple read/write storage).
Signed-off-by: Nicholas Piggin
---
Since v2: no change.
target/ppc/cpu_init.c| 18 +-
target/ppc/helper_regs.c | 2 +-
target/ppc/misc_helper.c | 4 ++--
target/ppc
The hypervisor emulation assistance interrupt modifies HEIR to
contain the value of the instruction which caused the exception.
Signed-off-by: Nicholas Piggin
---
Since v2:
- Fix ordering of prefix/suffix words in the register, as pointed
out by Mikey.
target/ppc/cpu.h | 1 +
target
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
Since v2: no change.
target/ppc/excp_helper.c | 20
Hopefully these are getting close to ready now. There is still the
question about doing better with adding test cases for all this, I
haven't exactly got a good answer yet but I do have kvm-unit-tests
for most at least.
Thanks,
Nick
Nicholas Piggin (9):
target/ppc: Fix width of some 3
The CTRL register is able to write bit zero, and that is reflected in a
bit field in the register that reflects the state of all threads in the
core.
TCG does not implement SMT, so this just requires mirroring that bit into
the first bit of the thread state field.
Signed-off-by: Nicholas Piggin
by the Alignment interrupt.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
Since v2: no change.
target/ppc/excp_helper.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index bc2be4a726
will allow more information to be passed to the exception
handler in the next patch.
Signed-off-by: Nicholas Piggin
---
Since v2: new patch to deal with bug in patch 6.
target/ppc/mmu-radix64.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/target
A store to MMCR0 with PMCjCE=1 fails to update hflags correctly and
results in hflags mismatch:
qemu: fatal: TCG hflags mismatch (current:0x2408003d rebuilt:0x240a003d)
This can be reproduced by running perf on a recent machine.
Signed-off-by: Nicholas Piggin
---
Since v2: new patch
from a load or store instruction (in that case the prefix
bit should be provided).
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
Since v2:
- Fix a bug where ifetch access causing HDSI due to process scoped table
access failing on partition scope translation would go into infinite
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.
Signed-off-by: Nicholas Piggin
---
Since v2: new patch.
target/ppc/excp_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target
On Mon May 15, 2023 at 7:32 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/15/23 14:02, Harsh Prateek Bora wrote:
> >>
> >> That would be wrong for the other HSRR fallthroughs above it.
> >>
> > Oh yeh, in that case, may be move it to top of the EXCP_HISI, it would
> > need duplicating one line of
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