From: yangxiaojuan
fw_cfg_data_read() func supports access widths from
1 to 8 bytes while the ops set the wrong read size.
Most arch use 8 bytes to send ram_size to bios.
Signed-off-by: yangxiaojuan
---
hw/nvram/fw_cfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This patch set default csr values Mainly used for
cpu_initfn and cpu_reset.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 40
target/loongarch/cpu.h | 6 ++
2 files changed, 46 insertions(+)
diff --git a/target
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 74 +
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ipi.c | 145 +++
hw/loongarch/ls3a5000_virt.c | 2 +
hw/loongarch/meson.build | 2 +-
include/hw/loongarch/gipi.h
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 571 +
hw/intc/meson.build| 1 +
hw/loongarch/Kconfig
the doc at
https://github.com/loongson/LoongArch-Documentation/releases/latest/
download/Loongson-7A1000-usermanual-2.00-EN.pdf
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/pci-host/Kconfig| 4 +
hw/pci-host/ls7a.c | 188 +
hw/pci
LoongArch is a new RISC ISA, support 32bit mode
or 64bit mode. Now we only add 64bit support.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
.../devices/loongarch64-softmmu/default.mak | 3
This patch Add loongarch interrupt and exception handle.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 293 +
target/loongarch/cpu.h | 6 +-
2 files changed, 298 insertions(+), 1 deletion(-)
diff --git a/target
This patch introduce vmstate_loongarch_cpu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 12 +++
target/loongarch/internals.h | 4 +
target/loongarch/machine.c | 155 +++
target/loongarch/meson.build | 6 ++
4
son.git/tree/Documentation/loongarch?h=loongarch-next
2.https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongarch_int.c | 62
hw/loongarch/ls3a5000_virt.c | 2 ++
hw/loongarch/meson.build
This patch add a stabletimer support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 10 +
target/loongarch/csr_helper.c | 26 +
target/loongarch/meson.build | 1 +
target/loongarch
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 19 +
target/loongarch/helper.h| 8 +
target/loongarch/insn_trans/trans_core.c | 54
more than 4 cpus.
Patch 30-31 Add some functions for debug.
Xiaojuan Yang (31):
target/loongarch: Upate the README for the softmmu.
target/loongarch: Add CSR registers definition
target/loongarch: Set default csr values.
target/loongarch: Add basic vmstate description of CPU.
target
This patch define All the CSR registers and its field.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 493 +
1 file changed, 493 insertions(+)
create mode 100644 target/loongarch/cpu-csr.h
diff --git a/target
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ls3a5000_virt.c | 49
include/hw/pci-host/ls7a.h | 4 +++
2 files changed, 53 insertions(+)
diff --git a/hw/loongarch
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 284
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
target/loongarch/cpu.h | 5 +-
target/loongarch/helper.h| 4 ++
target/loongarch/insn_trans
This patch introduce qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 28
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/qapi/machine
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 2 ++
target/loongarch/insn_trans/trans_core.c | 23 +
target/loongarch/insn_trans/trans_extra.c | 2 ++
target/loongarch
This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 88 +
target/loongarch/csr_helper.c| 112 +
target/loongarch/disas.c | 15
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 1 +
target/loongarch/insn_trans/trans_extra.c.inc | 32 +++
target/loongarch/translate.c | 2 ++
3 files changed
This patch introduce vmstate_loongarch_cpu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c | 3 ++
target/loongarch/internals.h | 4 ++
target/loongarch/machine.c | 84
target
1.This patch Add loongarch interrupt and exception handle.
2.Rename the user excp to the exccode from the csr defintions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
linux-user/loongarch64/cpu_loop.c | 8 +-
target/loongarch/cpu.c| 254
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 9 +
target/loongarch/cpu.h | 10 ++
target/loongarch/meson.build | 1 +
target/loongarch/stabletimer.c | 63 ++
4 files changed, 83 insertions
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 84 ++
include/hw/pci-host/ls7a.h | 13 ++
2 files changed, 97 insertions(+)
diff --git a/hw/loongarch/loongson3.c
son.git/tree/Documentation/loongarch?h=loongarch-next
2.https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 28
1 file changed, 28 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loo
This includes:
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 8 ++
target/loongarch/helper.h| 2 +
target/loongarch/insn_trans/trans_core.c.inc | 103 ++
target/loongarch
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 357
hw/intc/meson.build | 1 +
hw/intc/trace-events
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 41
include/hw/loongarch/loongarch.h | 1 +
3 files changed, 43 insertions(+)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 4
hw/loongarch/fw_cfg.c| 33 ++
hw/loongarch/fw_cfg.h| 15 ++
hw/loongarch/loongson3.c | 35
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 79
include/hw/loongarch/loongarch.h | 5 ++
2 files changed, 84 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index bc3c1920ef
This patch introduces basic TLB interfaces.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-param.h | 2 +-
target/loongarch/cpu.c| 32
target/loongarch/cpu.h| 45 -
target/loongarch/internals.h | 10 +
target/loongarch/machine.c
are emulated.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
.../devices/loongarch64-softmmu/default.mak | 3 +
configs/targets/loongarch64-softmmu.mak | 3 +
hw/Kconfig
on the github.
4.Modify some emulate errors when use the kernel from the github.
5.Adjust some format problem and the Naming problem
6.Others mainly follow Richard's code review comments.
Please help review!
Thanks
Xiaojuan Yang (27):
target/loongarch: Update README
target/loongarch: Add CSR registers
This patch introduce qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 26 ++
2 files changed, 30 insertions(+), 2 deletions
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 236 +
target/loongarch/cpu.c | 35 ++
target/loongarch/cpu.h | 57 +
3
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 2 +
target/loongarch/disas.c | 17
target/loongarch/helper.h| 4 +
target/loongarch
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 +++
hw/intc/loongarch_pch_msi.c | 67 +
hw/intc/meson.build | 1 +
hw/intc/trace-events
Mainly introduce how to run the softmmu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/README | 20
1 file changed, 20 insertions(+)
diff --git a/target/loongarch/README b/target/loongarch/README
index 09f809cf80..49c1f1575a 100644
--- a/target
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_ipi.c | 162
hw/intc/meson.build | 1 +
hw/intc/trace-events
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 499 +
hw/intc/meson.build| 1 +
hw/intc/trace-events
Add a simple acpi model for LoongArch cpu
More complex functions will be added later
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 349 +
hw/acpi/meson.build | 1 +
hw
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/helper.h| 12 +
target/loongarch/insn_trans/trans_core.c.inc
interrupt sources.
For more detailed info about ls7a1000 you can see the doc at
https://github.com/loongson/LoongArch-Documentation/releases/latest/
download/Loongson-7A1000-usermanual-2.00-EN.pdf
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/pci-host/Kconfig| 4 +
hw/pci-host
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 3 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c | 323 +
hw/rtc
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml| 43 +++
gdb-xml/loongarch-fpu64.xml | 57 +++
target/loongarch/cpu.c | 7 ++
target/loongarch
Mainly introduce how to run the softmmu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/README | 20
1 file changed, 20 insertions(+)
diff --git a/target/loongarch/README b/target/loongarch/README
index 09f809cf80..6f64bde22f 100644
--- a/target
This includes:
- CSRRD
- CSRWR
- CSRXCHG
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/csr_helper.c| 322 ++
target/loongarch/helper.h| 11 +
target/loongarch/insn_trans/trans_core.c.inc | 437
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 334 +
target/loongarch/cpu.c | 12 ++
target/loongarch/cpu.h | 127 ++
3
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h| 8 +
target/loongarch/insn_trans/trans_core.c.inc | 71 +++
target/loongarch/insns.decode
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 2 +
target/loongarch/helper.h| 4 +
target/loongarch/insn_trans/trans_core.c.inc | 62 +++
target
the doc at
https://github.com/loongson/LoongArch-Documentation/releases/latest/
download/Loongson-7A1000-usermanual-2.00-EN.pdf
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/pci-host/Kconfig| 4 +
hw/pci-host/ls7a.c | 187 +
hw/pci
1.From Loongson-3A5000 4 cpus belongs to 1 node.
Now support mostly 4 nodes 16 cpus.
2.Different nodes access different address spaces. All
memory access should be handle correctly even nodes
not assigned memory by numa parameters in the command
line.
Signed-off-by: Xiaojuan Yang
Signed
LoongArch is a new RISC ISA, support 32bit mode
or 64bit mode. Now we only add 64bit support.
More detailed info you can see
https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
.../devices/loongarch64-softmmu/default.mak | 3
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 570 +
hw/intc/meson.build| 1 +
hw/loongarch/Kconfig
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ls3a5000_virt.c | 64
include/hw/pci-host/ls7a.h | 4 +++
2 files changed, 68 insertions(+)
diff --git a/hw/loongarch
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/ls3a5000_virt.c | 41
include/hw/loongarch/loongarch.h | 2 ++
3 files changed, 44 insertions(+)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ls3a5000_virt.c | 81
include/hw/loongarch/loongarch.h | 5 ++
2 files changed, 86 insertions(+)
diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c
index 85c8466d75
This patch introduces qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 28
2 files changed, 32 insertions(+), 2 deletions
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/ipi.c | 144 +++
hw/loongarch/ls3a5000_virt.c | 1 +
hw/loongarch/meson.build | 2 +-
include/hw/loongarch/gipi.h
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-31.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig
This patch introduces vmstate_loongarch_cpu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 4 +
target/loongarch/internals.h | 4 +
target/loongarch/machine.c | 154 +++
target/loongarch/meson.build | 6 ++
4
the kernel from the github.
5.Adjust some format problem and the Naming problem
6.Others mainly follow Richard's code review comments.
Please help review!
Thanks
Xiaojuan Yang (30):
target/loongarch: Update README
target/loongarch: Add CSR registers definition
target/loongarch: Add basic
This patch introduces basic TLB interfaces.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-param.h | 3 +
target/loongarch/cpu.c| 36
target/loongarch/cpu.h| 57 ++
target/loongarch/internals.h | 7 +
target/loongarch/machine.c
son.git/tree/Documentation/loongarch?h=loongarch-next
2.https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongarch_int.c | 59
hw/loongarch/ls3a5000_virt.c | 2 ++
hw/loongarch/meson.build
This patch introduces all possible exceptions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 13 +
target/loongarch/cpu.h | 17 +++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.c b/target
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 283
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/ls3a5000_virt.c | 3 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c| 323 +++
hw/rtc
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 4 +++
hw/loongarch/fw_cfg.c| 33 ++
hw/loongarch/fw_cfg.h| 15
hw/loongarch/ls3a5000_virt.c | 60 +---
hw/loongarch
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 73 +
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 11 ++
target/loongarch/meson.build | 1 +
target/loongarch/stabletimer.c | 70 ++
3 files changed, 82 insertions(+)
create mode 100644 target/loongarch
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 1 +
target/loongarch/insn_trans/trans_extra.c.inc | 32 +++
target/loongarch/op_helper.c | 4 +++
target
This patch Add loongarch interrupt and exception handle.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 279 +
1 file changed, 279 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/disas.c | 86
1 file changed, 86 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 1501462991..65aa0443bd 100644
--- a/target/loongarch/disas.c
Use possible_cpus for storing possible topology info
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/acpi-build.c| 16 ++--
hw/loongarch/ls3a5000_virt.c | 35 ++-
2 files changed, 44 insertions(+), 7 deletions(-)
diff --git
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml| 43 +++
gdb-xml/loongarch-fpu64.xml | 57 +++
target/loongarch/cpu.c | 9 +++
target/loongarch
Add a simple acpi model for LoongArch cpu
More complex functions will be added later
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 349 +
hw/acpi/meson.build | 1 +
hw
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 1 +
target/loongarch/insn_trans/trans_extra.c.inc | 32 +++
target/loongarch/op_helper.c | 4 +++
target
This patch introduces all possible exceptions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 13 +
target/loongarch/cpu.h | 17 +++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.c b/target
This patch introduces qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 28
2 files changed, 32 insertions(+), 2 deletions
Mainly introduce how to run the softmmu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/README | 20
1 file changed, 20 insertions(+)
diff --git a/target/loongarch/README b/target/loongarch/README
index 09f809cf80..b307bd4091 100644
--- a/target
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 4 +
target/loongarch/internals.h | 4 +
target/loongarch/machine.c | 154 +++
target/loongarch/meson.build | 6 ++
4 files changed, 168 insertions(+)
create mode
.Others mainly follow Richard's code review comments.
Please review!
Thanks
Xiaojuan Yang (30):
target/loongarch: Update README
target/loongarch: Add CSR registers definition
target/loongarch: Add basic vmstate description of CPU.
target/loongarch: Define exceptions for LoongArch
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 334 +
target/loongarch/cpu.c | 12 ++
target/loongarch/cpu.h | 127 ++
3
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 488
hw/intc/meson.build | 1 +
hw/intc/trace-events
Add tree nodes for 3A5000 device tree.
- cpu nodes;
- fw_cfg nodes;
- pcie nodes.
The lastest loongarch bios have supported fdt.
- https://github.com/loongson/edk2
- https://github.com/loongson/edk2-platforms
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c
1.This patch Add loongarch interrupt and exception handle.
2.Rename the user excp to the exccode from the csr defintions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
linux-user/loongarch64/cpu_loop.c | 8 +-
target/loongarch/cpu.c| 251
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/constant_timer.c | 62 +++
target/loongarch/cpu.h| 10 +
target/loongarch/meson.build | 1 +
3 files changed, 73 insertions(+)
create mode 100644 target/loongarch
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 417 +
hw/intc/meson.build| 1 +
hw/intc/trace-events
- We write a very minimal softmmu harness.
- This is a very simple smoke test with no need to run a full Linux/kernel.
- The Makefile.softmmu-target record the rule to run.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS | 1 +
tests/tcg
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h| 2 +
target/loongarch/disas.c | 17
target/loongarch/helper.h | 4 +
.../insn_trans
Add a simple acpi model for LoongArch cpu
More complex functions will be added later
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS | 2 +
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 374 ++
hw/acpi
nto one.
2.Adjust the order of the patch.
3.Put all the binaries on the github.
4.Modify some emulate errors when use the kernel from the github.
5.Adjust some format problem and the Naming problem
6.Others mainly follow Richard's code review comments.
Please help review!
Thanks
Xiaojuan Yang (29)
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 43
include/hw/loongarch/loongarch.h | 1 +
3 files changed, 45 insertions(+)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch
nto one.
2.Adjust the order of the patch.
3.Put all the binaries on the github.
4.Modify some emulate errors when use the kernel from the github.
5.Adjust some format problem and the Naming problem
6.Others mainly follow Richard's code review comments.
Please help review!
Thanks
Xiaojuan Yang (29)
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 75 +
hw/intc/meson.build | 1 +
hw/intc/trace-events
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS | 2 +
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml| 43 +++
gdb-xml/loongarch-fpu64.xml | 57 +++
target/loongarch/cpu.c
son.git/tree/Documentation/loongarch?h=loongarch-next
2.https://github.com/loongson/LoongArch-Documentation
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongar
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 7
1 - 100 of 645 matches
Mail list logo
