On Tue, Mar 20, 2012 at 03:13:33PM +, Peter Maydell wrote:
On 20 March 2012 14:57, Liming Wang walimis...@gmail.com wrote:
Vexpress motherboard has two 2x16 NOR flash, but pflash_cfi01
doesn't support interleaving, so here only models two 1x32 flash.
Although it's not exactly modeled
On Tue, Mar 20, 2012 at 04:13:43PM +, Peter Maydell wrote:
On 20 March 2012 16:00, walimis walimis...@gmail.com wrote:
On Tue, Mar 20, 2012 at 03:13:33PM +, Peter Maydell wrote:
On 20 March 2012 14:57, Liming Wang walimis...@gmail.com wrote:
Vexpress motherboard has two 2x16 NOR flash
info by
define PFLASH_DEBUG if we want to debug pflash_cfi01.
Signed-off-by: Liming Wang walimis...@gmail.com
---
hw/pflash_cfi01.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 2e6fa71..4e39ea6 100644
--- a/hw/pflash_cfi01.c
+++ b
On Tue, Nov 20, 2012 at 02:32:33PM +1000, Peter Crosthwaite wrote:
Hi Liming,
On Mon, Nov 19, 2012 at 11:03 PM, Liming Wang walimis...@gmail.com wrote:
The jedec id of n25q128 should be 0x20bb18, not 0x20ba18.
Signed-off-by: Liming Wang walimis...@gmail.com
---
hw/m25p80.c |2 +-
1
Hi, Peter
On Mon, Oct 29, 2012 at 04:45:00PM +1000, Peter Crosthwaite wrote:
Added the QSPI controller to the Zynq. 4 SPI devices are attached to allow
modelling of the different geometries. E.G. Dual parallel and dual stacked
mode can both be tested with this one arrangement.
Signed-off-by:
On Sat, Nov 24, 2012 at 11:03:13PM +0100, Stefan Weil wrote:
There are several ARM and MIPS boards which are manufactured with
either Intel (pflash_cfi01.c) or AMD (pflash_cfi02.c) flash memory.
The Linux kernel supports both and first probes for AMD flash which
resulted in one or two warnings
fix for sysbus EHCI.
I have also found this issue, but it's not the cause that xilinx
ehci can't work with usb-storage disk. Do you have any update
for xilinx ehci?
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Tested-by: Liming Wang walimis...@gmail.com
Liming Wang
---
hw/usb
On Tue, Nov 20, 2012 at 02:32:33PM +1000, Peter Crosthwaite wrote:
Hi Liming,
On Mon, Nov 19, 2012 at 11:03 PM, Liming Wang walimis...@gmail.com wrote:
The jedec id of n25q128 should be 0x20bb18, not 0x20ba18.
Signed-off-by: Liming Wang walimis...@gmail.com
---
hw/m25p80.c |2 +-
1
: Liming Wang walimis...@gmail.com
Cc: Vincent Palatin vpala...@chromium.org
Andreas Färber (4):
usb/ehci: Clean up SysBus and PCI EHCI split
usb/ehci: Move capsbase and opregbase into SysBus EHCI class
usb/ehci: Add SysBus EHCI device for Exynos4210
usb/ehci: Add Tegra2 SysBus EHCI device
On Sun, Dec 02, 2012 at 05:27:16PM +0100, Andreas F鋜ber wrote:
Am 02.12.2012 11:34, schrieb walimis:
On Sun, Dec 02, 2012 at 03:57:17AM +0100, Andreas F鋜ber wrote:
Appended is Liming's patch to add an EHCI device to Exynos 4 as well as a
new patch of mine to prepare a Tegra 2 EHCI device (cf
On Mon, Dec 03, 2012 at 07:59:55AM +0100, Gerd Hoffmann wrote:
Hi,
Gerd: In order for me to use this with the new-style Tegra2 model we
will need to further move EHCISysBusState and the accompanying macros
that this series adds into the hcd-ehci.h header so that it can be
embedded into the
On Thu, Nov 29, 2012 at 12:05:14PM +1000, Peter Crosthwaite wrote:
On Thu, Nov 29, 2012 at 12:00 PM, walimis walimis...@gmail.com wrote:
On Thu, Nov 29, 2012 at 11:43:18AM +1000, Peter Crosthwaite wrote:
This was left as NULL on the initial merge due to debate on the mailing list
on
how
On Mon, Dec 03, 2012 at 12:10:02PM +, Peter Maydell wrote:
On 3 December 2012 11:58, walimis walimis...@gmail.com wrote:
For example, xilinx_zynq has two EHCI controllers. If I specify a usb
device of type usb-storage, the question is: which EHCI controller does the
usb device attach
On Mon, Dec 03, 2012 at 01:51:00PM +0100, Gerd Hoffmann wrote:
Hi,
As said in another mail, I found that the root cause is that xilinx_zynq has
two EHCI controller. If we use usb-storage disk, the disk will be attached to
the second EHCI controller, which the kernel uses the first EHCI
On Mon, Dec 03, 2012 at 10:51:49PM +0400, Igor Mitsyanko wrote:
On 12/02/2012 06:57 AM, Andreas Färber wrote:
It uses a different capsbase and opregbase than the Xilinx device.
Signed-off-by: Liming Wang walimis...@gmail.com
Signed-off-by: Andreas Färber andreas.faer...@web.de
Cc: Igor Mitsyanko
On Tue, Dec 04, 2012 at 03:16:09PM +1000, Peter Crosthwaite wrote:
Hi Liming, Gerd,
On Tue, Dec 4, 2012 at 12:50 AM, walimis walimis...@gmail.com wrote:
On Mon, Dec 03, 2012 at 01:51:00PM +0100, Gerd Hoffmann wrote:
Hi,
As said in another mail, I found that the root cause is that xilinx_zynq
On Mon, Dec 03, 2012 at 10:51:49PM +0400, Igor Mitsyanko wrote:
On 12/02/2012 06:57 AM, Andreas Färber wrote:
It uses a different capsbase and opregbase than the Xilinx device.
Signed-off-by: Liming Wang walimis...@gmail.com
Signed-off-by: Andreas Färber andreas.faer...@web.de
Cc: Igor Mitsyanko
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