Re: [PATCH RFC] target: riscv: Add Svvptc extension support

Hi Andrew, Sorry for the very late reply, I was (and still am) off! On Tue, Feb 13, 2024 at 4:33 PM Andrew Jones wrote: > > On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote: > > The Svvptc extension describes a uarch that does not cache invalid TLB > > entrie

[PATCH RFC] target: riscv: Add Svvptc extension support

The Svvptc extension describes a uarch that does not cache invalid TLB entries: that's the case for qemu so there is nothing particular to implement other than the introduction of this extension, which is done here. Signed-off-by: Alexandre Ghiti --- That's an RFC since the extension has

Re: [PATCH v2] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM

On Tue, Feb 6, 2024 at 9:39 PM Daniel Henrique Barboza wrote: > > > > On 2/6/24 12:40, Alexandre Ghiti wrote: > > Currently, the initrd is placed at 128MB, which overlaps with the kernel > > when it is large (for example syzbot kernels are). From the kernel side, > &g

[PATCH v2] hw: riscv: Allow large kernels to boot by moving the initrd further away in RAM

. The ideal solution would have been to place the initrd based on the kernel size but we actually can't since the bss size is not known when the image is loaded by load_image_targphys_as() and the initrd would then overlap with this section. Signed-off-by: Alexandre Ghiti --- Changes in v2: - Fix typos

Re: [PATCH] hw: riscv: Allow large kernels to boot by moving the initrd further way in RAM

Hi Daniel, On Mon, Feb 5, 2024 at 2:36 PM Alexandre Ghiti wrote: > > Hi Daniel, > > On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza > wrote: > > > > > > > > On 2/5/24 04:00, Alexandre Ghiti wrote: > > > Currently, the initrd is placed at

Re: [PATCH] hw: riscv: Allow large kernels to boot by moving the initrd further way in RAM

Hi Daniel, On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza wrote: > > > > On 2/5/24 04:00, Alexandre Ghiti wrote: > > Currently, the initrd is placed at 128MB, which overlaps with the kernel > > when it is large (for example syzbot kernels ar

[PATCH] hw: riscv: Allow large kernels to boot by moving the initrd further way in RAM

-off-by: Alexandre Ghiti --- hw/riscv/boot.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05189..9a367af2fa 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -188,13 +188,13 @@ static void riscv_load_initrd

Re: [PATCH v2] riscv: Make sure an exception is raised if a pte is malformed

On Thu, Apr 20, 2023 at 1:31 AM Alistair Francis wrote: > > On Wed, Apr 19, 2023 at 8:48 PM Alexandre Ghiti > wrote: > > > > As per the privileged specification, in 64-bit, if any of the pte reserved > > bits 60-54 is set an exception should be triggered, and the sam

[PATCH v3] riscv: Make sure an exception is raised if a pte is malformed

Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis --- Changes in v3: - Rebase on top of https://github.com/alistair23/qemu/tree/riscv-to-apply.next Changes in v2: - Handle napot and pbmt exception target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 15 +++ 2 fil

[PATCH v2] riscv: Make sure an exception is raised if a pte is malformed

Signed-off-by: Alexandre Ghiti --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 15 +++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fca7ef0cef..8d9ba2ce11 100644 --- a/target/riscv/cpu_bits.h +++ b/ta

Re: [PATCH] riscv: Raise an exception if pte reserved bits are not cleared

Hi Alistair, Sorry for the late reply, I was on PTO. On Tue, Apr 18, 2023 at 4:22 AM Alistair Francis wrote: > > On Mon, Apr 17, 2023 at 8:47 PM Andrea Parri wrote: > > > > Hi Alistair, > > > > > > @@ -936,6 +936,11 @@ restart: > > > > return TRANSLATE_FAIL; > > > > } > >

[PATCH] riscv: Raise an exception if pte reserved bits are not cleared

As per the specification, in 64-bit, if any of the pte reserved bits 60-54 is set, an exception should be triggered (see 4.4.1, "Addressing and Memory Protection"), so implement this behaviour in the address translation process. Reported-by: Andrea Parri Signed-off-by: Alexa

Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode

Use custom boolean properties instead of OnOffAuto properties, based > > on ARMVQMap, as suggested by Andrew > > > > v3: > > - Free sv_name as pointed by Bin > > - Replace satp-mode with boolean properties as suggested by Andrew > > - Removed RB from Atish as the patch co

[PATCH v11 5/5] riscv: Correctly set the device-tree entry 'mmu-type'

The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- hw/riscv/virt.c | 19

[PATCH v11 4/5] riscv: Introduce satp mode hw capabilities

select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 93

[PATCH v11 3/5] riscv: Allow user to set the satp mode

v64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 214 +++

[PATCH v11 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool

This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair

[PATCH v11 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState

One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Reviewed

[PATCH v11 0/5] riscv: Allow user to set the satp mode

y Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mo

Re: [PATCH v10 0/5] riscv: Allow user to set the satp mode

; comment in patch 3 can also be handled during the process. Sure I'll do that today, Thanks, Alex > > > Thanks, > > > Daniel > > > > > > > > > Thanks, > > > > > > Daniel > > > > > > > > > > On

[PATCH v10 5/5] riscv: Correctly set the device-tree entry 'mmu-type'

The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Frank Chang --- hw/riscv/virt.c | 19

[PATCH v10 4/5] riscv: Introduce satp mode hw capabilities

select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng --- target/riscv/cpu.c | 91 +- target/riscv/cpu.h | 8 +++- 2 files changed, 72 insertions

[PATCH v10 3/5] riscv: Allow user to set the satp mode

v64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Acked-by: Alistair Francis --- target/riscv/cpu.c | 215

[PATCH v10 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool

This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair

[PATCH v10 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState

One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Reviewed

[PATCH v10 0/5] riscv: Allow user to set the satp mode

from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceSta

Re: [PATCH v9 4/5] riscv: Introduce satp mode hw capabilities

Hi Frank, On Wed, Feb 1, 2023 at 4:49 PM Frank Chang wrote: > > On Tue, Jan 31, 2023 at 10:36 PM Alexandre Ghiti > wrote: >> >> Currently, the max satp mode is set with the only constraint that it must be >> implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].

Re: [PATCH v8 4/5] riscv: Introduce satp mode hw capabilities

On Mon, Jan 30, 2023 at 5:29 AM Bin Meng wrote: > > On Thu, Jan 26, 2023 at 12:24 AM Alexandre Ghiti > wrote: > > > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].

[PATCH v9 3/5] riscv: Allow user to set the satp mode

v64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 207 + target/riscv/cpu.h | 19 + target/

Re: [PATCH v8 3/5] riscv: Allow user to set the satp mode

On Wed, Jan 25, 2023 at 5:52 PM Andrew Jones wrote: > > On Wed, Jan 25, 2023 at 05:20:08PM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in >

[PATCH v9 4/5] riscv: Introduce satp mode hw capabilities

select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 79 +++--- target/riscv/cpu.h | 8 +++-- 2 files changed, 60 insertions(+), 27 deletions

[PATCH v9 0/5] riscv: Allow user to set the satp mode

- Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre

[PATCH v9 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState

One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Reviewed

[PATCH v9 5/5] riscv: Correctly set the device-tree entry 'mmu-type'

The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/virt.c | 19 ++- 1 file changed

[PATCH v9 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool

This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair

Re: [PATCH v8 3/5] riscv: Allow user to set the satp mode

Hi Bin, On Mon, Jan 30, 2023 at 5:22 AM Bin Meng wrote: > > On Thu, Jan 26, 2023 at 12:23 AM Alexandre Ghiti > wrote: > > > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via

[PATCH v8 5/5] riscv: Correctly set the device-tree entry 'mmu-type'

The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 19 ++- 1 file changed, 10 insertions(+), 9

[PATCH v8 4/5] riscv: Introduce satp mode hw capabilities

select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 74 +++--- target/riscv/cpu.h | 8 +++-- 2 files changed, 56 insertions(+), 26 deletions

[PATCH v8 3/5] riscv: Allow user to set the satp mode

v64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 206 + target/riscv/cpu.h | 19 + target/riscv/csr.c | 12 ++- 3 files

[PATCH v8 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool

This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair

[PATCH v8 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState

One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones --- target

[PATCH v8 0/5] riscv: Allow user to set the satp mode

with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode riscv: Introduce satp mode hw capabilities riscv: Correctly set the device-tree entry 'mmu-type' hw

Re: [PATCH v7 3/5] riscv: Allow user to set the satp mode

On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote: > > On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in >

[PATCH v7 5/5] riscv: Correctly set the device-tree entry 'mmu-type'

The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 19 ++- 1 file changed, 10 insertions(+), 9

[PATCH v7 4/5] riscv: Introduce satp mode hw capabilities

select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 74 +++--- target/riscv/cpu.h | 8 +++-- 2 files changed, 56 insertions(+), 26 deletions(-) diff --git a/target/riscv

[PATCH v7 3/5] riscv: Allow user to set the satp mode

v64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 207 + target/riscv/cpu.h | 19 + target/riscv/csr.c | 12 ++- 3 files

[PATCH v7 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool

This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair

[PATCH v7 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState

One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones --- target

[PATCH v7 0/5] riscv: Allow user to set the satp mode

as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object

Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities

On Mon, Jan 23, 2023 at 2:51 PM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > &g

Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities

On Mon, Jan 23, 2023 at 2:31 PM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 12:15:08PM +0100, Alexandre Ghiti wrote: > > On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones > > wrote: > > > > > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:

Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities

On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > >

Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode

On Mon, Jan 23, 2023 at 11:29 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > ... > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +{ > > ni

Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode

On Mon, Jan 23, 2023 at 11:14 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in >

Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode

Hi Andrew, On Mon, Jan 23, 2023 at 11:11 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp

Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities

Hi Alistair, On Tue, Jan 24, 2023 at 1:41 AM Alistair Francis wrote: > > On Mon, Jan 23, 2023 at 7:09 PM Alexandre Ghiti > wrote: > > > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1

Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities

On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > >

[PATCH v6 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState

One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Signed-off-by: Alexandre Ghiti --- target

[PATCH v6 5/5] riscv: Introduce satp mode hw capabilities

igned-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 78 +++--- target/riscv/cpu.h | 8 +++-- 2 files changed, 59 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e409e6ab64..19a37fee2b 100644 --- a/target/ri

[PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type'

The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti --- hw/riscv/virt.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv

[PATCH v6 3/5] riscv: Allow user to set the satp mode

ot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme In addition, we now correctly set the device-tree entry 'mmu-type' using those new properties. Co-Developed-by: Ludovic Henry Signed-off-by: Ludovi

[PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool

This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Signed-off-by: Alexandre Ghiti --- target/riscv/csr.c | 21 +++-- 1 file changed, 11

[PATCH v6 0/5] riscv: Allow user to set the satp mode

-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5

Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode

On Fri, Jan 20, 2023 at 10:53 AM Andrew Jones wrote: > > On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote: > > On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti > > wrote: > > > > > > Hi Alistair, Andrew, > > > > > > On Thu,

Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode

Andrew Jones > > > wrote: > > > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > ... > > > > > + > > > > > +/* Get rid of 32-bit/64-bit incompatibility */ > > > > > +for (int i = 0; i < 16; ++i)

Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode

Hey Andrew, On Tue, Jan 17, 2023 at 5:31 PM Andrew Jones wrote: > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp

[PATCH v5 2/2] riscv: Allow user to set the satp mode

t using sv48 scheme -cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default) In addition, we now correctly set the device-tree entry 'mmu-type' using those new properties. Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexand

[PATCH v5 1/2] riscv: Pass Object to register_cpu_props instead of DeviceState

One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions

[PATCH v5 0/2] riscv: Allow user to set the satp mode

with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (2): riscv

Re: [PATCH v4] riscv: Allow user to set the satp mode

Hey Andrew, Sorry about the response delay, I was traveling. On Fri, Jan 6, 2023 at 4:30 PM Andrew Jones wrote: > > On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the

Re: [PATCH v4] riscv: Allow user to set the satp mode

On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti wrote: > > Hi Frank, > > On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote: > > > > Hi Alexandre, > > > > Thanks for the contribution. This is really helpful. > > > > It seems like if we want to sp

Re: [PATCH v4] riscv: Allow user to set the satp mode

lt satp mode for the current cpus in each cpu init function too. Thanks for your remarks, Alex > > Regards, > Frank Chang > > > On Mon, Dec 12, 2022 at 6:23 PM Alexandre Ghiti > wrote: >> >> RISC-V specifies multiple sizes for addressable memory and Lin

[PATCH v4] riscv: Allow user to set the satp mode

se new properties. Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- v4: - Use custom boolean properties instead of OnOffAuto properties, based on ARMVQMap, as suggested by Andrew v3: - Free sv_name as pointed by Bin - Replace satp-mode wit

Re: [PATCH v3] riscv: Allow user to set the satp mode

Hi Andrew, On Thu, Dec 1, 2022 at 3:47 PM Andrew Jones wrote: > On Thu, Dec 01, 2022 at 10:36:23AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes > for > > the machine's support at startup via the satp

[PATCH v3] riscv: Allow user to set the satp mode

se new properties. Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- v3: - Free sv_name as pointed by Bin - Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg

[PATCH v2] riscv: Add RISCVCPUConfig.satp_mode to set sv48, sv57, etc.

correctly set the device-tree entry 'mmu-type' using this new satp_mode property. Reviewed-by: Atish Patra Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpa

[PATCH] riscv: Add RISCVCPUConfig.satp_mode to set sv48, sv57, etc.

correctly set the device-tree entry 'mmu-type' using this new satp_mode property. Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- hw/riscv/virt.c| 15 ++- target/riscv/cpu.c | 45 + ta