Recently the Linux kernel started to use a non default value, for
the scounteren CSR, which is ignored by QEMU. Fix that by implementing
the PMU CSR predicate function for U-mode.
Signed-off-by: Aurelien Jarno
---
target/riscv/csr.c | 49 ++
1 file
On 2022-09-02 18:46, Aurelien Jarno wrote:
> Recently the Linux kernel started to use a non default value, for
> the scounteren CSR, which is ignored by QEMU. Fix that by implementing
> the PMU CSR predicate function for U-mode.
>
> Signed-off-by: Aurelien Jarno
> ---
> ta
Signed-off-by: Aurelien Jarno
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index dec252f38b..0535e043f0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -130,7 +130,6 @@ F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
FPU emulation
-M: Aurelien
On 2020-07-01 20:55, Aurelien Jarno wrote:
> NACK
This NACK was because I find inacceptable to claim that you got not
answer from Paul or from myself after very few time.
Now about the content of the patch, QEMU used to be a fun ride, but it
happens that interactions are now hurtful, especia
Aleksandar,
On 2020-07-01 20:51, Aleksandar Markovic wrote:
> On Wed, Jul 1, 2020 at 7:39 PM Aurelien Jarno wrote:
> >
> > Aleksandar,
> >
> > On 2020-06-30 23:54, Aleksandar Markovic wrote:
> > > As, in a very clear way, evidenced from the previous versio
pointed out. However, I am still concerned by the way things
happened.
Regards,
Aurelien
On 2020-06-30 18:46, Aleksandar Markovic wrote:
> Paul Burton and Aurelien Jarno removed for not being present.
>
> Huacai Chen and Jiaxun Yang step in as new energy.
>
> CC: Paul Burton
NACK
On 2020-07-01 20:25, Aleksandar Markovic wrote:
> Paul Burton and Aurelien Jarno removed for not being present.
> A polite email was sent to them with question whether they
> intend to actively participate, but there was no response.
I indeed received a polite email, but it was
gt;
> > Philippe Mathieu-Daudé (5):
> > hw/mips/malta: Trivial code movement
> > hw/mips/malta: Register the machine as a TypeInfo
> > hw/mips/malta: Introduce MaltaMachineClass::max_ramsize
> > hw/mips/malta: Introduce the 'malta-strict' machine
> > hw
On 2020-06-08 11:01, Philippe Mathieu-Daudé wrote:
> Aurelien Jarno expressed his desire to orphan the SH4 target [*]:
>
> I don't mind being [...] removed from there.
> I do not really have time to work on that.
>
> Mark the SH4 TCG target orphan.
>
> Many th
S
> index 0944d9c731..cbba3ac757 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -298,9 +298,7 @@ SH4 TCG CPUs
> M: Aurelien Jarno
> S: Odd Fixes
> F: target/sh4/
> -F: hw/sh4/
> F: disas/sh4.c
> -F: include/hw/sh4/
>
> SPARC TCG CPUs
> M: Mark Cave-Aylan
ducing a malta-5.0 machine restricted to
> 1GB?
In any case having an easy way to simulate machines with more than 2GB
of RAM in QEMU would be great.
Cheers,
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
iner's
> duties for QEMU for MIPS items. Aurelien is though welcome to come
> back at any time. Some empty spots caused by this are filled in by
> Aleksandar.
>
> CC: Aurelien Jarno
> Signed-off-by: Aleksandar Markovic
> ---
> MAINTAINERS | 8 +---
> 1 file chang
Hi,
On 2020-01-20 10:31, Alistair Francis wrote:
> On Mon, Jan 6, 2020 at 2:59 AM Aurelien Jarno wrote:
> >
> > On 2020-01-05 17:36, Aurelien Jarno wrote:
> > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > > > index e0d4586760..2789215b5e
On 2020-01-05 17:36, Aurelien Jarno wrote:
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index e0d4586760..2789215b5e 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
>
> [ snip ]
>
> > @@ -307,6 +307,7 @@ static int writ
ATUS_FS) == MSTATUS_FS)) |
-((mstatus & MSTATUS_XS) == MSTATUS_XS);
+int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
env->mstatus = mstatus;
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
es changed, 7 insertions(+), 1 deletion(-)
The Linux kernel support for this machine has been dropped more than 10
years ago in this commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=302922e5f6901eb6f29c58539631f71b3d9746b8
I therefore think it's time to also
tions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4a478f8..1a49381 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -941,8 +941,9 @@ F: hw/display/jazz_led.c
> F: hw/dma/rc4030.c
>
> Malta
> -M: Aurelien Jarno
> -R: Aleksandar Rikalo
> +M: Philippe Mathi
tions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1a49381..62e7d6d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -957,8 +957,9 @@ F: hw/mips/mips_mipssim.c
> F: hw/net/mipsnet.c
>
> R4000
> -M: Aurelien Jarno
> -R: Aleksandar Rikalo
> +M: Hervé Po
tions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4a478f8..1a49381 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -941,8 +941,9 @@ F: hw/display/jazz_led.c
> F: hw/dma/rc4030.c
>
> Malta
> -M: Aurelien Jarno
> -R: Aleksandar Rikalo
> +M: Philippe Mathi
n-extended to 64-bit in case of an instruction fetch. The trap_arg2
ends up with 0x instead of 0x. Fix that by
changing the -1 into -1LL.
This fixes the execution of user space processes in qemu-system-alpha.
Fixes: e41c94529740cc26
Cc: qemu-sta...@nongnu.org
Signed-off-by: Aure
On 2019-02-26 16:44, Alex Bennée wrote:
> I'm basing this on email addresses or published employment. Please
> confirm if this is correct or you want to be under (None).
Please list me as (None) instead, QEMU is not related to my paid work.
Aurelien
--
Aurelien
et/sh4: Convert to DisasJumpType")
> >> Reported-by: John Paul Adrian Glaubitz
> >> Signed-off-by: Laurent Vivier
> >> ---
> >>
> >> Notes:
> >> v2:
> >> don't revert the part of the original patch,
> >> but fixes th
te for 2048-bit
> vector registers.
>
> Note that tcg/mips has the exact same problem. However, the mips isa
> makes it more difficult to fix up. I'd like someone with hardware to
> make this change.
Ok, I'll try to have a look at that.
--
Aurelien Jarno
but that's
what is still done for at least x86 for the trigonometrical functions.
The check prevents assigning a float or double value to a softfloat type
without calling the conversion function.
Now, when we make sure that those ugly things are removed, I think these
type-checking m
;
Message-Id: <20170907185057.23421-4-richard.hender...@linaro.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
inde
From: Richard Henderson <r...@twiddle.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
[aurel32: fix whitespace]
Message-Id: <20170907185057.23421-5-richard.hender...@linaro.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
targ
<glaub...@physik.fu-berlin.de>
Suggested-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-Id: <20171206093050.25308-1-alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-
-richard.hender...@linaro.org>
[aurel32: fix whitespace]
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
linux-user/main.c | 19 +---
target/sh4/cpu.h | 4 ++-
target/sh4/helper.c| 1 +
target/sh4/translate.c | 82 ---
From: Richard Henderson <r...@twiddle.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170907185057.23421-3-richard.hender...@linaro.org>
[aurel32: fix whitespace]
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tar
The following changes since commit eaefea537b476cb853e2edbdc68e969ec777e4bb:
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into
staging (2017-12-18 14:17:42 +)
are available in the Git repository at:
git://git.aurel32.net/qemu.git tags/pull-target-sh4-20171218
From: Philippe Mathieu-Daudé <f4...@amsat.org>
missed in c55497ecb8c and 852d481faf7.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-Id: <20171205170013.22337-3-f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Aurelien
is not a valid register, then op_arg was a constant. */
> -if (op_src < 0) {
> +if (op_src < 0 && !TCGV_IS_UNUSED(op_arg)) {
> tcg_temp_free_i32(op_arg);
> }
I guess this happens when trying to match the exchange pattern, so this
looks correct to me.
Reviewed-by
inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
AFAIR, temps are not preserved across a branch (contrary to local
temps), so I am not sure they need to be freed.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
; tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL);
> gen_helper_movcal(cpu_env, REG(B11_8), val);
> tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
> +tcg_temp_free(val);
> }
> ctx->has_movcal = 1
by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/mips/tcg-target.inc.c | 52
> +++
> 1 file changed, 26 insertions(+), 26 deletions(-)
Looks good to me.
Acked-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
On 2017-09-01 11:30, Eduardo Habkost wrote:
> i82374 is compiled in only on ppc and sh4, so I'm CCing the
> maintainers for those architectures.
The i82374 device is not useful nor usable on SH4. It has just been
added in commit 85d3846a39 to be able to run the tests.
Aurelien
--
Au
ory.
Therefore reserve 128kiB after the initrd.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
hw/mips/mips_malta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 8ecd544baa..9dcec27304 100644
---
AINTAINERS
> +++ b/MAINTAINERS
> @@ -235,6 +235,7 @@ F: target/sh4/
> F: hw/sh4/
> F: disas/sh4.c
> F: include/hw/sh4/
> +F: default-configs/sh4*-softmmu.mak
>
> SPARC
> M: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Acked-by: Aurelien Jarno <aurel...@au
little and big endian kernels.
Alexey Kardashevskiy (1):
Revert "elf-loader: warn about invalid endianness"
Aurelien Jarno (1):
hw/mips: load_elf_strerror to report kernel loading failure
hw/core/loader.c| 1 -
hw/mips/mips_fulong2e.c | 15 +--
hw/mips/mi
avoid such
> > problems.
> > I don't object reverting this patch for 2.10 and improve the loader.c usage
> > during 2.11 cycle, I only wonder if this is another corporate/hobbyist>
> > conflict of interest with corporate crushing on hobbyist instead of
>
> Come on mate...
ENDIAN and tries with big_endian=0.
Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
hw/core/loader.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index c17ace0a2e..e5e8cbb638 100644
Emulated MIPS boards bail out with a simple "could not load kernel" when
a kernel could not be load, without specifying the underlying reason.
Fix that by calling load_elf_strerror.
At the same time use error_report to report the error instead of
fprintf.
Signed-off-by: Aurelien Ja
On 2017-07-21 14:58, Peter Maydell wrote:
> On 21 July 2017 at 14:50, Alex Bennée <alex.ben...@linaro.org> wrote:
> > Aurelien Jarno <aurel...@aurel32.net> writes:
> >> As said in another email, some architectures actually use more than one
> >> float
unity POV. At least v3 has the possibility to be become more
> community driven in future, where as v2 is essentially now a obsolete
> version.
It depends if we are able to get (at least part of) our changes
upstreamed. Switching to softfloat v3 is likely to be a substantial
effo
oftfloat2a code in it's
> specialise header. Maybe we should rename 8086-SSE to default and then
> create a specialisation for each guest that needs it?
For the sNaN is 0 or 1 specialisation we actually need to be able to
select this at runtime, as we have implemented it in the QEMU softfloat
version.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ter, when the front
> > end is fully converted? That's just nonsense.
>
> Wouldn't the other option to be to drop float_status out of the guests
> CPUEnv and grab it from the TLS variable instead? Of course all guests
> would need to be MTTCG enabled for that to work.
As said in another email, some architectures actually use more than one
float_status. We therefore need to implement a solution like the one
proposed by Richard.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
as we have one thread per VCPU (which is the
case with MTTCG). However, how do you plan to handle the switch from one
FPU state to another for the architectures using multiple FPU contexts?
That concerns at least arm, i386, mips and ppc.
Regards,
Aurelien
--
Aurelien Jarno
On 2017-07-19 14:44, James Hogan wrote:
> On Wed, Jul 19, 2017 at 12:27:50PM +0200, Aurelien Jarno wrote:
> > On 2017-07-18 12:55, James Hogan wrote:
> > > Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however
> > > CP0_UserLocal is a target_ulong. On a bi
+ offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
> +tcg_gen_ext32s_tl(arg, arg);
> rn = "UserLocal";
> break;
> default:
I think this is what gen_mfc0_load64() does, that said this whole area
proba
On 2017-07-18 15:40, no-re...@patchew.org wrote:
> Hi,
>
> This series failed automatic build test. Please find the testing commands and
> their output below. If you have docker installed, you can probably reproduce
> it
> locally.
>
> Subject: [Qemu-devel] [PULL 00/31] target/sh4 queue
>
avoided in .c files
> #22: FILE: target/sh4/translate.c:476:
> +CHECK_FPSCR_PR_0
>
> ERROR: externs should be avoided in .c files
> #27: FILE: target/sh4/translate.c:481:
> +CHECK_FPSCR_PR_0
>
> total: 2 errors, 0 warnings, 12 lines checked
>
> Your patch has style problems, please review. If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
>
> Checking PATCH 30/31: target/sh4: Implement fsrra...
> Checking PATCH 31/31: target/sh4: Use tcg_gen_lookup_and_goto_ptr...
> === OUTPUT END ===
>
> Test command exited with code: 1
>
Those are all false positives.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
8200255.31647-8-...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 321 +
1 file changed, 321 insertions(+)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a4e614d0f7..385b69ef14
From: Richard Henderson <r...@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-13-...@twiddle.net>
[aurel32: fix
From: Richard Henderson <r...@twiddle.net>
We were treating FREG as an index and REG as a TCGv.
Making FREG return a TCGv is both less confusing and
a step toward cleaner banking of cpu_fregs.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel
net>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/op_helper.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index f228daf125.
me way. Instead, we notice
the normal start of such a sequence (mov #-x,r15), and start a new TB
that can be executed under cpu_exec_step_atomic.
Reported-by: Bruno Haible <br...@clisp.org>
LP: https://bugs.launchpad.net/bugs/1701971
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Sign
Message-Id: <20170718200255.31647-17-...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 75 --
1 file changed, 36 insertions(+), 39 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/tran
From: Richard Henderson <r...@twiddle.net>
If we mask off any out-of-band bits before we assign to the
variable, then we don't need to clean it up when reading.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Sign
From: Richard Henderson <r...@twiddle.net>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-24-...@twiddle.net>
[aurel32: fix conflict]
Signed-off-by: Aurelien Jarno <aurel...@a
From: Richard Henderson <r...@twiddle.net>
We do not need to emit N copies of raising an exception.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id:
From: Richard Henderson <r...@twiddle.net>
Now that we have a do_illegal label, use goto in order
to self-document the forcing of the exception.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Ri
From: Richard Henderson <r...@twiddle.net>
We do not need to emit N copies of raising an exception.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id:
From: Richard Henderson <r...@twiddle.net>
Both frchg and fschg require PR == 0, otherwise undefined_operation.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-26-...@twiddle.net>
From: Richard Henderson <r...@twiddle.net>
Compute which register bank to use once at the start of translation.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-14-...@twiddle.net>
3-5-aurel...@aurel32.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h| 8
target/sh4/op_helper.c | 16
target/sh4/translate.c | 10 ++
3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/sh4/hel
From: Richard Henderson <r...@twiddle.net>
We do not need to form full 64-bit quantities in order to perform
the move. This reduces code expansion on 64-bit hosts.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.
From: Richard Henderson <r...@twiddle.net>
We translate gUSA regions atomically in a parallel context.
But in a serial context a gUSA region may be interrupted.
In that case, restart the region as the kernel would.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off
From: Richard Henderson <r...@twiddle.net>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-23-...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
--
From: Richard Henderson <r...@twiddle.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-27-...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h| 1 +
target/sh4/op_helper.c | 16
From: Richard Henderson <r...@twiddle.net>
We'll be putting more things into this bitmask soon.
Let's have a name that covers all possible uses.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Ri
From: Richard Henderson <r...@twiddle.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-28-...@twiddle.net>
[aurel32: fix whitespace]
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 30 +
viewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-10-...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
linux-user/signal.c | 3 +++
1 file changed, 3 insertions(+)
diff
From: Richard Henderson <r...@twiddle.net>
Also add a debugging assert that we did signal illegal opc
for odd double-precision registers.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.316
From: Richard Henderson <r...@twiddle.net>
We do not need to emit N copies of raising an exception.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id:
There is no need to use a helper to flip one bit, just use a TCG xor
instruction instead.
Message-Id: <20170702202814.27793-5-aurel...@aurel32.net>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/helper.h
From: Richard Henderson <r...@twiddle.net>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-25-...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
targe
the check, and at the same time use a TCG instruction instead of
a helper to clear one bit.
LP: https://bugs.launchpad.net/qemu/+bug/1701821
Reported-by: Bruno Haible <br...@clisp.org>
Message-Id: <20170702202814.27793-2-aurel...@aurel32.net>
Reviewed-by: Richard Henderson <r...@twiddle.net>
S
From: Richard Henderson <r...@twiddle.net>
Don't leave an unused bit after DELAY_SLOT_MASK.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id:
From: Richard Henderson <r...@twiddle.net>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-15-...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target
)
Queued target/sh4 patches
Aurelien Jarno (5):
target/sh4: do not check for PR bit for fabs instruction
target/sh4: fix FPU unorderered compare
target
From: Richard Henderson <r...@twiddle.net>
We can fold 3 different tests within the decode loop
into a more accurate computation of max_insns to start.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <2
From: Richard Henderson <r...@twiddle.net>
Compute which register bank to use once at the start of translation.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <20170718200255.31647-11-...@twiddle.net>
3-3-aurel...@aurel32.net>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/op_helper.c | 28
1 file changed, 8 insertions(+), 20 deletions(-)
diff --git a/target/sh4/op_helper.c b/targ
lied patches 2-27 to my tree. I
believe the patch 1 doesn't provide the correct (corner case) behaviour
in system mode. As for the last 3 patches, given they touch non-sh4
specific part of linux-user, I guess they should at least be acked by
a linux-user maintainer.
--
Aurelien Jarno
t; ---
> V2: Free constants loaded during the gUSA sequence.
> ---
> target/sh4/translate.c | 321
> +
> 1 file changed, 321 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
ur for other CPUs. For the user case it's
different, we don't have real choice, plus we know that it will be used
to execute linux binaries, which are more likely to have a sane usage of
atomic instructions.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
or should I just
pick your patches and apply the small fixes that are needed?
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2017-07-17 20:25, Richard Henderson wrote:
> On 07/17/2017 06:55 PM, Philippe Mathieu-Daudé wrote:
> > Aurelien Jarno denoted this function could be implemented more effectively
> > using
> > the aarch32 rev16() pattern.
> >[http://lists.nongnu.org/archive/html/
)
Queued target/mips patches
Aurelien Jarno (1):
target/mips: optimize WSBH, DSBH and DSHD
Pavel Dovgalyuk (1):
mips: set CP0 Debug DExcCode for SDBBP instruction
target/mips/helper.c| 2
;
Message-id: 20170502120350.3368.92338.stgit@PASHA-ISP
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/mips/helper.c | 2 ++
1 file changed, 2 insertions(+)
dif
Use the same mask to avoid having to load two different constants.
Suggested-by: Richard Henderson <r...@twiddle.net>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/mips/translate.c | 18 --
version 2.5 obsolete. Therefore I guess the
version 2 is the one to be used instead.
Unfortunately my knowledge of linux-user is rather limited to review
this new series.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
op_src = mv_src;
> +} else {
> +goto fail;
> +}
> + op_arg = REG(op_src);
> +break;
> +
> +case 0x6007: /* not Rm,Rn */
> +if (ld_dst != B7_4 || mv_src >= 0) {
> +goto fail;
> +}
> +op_dst = B11_8;
> +op_opc = INDEX_op_xor_i32;
> +op_arg = tcg_const_i32(-1);
This temp is never freed. Same for a few others below.
Overall, parsing the atomic sequence ends up being complex. I have
verified the most common sequences from GCC or GLIBC, and your code
seems fine for at least those cases.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2017-07-16 11:59, Richard Henderson wrote:
> On 07/16/2017 11:43 AM, Aurelien Jarno wrote:
> > Indeed, if the same atomic code is used often it might be better to have
> > it cached. That said it's only true for TB that are recognized, as IIRC
> > TB with the exclusiv
On 2017-07-16 01:22, Aurelien Jarno wrote:
> On 2017-07-06 16:20, Richard Henderson wrote:
> > As for other targets, cmpxchg isn't quite right for ll/sc,
> > suffering from an ABA race, but is sufficient to implement
> > portable atomic operations.
> >
> > Si
On 2017-07-16 09:35, Richard Henderson wrote:
> On 07/16/2017 05:18 AM, Aurelien Jarno wrote:
> > That said for further improvements did you consider decoding the gUSA
> > section in a helper. It might avoid having to emulate the atomic
> > sequence with 3 TBs in the worst c
On 2017-07-15 16:33, Richard Henderson wrote:
> On 07/15/2017 12:59 PM, Aurelien Jarno wrote:
> > On 2017-07-06 16:20, Richard Henderson wrote:
> > > If a signal is delivered during the execution of a delay slot,
> > > or a gUSA region, clear those b
On 2017-07-15 16:30, Richard Henderson wrote:
> On 07/15/2017 12:14 PM, Aurelien Jarno wrote:
> > On 2017-07-06 16:20, Richard Henderson wrote:
> > > For uniprocessors, SH4 uses optimistic restartable atomic sequences.
> > > Upon an interrupt, a real kernel would
hould just add the code to correctly clear LDST in case of interrupt
or exception.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
(int sig, struct target_sigaction *ka,
Why not using TB_FLAG_ENVFLAGS_MASK introduced earlier in this patch
series?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
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