On 4/24/24 08:23, Guenter Roeck wrote:
On 4/24/24 04:16, Gerd Hoffmann wrote:
qemu hack:
hw/usb/hcd-ohci.c | 11 +++
hw/usb/hcd-ohci.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index fc8fc91a1d..99e52ad13a 100644
--- a/hw/usb/hcd
On 4/24/24 04:16, Gerd Hoffmann wrote:
qemu hack:
hw/usb/hcd-ohci.c | 11 +++
hw/usb/hcd-ohci.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index fc8fc91a1d..99e52ad13a 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -267,6
On 4/23/24 19:11, Alan Stern wrote:
[ ... ]
To avoid the overhead of repeated interrupts, it would be best to check the
interrupt status at the end of the routine and restart if any of the
enabled bits are set, as in your first patch.
If you would like to clean it up (get rid of the debugging
Hi Alan,
On 4/23/24 10:30, Alan Stern wrote:
On Tue, Apr 23, 2024 at 10:04:17AM -0700, Guenter Roeck wrote:
Hi,
when testing usb-ohci
What is usb-ohci? Do you mean ohci-hcd?
with qemu's pci-ohci emulation, I keep getting
random usb interface timeouts. Sometimes the usb_hub_wq times out
Hi,
when testing usb-ohci with qemu's pci-ohci emulation, I keep getting
random usb interface timeouts. Sometimes the usb_hub_wq times out.
[9.555666] Waiting for root device /dev/sda...
[ 62.452625] INFO: task kworker/0:2:42 blocked for more than 30 seconds.
[ 62.453036] Tainted:
On Fri, Mar 08, 2024 at 03:41:48PM +, Peter Maydell wrote:
> On Tue, 13 Feb 2024 at 15:36, Guenter Roeck wrote:
> >
> > On Tue, Feb 13, 2024 at 03:14:21PM +, Peter Maydell wrote:
> > > On Mon, 12 Feb 2024 at 14:36, Guenter Roeck wrote:
> > > > O
On 2/17/24 01:06, Michael Tokarev wrote:
28.02.2023 20:11, Guenter Roeck wrote:
Host drivers do not necessarily set cdb_len in megasas io commands.
With commits 6d1511cea0 ("scsi: Reject commands if the CDB length
exceeds buf_len") and fe9d8927e2 ("scsi: Add buf_len parameter
solve the problem unconditionally.
Fixes: 931adff31478 ("target/hppa: Update cpu_hppa_get/put_psw for hppa64")
Cc: Richard Henderson
Cc: Charlie Jenkins
Cc: Helge Deller
Reviewed-by: Richard Henderson
Signed-off-by: Guenter Roeck
---
v2: Rework to not require conditional code [
On 2/15/24 22:16, Richard Henderson wrote:
On 2/15/24 19:34, Guenter Roeck wrote:
- env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
+ if (hppa_is_pa20(env)) {
+ env->psw = psw & ~(PSW_N | PSW_V | PSW_CB | 0xffull);
+ } else {
+ env->psw = psw
Cc: Helge Deller
Signed-off-by: Guenter Roeck
---
target/hppa/helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index 859644c47a..7b798d1227 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -76,7 +76,
On Tue, Feb 13, 2024 at 03:14:21PM +, Peter Maydell wrote:
> On Mon, 12 Feb 2024 at 14:36, Guenter Roeck wrote:
> > On 2/12/24 04:32, Peter Maydell wrote:
> > > The machines I have in mind are:
> > >
> > > PXA2xx machines:
> > >
> > > a
Hi,
On Tue, Feb 13, 2024 at 02:42:29PM +0100, Marcin Juszkiewicz wrote:
>
> > > The one SA1110 machine:
> > >
> > > collie Sharp SL-5500 (Collie) PDA (SA-1110)
> > >
> > I do test collie.
>
> Can you share kernel/initrd/config? I wanted to boot something at 20th
> anniversary of
[ sorry for the earlier noise; accidentally hit "send" ]
On 2/12/24 04:32, Peter Maydell wrote:
QEMU includes some models of old Arm machine types which are
a bit problematic for us because:
* they're written in a very old way that uses numerous APIs that we
would like to get away from
On 2/12/24 04:32, Peter Maydell wrote:
QEMU includes some models of old Arm machine types which are
a bit problematic for us because:
* they're written in a very old way that uses numerous APIs that we
would like to get away from (eg they don't use qdev, they use
Hi Helge,
On Thu, Feb 01, 2024 at 08:22:58PM -0800, Guenter Roeck wrote:
> Hi,
>
> On Sat, Jan 13, 2024 at 06:57:20AM +0100, del...@kernel.org wrote:
> > From: Helge Deller
> >
> > Recognize the qemu --nodefaults option, which will disable the
> >
On Fri, Feb 02, 2024 at 10:54:20AM +0100, Helge Deller wrote:
> Hi Guenter,
>
> On 2/2/24 05:22, Guenter Roeck wrote:
> > On Sat, Jan 13, 2024 at 06:57:20AM +0100, del...@kernel.org wrote:
> > > From: Helge Deller
> > >
> > > Recognize the qe
Hi,
On Sat, Jan 13, 2024 at 06:57:20AM +0100, del...@kernel.org wrote:
> From: Helge Deller
>
> Recognize the qemu --nodefaults option, which will disable the
> following default devices on hppa:
> - lsi53c895a SCSI controller,
> - artist graphics card,
> - LASI 82596 NIC,
> - tulip PCI NIC,
>
On Thu, Feb 01, 2024 at 02:58:40PM +, Peter Maydell wrote:
> On Mon, 29 Jan 2024 at 06:00, Guenter Roeck wrote:
> >
> > The latest version of qemu (v8.2.0-869-g7a1dc45af5) crashes when booting
> > the mcimx7d-sabre emulation with Linux v5.11 and later.
> >
>
xes: d64e5eabc4c7 ("pci: Add support for Designware IP block")
Cc: Andrey Smirnov
Cc: Nikita Ostrenkov
Signed-off-by: Guenter Roeck
---
hw/pci-host/designware.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index dd9e389c0
On Sat, Jan 27, 2024 at 11:11:58AM -0800, Guenter Roeck wrote:
> Hi,
>
> On Mon, Jan 08, 2024 at 02:03:25PM +, Nikita Ostrenkov wrote:
> > Signed-off-by: Nikita Ostrenkov
> > ---
>
> This patch, with the "sabrelite" emulation and the Lin
On Sat, Jan 27, 2024 at 11:11:58AM -0800, Guenter Roeck wrote:
> Hi,
>
> On Mon, Jan 08, 2024 at 02:03:25PM +, Nikita Ostrenkov wrote:
> > Signed-off-by: Nikita Ostrenkov
> > ---
>
> This patch, with the "sabrelite" emulation and the Lin
Hi,
On Mon, Jan 08, 2024 at 02:03:25PM +, Nikita Ostrenkov wrote:
> Signed-off-by: Nikita Ostrenkov
> ---
This patch, with the "sabrelite" emulation and the Linux upstream kernel
(v6.8-rc1, using imx_v6_v7_defconfig), results in:
qemu-system-arm: ../system/memory.c:2750:
On 1/20/24 05:09, Michael Tokarev wrote:
12.01.2024 16:15, Mark Cave-Ayland:
This series contains fixes for the esp-pci device (am53c974 or dc390) for a
few issues spotted whilst testing the previous ESP series.
Patches 1-3 are fixes for issues found by Helge/Guenter whilst testing the
hppa
The commit
reduced the DAP address range from 0x10 to 4kB, and the emulation
thus no longer covered the various unimplemented devices in the affected
address range.
Fixes: 0cd4926b85 ("Refactor i.MX6UL processor code")
Cc: Jean-Christophe Dubois
Signed-off-by: Guenter Roeck
---
Thi
On Fri, Jan 19, 2024 at 02:32:47PM -0800, Guenter Roeck wrote:
> Hi,
>
> On Fri, Oct 27, 2023 at 03:39:40PM +0100, Peter Maydell wrote:
> > From: Luc Michel
> >
> > Use the FIELD macro to describe the PHYMNTNC register fields.
> >
> > Signed-off-by: Lu
Hi,
On Fri, Oct 27, 2023 at 03:39:40PM +0100, Peter Maydell wrote:
> From: Luc Michel
>
> Use the FIELD macro to describe the PHYMNTNC register fields.
>
> Signed-off-by: Luc Michel
> Reviewed-by: sai.pavan.bo...@amd.com
> Message-id: 20231017194422.4124691-10-luc.mic...@amd.com
>
On 1/16/24 02:04, Philippe Mathieu-Daudé wrote:
Hi,
(Cc'ing Li, Strahinja and Niek)
On 15/1/24 19:27, Guenter Roeck wrote:
Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.
I'm confused by these registers from
-by: Guenter Roeck
---
v2: The USB Controllers are part of the chipset, so instantiate them
unconditionally
docs/system/arm/bananapi_m2u.rst | 2 +-
hw/arm/Kconfig | 2 ++
hw/arm/allwinner-r40.c | 47 ++--
include/hw/arm/allwinner-r40.h
Allwinner R40 supports an AHCI compliant SATA controller.
Add support for it.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 1 +
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 12 +++-
include/hw
Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 8
, by booting from ATA/SATA drive, and by manually
testing watchdog operation.
v2:
- The USB Controllers are part of the chipset, so instantiate them
unconditionally
- Add Reviewed-by: tag to patch 2/3
Guenter Roeck (3):
hw/arm: Add
On Mon, Jan 15, 2024 at 05:56:14PM +0100, Philippe Mathieu-Daudé wrote:
> The USB Controllers are part of the chipset, thus are
> always present and mapped in memory.
>
> Reported-by: Guenter Roeck
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Guenter Roeck
Tested-by: Guenter Roeck
On 1/15/24 08:30, Philippe Mathieu-Daudé wrote:
On 15/1/24 17:12, Guenter Roeck wrote:
On 1/15/24 03:02, Philippe Mathieu-Daudé wrote:
Hi,
On 13/1/24 20:16, Guenter Roeck wrote:
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host
On 1/15/24 03:02, Philippe Mathieu-Daudé wrote:
Hi,
On 13/1/24 20:16, Guenter Roeck wrote:
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machine USB support is not enabled, create
Allwinner R40 supports an AHCI compliant SATA controller.
Add support for it.
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 1 +
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 12 +++-
include/hw/arm/allwinner-r40.h | 3 +++
4 files
Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.
Signed-off-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/allwinner-r40.c | 8
-by: Guenter Roeck
---
docs/system/arm/bananapi_m2u.rst | 2 +-
hw/arm/Kconfig | 2 +
hw/arm/allwinner-r40.c | 70 +++-
include/hw/arm/allwinner-r40.h | 9
4 files changed, 80 insertions(+), 3 deletions(-)
diff --git a/docs/system
, by booting from ATA/SATA drive, and by manually
testing watchdog operation.
Guenter Roeck (3):
hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi
t;Spurious irq, sreg=10" errors.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Guenter Roeck
Tested-by: Guenter Roeck
> ---
> hw/scsi/esp-pci.c | 28 +---
> 1 file changed, 13 insertions(+), 15 deletions(-)
>
> diff --git a/hw/scsi/esp-pci.c b/hw
issue with the DC390 DOS driver which issues the BLAST command
> as
> part of its normal error recovery routine at startup, and otherwise sits in a
> tight loop waiting for DMA_STAT_BCMBLT to be set before continuing.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Gue
INTE_D
> isn't set in the DMA_CMD register.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Guenter Roeck
Tested-by: Guenter Roeck
> ---
> hw/scsi/esp-pci.c | 32 +++-
> 1 file changed, 27 insertions(+), 5 deletions(-)
>
> diff --git a
ding the
> data transferred to the guest.
>
> Fix esp_pci_dma_memory_rw() to use the DMA_WAC (Working Address Counter) for
> the DMA address which is correctly incremented across multiple SCSI layer
> transfers.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Guenter Roeck
Teste
On 12/13/23 09:19, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 13/12/23 18:12, Peter Maydell wrote:
On Wed, 13 Dec 2023 at 01:49, Guenter Roeck wrote:
All tests using pxa2xx_mmc to access mmc cards on pxa2xx platforms
such as borzoi fail starting with commit a2e1753b80 ("memory: pr
On 12/13/23 09:12, Peter Maydell wrote:
On Wed, 13 Dec 2023 at 01:49, Guenter Roeck wrote:
All tests using pxa2xx_mmc to access mmc cards on pxa2xx platforms
such as borzoi fail starting with commit a2e1753b80 ("memory: prevent
dma-reentracy issues"). Disable reentrancy gu
Hi,
On Tue, Aug 02, 2022 at 07:32:41PM -0700, Iris Chen wrote:
> From: Iris Chen
>
> Signed-off-by: Iris Chen
> ---
Are there any plans to submit a new version of this patch ?
Thanks,
Guenter
> configs/devices/arm-softmmu/default.mak | 1 +
> hw/arm/Kconfig | 5
All tests using pxa2xx_mmc to access mmc cards on pxa2xx platforms
such as borzoi fail starting with commit a2e1753b80 ("memory: prevent
dma-reentracy issues"). Disable reentrancy guard to fix the problem.
Fixes: a2e1753b80 ("memory: prevent dma-reentracy issues")
Signed-o
On 8/1/23 09:01, Peter Maydell wrote:
On Sat, 24 Jun 2023 at 16:02, Guenter Roeck wrote:
On 6/24/23 07:23, Guenter Roeck wrote:
On 6/24/23 03:40, Peter Maydell wrote:
On Fri, 23 Jun 2023 at 20:33, Guenter Roeck wrote:
On 6/23/23 10:44, Peter Maydell wrote:
On Sat, 17 Jun 2023 at 17:29
On 7/24/23 00:18, Bernhard Beschow wrote:
Am 16. Juli 2023 19:53:37 UTC schrieb Bernhard Beschow :
Am 10. Juli 2023 16:01:46 UTC schrieb Bernhard Beschow :
Am 10. Juli 2023 10:16:35 UTC schrieb "Philippe Mathieu-Daudé"
:
On 9/7/23 10:09, Bernhard Beschow wrote:
Since commit
On Mon, Jul 10, 2023 at 12:16:35PM +0200, Philippe Mathieu-Daudé wrote:
> On 9/7/23 10:09, Bernhard Beschow wrote:
> > Since commit c0a55a0c9da2 "hw/sd/sdhci: Support big endian SD host
> > controller
> > interfaces" sdhci_common_realize() forces all SD card controllers to use
> > either
> >
ndian and switch to big
endian in sdhci_common_realize() only if there is a matchig big endian variant
available.
Fixes: c0a55a0c9da2 ("hw/sd/sdhci: Support big endian SD host controller
interfaces")
Signed-off-by: Bernhard Beschow
Tested-by: Guenter Roeck
---
hw/sd/sdhci.c | 8 +
Barboza
Cc: Alistair Francis
Cc: Daniel Henrique Barboza
Fixes: 325b7c4e75 hw/riscv: Enable TPM backends
Signed-off-by: Guenter Roeck
---
v2: Handle devicetree (load & create) entirely in machine_done function.
hw/riscv/virt.c | 22 +++---
1 file changed, 11 insertions(+)
On 7/3/23 12:25, Daniel Henrique Barboza wrote:
On 7/3/23 00:46, Guenter Roeck wrote:
If the devicetree is created before machine initialization is complete,
it misses dynamic devices. Specifically, the tpm device is not added
to the devicetree file and is therefore not instantiated in Linux
On 7/3/23 00:46, Philippe Mathieu-Daudé wrote:
On 3/7/23 05:46, Guenter Roeck wrote:
If the devicetree is created before machine initialization is complete,
it misses dynamic devices. Specifically, the tpm device is not added
to the devicetree file and is therefore not instantiated in Linux
Fixes: 325b7c4e75 hw/riscv: Enable TPM backends
Signed-off-by: Guenter Roeck
---
hw/riscv/virt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ed4c27487e..08876284f5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1248,6
On 6/24/23 07:23, Guenter Roeck wrote:
On 6/24/23 03:40, Peter Maydell wrote:
On Fri, 23 Jun 2023 at 20:33, Guenter Roeck wrote:
On 6/23/23 10:44, Peter Maydell wrote:
On Sat, 17 Jun 2023 at 17:29, Guenter Roeck wrote:
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com
On 6/24/23 03:40, Peter Maydell wrote:
On Fri, 23 Jun 2023 at 20:33, Guenter Roeck wrote:
On 6/23/23 10:44, Peter Maydell wrote:
On Sat, 17 Jun 2023 at 17:29, Guenter Roeck wrote:
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
From: qianfan Zhao
Allwinner
On 6/23/23 10:44, Peter Maydell wrote:
On Sat, 17 Jun 2023 at 17:29, Guenter Roeck wrote:
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's
On Sun, Jun 18, 2023 at 08:40:28AM +0800, qianfan wrote:
>
> 在 2023/6/18 0:29, Guenter Roeck 写道:
> > Hi,
> >
> > On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
> > > From: qianfan Zhao
> > >
> > > Allwinner R40
On Mon, Jun 19, 2023 at 01:32:34PM -0700, Guenter Roeck wrote:
> Hi Alistair,
>
> On Wed, Apr 20, 2022 at 03:52:48PM +1000, Alistair Francis wrote:
> > From: Alistair Francis
> >
> > Imply the TPM sysbus devices. This allows users to add TPM devices t
Hi Alistair,
On Wed, Apr 20, 2022 at 03:52:48PM +1000, Alistair Francis wrote:
> From: Alistair Francis
>
> Imply the TPM sysbus devices. This allows users to add TPM devices to
> the RISC-V virt board.
>
> This was tested by first creating an emulated TPM device:
>
> swtpm socket --tpm2
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
> From: qianfan Zhao
>
> Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
> for In-Car Entertainment usage, A40i and A40pro are
0 convention, which happens to work with the interrupt
> controller it is wired up to.
>
> Coerce the value to boolean to follow our usual convention.
>
> Signed-off-by: Peter Maydell
Tested-by: Guenter Roeck
> ---
> hw/sd/allwinner-sdhost.c | 2 +-
> 1 file changed, 1 i
: qemu-sta...@nongnu.org
> Signed-off-by: Peter Maydell
Tested-by: Guenter Roeck
Tested on top of 8.0.2, both this patch alone as well as this
patch plus the second patch in the series.
Guenter
> ---
> hw/intc/allwinner-a10-pic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On 6/5/23 02:40, Peter Maydell wrote:
On Sat, 3 Jun 2023 at 19:06, Guenter Roeck wrote:
On 6/3/23 10:46, Michael Tokarev wrote:
03.06.2023 18:03, Guenter Roeck wrote:
Hi,
On Tue, May 02, 2023 at 01:14:55PM +0100, Peter Maydell wrote:
The Allwinner PIC model uses set_bit() and clear_bit
On 6/3/23 10:46, Michael Tokarev wrote:
03.06.2023 18:03, Guenter Roeck wrote:
Hi,
On Tue, May 02, 2023 at 01:14:55PM +0100, Peter Maydell wrote:
The Allwinner PIC model uses set_bit() and clear_bit() to update the
values in its irq_pending[] array when an interrupt arrives. However
Hi,
On Tue, May 02, 2023 at 01:14:55PM +0100, Peter Maydell wrote:
> The Allwinner PIC model uses set_bit() and clear_bit() to update the
> values in its irq_pending[] array when an interrupt arrives. However
> it is using these functions wrongly: they work on an array of type
> 'long', and it
On Sat, Apr 29, 2023 at 01:46:26PM -0700, Guenter Roeck wrote:
> Hi,
>
> On Tue, Nov 01, 2022 at 11:29:33PM +0100, Philippe Mathieu-Daudé wrote:
> > Some SDHCI IP can be synthetized in various endianness:
> > https://github.com/u-boot/u-boot/blob/v2021.04
Hi,
On Tue, Nov 01, 2022 at 11:29:33PM +0100, Philippe Mathieu-Daudé wrote:
> Some SDHCI IP can be synthetized in various endianness:
> https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc
>
> - CONFIG_SYS_FSL_ESDHC_BE
>
>ESDHC IP is in big-endian mode. Accessing ESDHC
On 4/18/23 08:32, Peter Maydell wrote:
On Tue, 18 Apr 2023 at 16:18, Guenter Roeck wrote:
On 4/18/23 07:46, Peter Maydell wrote:
I guess I don't understand what the topology is for these specific
SoCs, then. If there's only one master that might be connected
to multiple PHYs, why does one
On 4/18/23 07:46, Peter Maydell wrote:
On Tue, 18 Apr 2023 at 15:42, Guenter Roeck wrote:
On 4/18/23 05:10, Peter Maydell wrote:
On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
So I was having a look at this to see if it was reasonably easy to
split out the PHY into its own device object
On 4/18/23 05:10, Peter Maydell wrote:
On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
be connected to separate MDIO busses, or both may be connected on the same
MDIO bus using different PHY addresses. Commit
On Thu, Mar 30, 2023 at 05:31:13PM +0100, Peter Maydell wrote:
> On Wed, 15 Mar 2023 at 14:52, Guenter Roeck wrote:
> >
> > The SOC on i.MX6UL and i.MX7 has 2 Ethernet interfaces. The PHY on each may
> > be connected to separate MDIO busses, or both may be connected on the sa
or
read-only registers.
Reported-by: Qiang Liu
Link: https://gitlab.com/qemu-project/qemu/-/issues/1408
Fixes: 0701a5efa015 ("hw/usb: Add basic i.MX USB Phy support")
Signed-off-by: Guenter Roeck
---
hw/usb/imx-usb-phy.c | 19 +--
1 file changed, 17 insertions(+), 2
On Thu, Mar 16, 2023 at 02:51:23PM +, Peter Maydell wrote:
> On Thu, 16 Mar 2023 at 14:12, Guenter Roeck wrote:
> >
> > Hi Peter,
> >
> > On 3/16/23 06:41, Peter Maydell wrote:
> > > On Fri, 13 Mar 2020 at 01:45, Guenter Roeck wrote:
> > >>
Hi Peter,
On 3/16/23 06:41, Peter Maydell wrote:
On Fri, 13 Mar 2020 at 01:45, Guenter Roeck wrote:
Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6,
and i.MX7 SoCs.
The only support really needed - at least to boot Linux - is support
for soft reset, which needs to reset
y-consumer.
Signed-off-by: Guenter Roeck
---
hw/net/imx_fec.c | 27 +++
include/hw/net/imx_fec.h | 2 ++
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index c862d96593..5d1f1f104c 100644
--- a/hw/net/imx_fec.c
++
On mcimx6ul-evk, the MDIO bus is connected to the second Ethernet
interface. Set fec1-phy-connected to false to reflect this.
Signed-off-by: Guenter Roeck
---
hw/arm/mcimx6ul-evk.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index
Add fec[12]-phy-connected properties and use it to set phy-connected
and phy-consumer properties for imx_fec.
Signed-off-by: Guenter Roeck
---
hw/arm/fsl-imx6ul.c | 20
include/hw/arm/fsl-imx6ul.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/arm/fsl
functional.
--------
Guenter Roeck (5):
hw/net/imx_fec: Support two Ethernet interfaces connected to single MDIO
bus
fsl-imx6ul: Add fec[12]-phy-connected properties
arm/mcimx6ul-evk: Set fec1-phy-connected property to false
fsl-imx7: Add fec[12]-phy-connected properties
arm/mci
On mcimx7d-sabre, the MDIO bus is connected to the first Ethernet
interface. Set fec2-phy-connected to false to reflect this.
Signed-off-by: Guenter Roeck
---
hw/arm/mcimx7d-sabre.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index
Add fec[12]-phy-connected properties and use it to set phy-connected
and phy-consumer properties for imx_fec.
Signed-off-by: Guenter Roeck
---
hw/arm/fsl-imx7.c | 20
include/hw/arm/fsl-imx7.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/arm/fsl-imx7.c
On 3/3/23 01:02, Fiona Ebner wrote:
Am 28.02.23 um 18:11 schrieb Guenter Roeck:
Host drivers do not necessarily set cdb_len in megasas io commands.
With commits 6d1511cea0 ("scsi: Reject commands if the CDB length
exceeds buf_len") and fe9d8927e2 ("scsi: Add buf_len parameter
ives because cdb_len is set to 0 by the host driver.
Set the cdb length to its actual size to solve the problem.
Signed-off-by: Guenter Roeck
---
hw/scsi/megasas.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 9c
On 1/31/23 23:49, Cédric Le Goater wrote:
On 2/1/23 06:39, Joel Stanley wrote:
On Thu, 19 Jan 2023 at 12:36, Cédric Le Goater wrote:
From: Guenter Roeck
supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
the Supermicro documentation for X11 BMCs, and it does not match
On 1/19/23 00:02, Klaus Jensen wrote:
On Jan 19 08:28, Klaus Jensen wrote:
On Jan 18 21:03, Keith Busch wrote:
On Thu, Jan 19, 2023 at 01:10:57PM +1000, Alistair Francis wrote:
On Thu, Jan 19, 2023 at 12:44 PM Keith Busch wrote:
Further up, it says the "interrupt gateway" is responsible
On Tue, Jan 17, 2023 at 04:18:14PM +, Peter Maydell wrote:
> On Tue, 17 Jan 2023 at 16:10, Guenter Roeck wrote:
> >
> > On Mon, Jan 16, 2023 at 09:58:13PM -0700, Keith Busch wrote:
> > > On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
> > > >
On Mon, Jan 16, 2023 at 09:58:13PM -0700, Keith Busch wrote:
> On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
> > I noticed that the Linux driver does not use the INTMS/INTMC registers
> > to mask interrupts on the controller while processing CQEs. While not
> > required by the
On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
[ ... ]
>
> I noticed that the Linux driver does not use the INTMS/INTMC registers
> to mask interrupts on the controller while processing CQEs. While not
> required by the spec, it is *recommended* in setups not using MSI-X to
>
On 1/12/23 11:27, Keith Busch wrote:
On Thu, Jan 12, 2023 at 06:45:55PM +0100, Klaus Jensen wrote:
On Jan 12 09:34, Keith Busch wrote:
On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
The pin-based interrupt logic in hw/nvme seems sound enough to me, so I
am wondering if there
On 1/12/23 09:45, Klaus Jensen wrote:
On Jan 12 09:34, Keith Busch wrote:
On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
The pin-based interrupt logic in hw/nvme seems sound enough to me, so I
am wondering if there is something going on with the kernel driver (but
I certainly
On 1/12/23 09:45, Klaus Jensen wrote:
On Jan 12 09:34, Keith Busch wrote:
On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
The pin-based interrupt logic in hw/nvme seems sound enough to me, so I
am wondering if there is something going on with the kernel driver (but
I certainly
On 1/12/23 05:10, Klaus Jensen wrote:
Hi all (linux-nvme, qemu-devel, maintainers),
On QEMU riscv64, which does not use MSI/MSI-X and thus relies on
pin-based interrupts, I'm seeing occasional completion timeouts, i.e.
nvme nvme0: I/O 333 QID 1 timeout, completion polled
To rule out issues
On Mon, Jan 02, 2023 at 06:42:03PM +0100, Michael Walle wrote:
> Am 2023-01-02 17:23, schrieb Guenter Roeck:
> > On Mon, Jan 02, 2023 at 04:43:49PM +0100, Michael Walle wrote:
> > > Am 2023-01-02 14:53, schrieb Cédric Le Goater:
> > > > On 12/27
2022 at 06:36:02PM +0100, Cédric Le Goater wrote:
> > > > > On 12/21/22 13:22, Guenter Roeck wrote:
> > > > > > Generated from hardware using the following command and
> > > > > > then padding
> > > > > > with 0xff to fill out a p
Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
Cc: Michael Walle
Cc: Tudor Ambarus
Signed-off-by: Guenter Roeck
---
hw/block/m25p80.c | 3 ++-
hw/block/m25p80_sfdp.c | 40
On Mon, Dec 12, 2022 at 08:30:42AM -0600, Richard Henderson wrote:
> On 12/11/22 19:13, Guenter Roeck wrote:
> > On Sat, Dec 10, 2022 at 07:27:46AM -0800, Guenter Roeck wrote:
> > > Hi,
> > >
> > > On Thu, Sep 01, 2022 at 11:15:09AM +0100, Richard Henderson
On 12/12/22 06:30, Richard Henderson wrote:
On 12/11/22 19:13, Guenter Roeck wrote:
On Sat, Dec 10, 2022 at 07:27:46AM -0800, Guenter Roeck wrote:
Hi,
On Thu, Sep 01, 2022 at 11:15:09AM +0100, Richard Henderson wrote:
The value previously chosen overlaps GUSA_MASK.
Rename all DELAY_SLOT_
On 12/12/22 05:45, Klaus Jensen wrote:
On Dec 12 05:39, Guenter Roeck wrote:
On 12/12/22 01:58, Klaus Jensen wrote:
On Dec 8 12:39, Guenter Roeck wrote:
On Thu, Dec 08, 2022 at 12:13:55PM -0800, Guenter Roeck wrote:
On Thu, Dec 08, 2022 at 10:47:42AM -0800, Guenter Roeck wrote:
A cq head
On 12/12/22 01:58, Klaus Jensen wrote:
On Dec 8 12:39, Guenter Roeck wrote:
On Thu, Dec 08, 2022 at 12:13:55PM -0800, Guenter Roeck wrote:
On Thu, Dec 08, 2022 at 10:47:42AM -0800, Guenter Roeck wrote:
A cq head doorbell mmio is skipped... And it is not the fault of the
kernel. The kernel
On Sat, Dec 10, 2022 at 07:27:46AM -0800, Guenter Roeck wrote:
> Hi,
>
> On Thu, Sep 01, 2022 at 11:15:09AM +0100, Richard Henderson wrote:
> > The value previously chosen overlaps GUSA_MASK.
> >
> > Rename all DELAY_SLOT_* and GUSA_* defines to emphasize
> > t
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