tests/qtest/machine-none-test.c | 2 +-
target/mips/cpu-defs.c.inc | 40 --
12 files changed, 12 insertions(+), 219 deletions(-)
--
---
Jiaxun Yang
x86-only roms.
FYI on some systems they use x86emu (or biosemu) to run x86 only
OpROMs, this is at least true for u-boot (u-boot/drivers/bios_emulator),
PMON (MIPS/Loongson) and coreboot.
Thanks
- Jiaxun
Thanks,
/mjt
--
---
Jiaxun Yang
在 2023/6/30 15:28, Marcin Nowakowski 写道:
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
so indicate that properly in CP0.Config5 register bits [16:15].
Signed-off-by: Marcin Nowakowski
VZ is unimplemented in TCG so perhaps we should leave them as not supported?
> 2023年6月3日 01:28，Peter Maydell 写道：
>
> On Sun, 21 May 2023 at 11:24, Jiaxun Yang wrote:
>>
>> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
>> Loongson 3A5000's IPI implementation have 4 mailboxes per
>> core.
>>
>> H
> 2023年5月23日 11:01，Song Gao 写道：
>
>
>
> 在 2023/5/23 上午11:22, Jiaxun Yang 写道:
[...]
>>
>>>
>> Is totally the same on MIPS and LoongArch. I’m guarding them out because
>> We have different way to get IOCSR address space on MIPS, which is due
> 2023年5月23日 02:25，Song Gao 写道：
>
>
>
> 在 2023/5/22 下午9:44, Philippe Mathieu-Daudé 写道:
>> On 22/5/23 13:47, Jiaxun Yang wrote:
>>>
>>>
>>>> 2023年5月22日 04:52，Huacai Chen 写道：
>>>>
>>>> Hi, Jiaxun,
>
> 2023年5月22日 13:08，Philippe Mathieu-Daudé 写道：
>
> On 21/5/23 23:48, Jiaxun Yang wrote:
>> After implemented CPUCFG and CSR, we are now able to boot Linux
>> kernel with Loongson-3A4000 CPU, so there is no point to restrict
>> CPU type for TCG.
>
> Resolves
ong_ipi to reflect the nature that it’s shared
by MIPS based Loongson and LoongArch based Loongson?
Thanks
- Jiaxun
>
>
> Huacai
>
> On Sun, May 21, 2023 at 6:24 PM Jiaxun Yang wrote:
>>
>> As per "Loongson 3A5000/3B5000 Processor Reference Manual",
>> Loon
/20230521102307.87081-1-jiaxun.y...@flygoat.com/T/#t
[2]:
https://lore.kernel.org/qemu-devel/0bb0cded-8450-536e-b90f-1a9d33311...@linaro.org/T/#t
Jiaxun Yang (2):
target/mips: Implement Loongson CSR instructions
hw/mips/loongson3_virt: Remove CPU restrictions for TCG
hw/mips/loongson3_virt.c
After implemented CPUCFG and CSR, we are now able to boot Linux
kernel with Loongson-3A4000 CPU, so there is no point to restrict
CPU type for TCG.
Signed-off-by: Jiaxun Yang
---
hw/mips/loongson3_virt.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mips
-by: Jiaxun Yang
---
target/mips/cpu-defs.c.inc | 9
target/mips/cpu.c| 8
target/mips/cpu.h| 40
target/mips/helper.h | 4 ++
target/mips/internal.h | 2 +
target/mips/tcg/lcsr.decode
workaround the situation that in such handler flow:
count = read_c0_count()
write_c0_compare(count)
If timer had not progressed when compare was written, the
interrupt would trigger again.
Signed-off-by: Jiaxun Yang
---
This seems fixed MTTCG booting issue on malta 5kEc with SMP.
I'm going to do more
Test loongson3-virt machine againt debian kernel and cpio rootfs.
Signed-off-by: Jiaxun Yang
---
tests/avocado/boot_linux_console.py | 46 +
1 file changed, 46 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
IOCSR based send features are tied to LoongArch's CPU implmentation,
ifdef them for LoongArch only so we can build loongarch_ipi on MIPS.
Note that Loongson-3A4000 have IOCSR as well, so we may implement
those features for MIPS in future.
Signed-off-by: Jiaxun Yang
---
hw/intc/loongarch_ipi.c
Hi all,
This series wires up loongarch_ipi device for loongson3-virt,
which is required for SMP support.
We also add a new test for loongson3-virt for acceptance harness.
Thanks
- Jiaxun
Jiaxun Yang (4):
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
hw/intc/loongarch_ipi: Guard
Wire up loongarch_ipi device for loongson3_virt machine, so we
can have SMP support for TCG backend as well.
Signed-off-by: Jiaxun Yang
---
hw/mips/Kconfig | 1 +
hw/mips/loongson3_bootp.c | 2 --
hw/mips/loongson3_bootp.h | 3 +++
hw/mips/loongson3_virt.c | 20
hardware.
It won't affect LoongArch based system as LoongArch boot code
only uses the first mailbox, however MIPS based Loongson boot
code uses all 4 mailboxes.
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
Signed-off-by: Jiaxun Yang
---
hw/intc/loongarch_ipi.c
> 2023年5月3日 10:12，Alex Bennée 写道：
>
> As the cached assets have fallen out of our cache new attempts to
> fetch these binaries fail hard due to certificate expirty. It's hard
> to find a contact email for the domain as the root page of mipsdistros
> throws up some random XML. I suspect Amazon
on
> in linux/arch/mips/kernel/elf.c).
>
> Signed-off-by: Daniil Kovalev
Reviewed-by: Jiaxun Yang
Thanks!
> ---
> linux-user/mips/cpu_loop.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_lo
> 2023年3月15日 08:18，Philippe Mathieu-Daudé 写道：
>
> On 11/3/23 13:39, Jiaxun Yang wrote:
>>> 2023年3月9日 12:32，Philippe Mathieu-Daudé 写道：
>>>
>>> Hi Jiaxun,
>>>
>>> On 11/2/23 18:34, Jiaxun Yang wrote:
>>>> Previously switch
> 2023年3月9日 12:32，Philippe Mathieu-Daudé 写道：
>
> Hi Jiaxun,
>
> On 11/2/23 18:34, Jiaxun Yang wrote:
>> Previously switchable NaN2008 requires fcsr31.nan2008 to be writable
>> for guest. However as per MIPS arch spec this bit can never be writable.
>> This
> 2023年3月7日 21:07，Philippe Mathieu-Daudé 写道：
>
> On 7/3/23 21:14, Philippe Mathieu-Daudé wrote:
>> On 7/3/23 21:07, Jiaxun Yang wrote:
>>>
>>>
>>>> 2023年3月7日 15:01，Philippe Mathieu-Daudé 写道：
>>>>
>>>> On 4/3/23 23:38, J
> 2023年3月7日 20:10，Philippe Mathieu-Daudé 写道：
>
> On 4/3/23 23:38, Jiaxun Yang wrote:
>> MIPS virt board is design to utilize existing VirtIO infrastures
>> but also comptitable with MIPS's existing internal simulation tools.
>> It includes virtio-pci, virtio-mmio, p
> 2023年3月7日 15:01，Philippe Mathieu-Daudé 写道：
>
> On 4/3/23 23:38, Jiaxun Yang wrote:
>> Hi there,
>> This patchset is to add a new machine type for MIPS architecture, which
>> is purely a VirtIO machine.
>
>> Jiaxun Yang (2):
>> hw/misc: Add MIPS
Generic MIPS
kernel.
Kernel patch available at:
https://lore.kernel.org/linux-mips/20230304221524.47160-1-jiaxun.y...@flygoat.com/
Thanks
Jiaxun Yang (2):
hw/misc: Add MIPS Trickbox device
hw/mips: Add MIPS virt board
MAINTAINERS | 7 +
configs/devices/mips-softmmu
.
Signed-off-by: Jiaxun Yang
---
v1:
- Rename to virt board
- Convert BIOS flash to ROM
- Cleanups
v2:
- Fix fdt flash
- Remove UP variant
---
MAINTAINERS | 7 +
configs/devices/mips-softmmu/common.mak | 1 +
docs/system/target-mips.rst | 22 +
hw/mips
-by: Jiaxun Yang
---
v1: Rewording commit message
---
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/mips_trickbox.c | 97 +
hw/misc/trace-events| 4 ++
include/hw/misc/mips_trickbox.h | 41
> 2023年3月4日 18:18，Richard Henderson 写道：
>
> Translators are no longer required to free tcg temporaries.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Jiaxun Yang
Thanks.
> ---
> 2.34.1
>
ci: Endian-swap using PCI_HOST_BRIDGE
MemoryRegionOps")
Signed-off-by: Jiaxun Yang
---
hw/pci-host/gt64120.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c
index f226d0342039..82c15edb4698 100644
--- a/hw/pci-
Ping?
> 2023年2月6日 01:08，Jiaxun Yang 写道：
>
>
>
>> 2023年2月5日 11:48，Philippe Mathieu-Daudé 写道：
>>
>> Hi Jiaxun,
>>
>> On 2/2/23 14:21, Jiaxun Yang wrote:
>>> MIPS virt board is design to utilize existing VirtIO infrastures
>>> b
Ping？
> 2023年2月11日 17:34，Jiaxun Yang 写道：
>
> Previously switchable NaN2008 requires fcsr31.nan2008 to be writable
> for guest. However as per MIPS arch spec this bit can never be writable.
> This cause NaN2008 ELF to be rejected by QEMU.
>
> NaN2008 can be enabled on R
在2023年2月17日二月 下午6:57，Thomas Huth写道：
> On 17/02/2023 18.43, Philippe Mathieu-Daudé wrote:
>> (Cc'ing Huacai & Jiaxun).
>>
>> On 17/2/23 17:38, Paolo Bonzini wrote:
>>> On 2/17/23 11:47, Daniel P. Berrangé wrote:
On Fri, Feb 17, 2023 at 11:36:41AM +0100, Markus Armbruster wrote:
> I
在2023年2月15日二月 下午8:50，Philippe Mathieu-Daudé写道：
> On 15/2/23 21:21, Richard Henderson wrote:
>> On 2/14/23 22:47, Marcin Nowakowski wrote:
>>> @@ -4860,6 +4860,7 @@ static void gen_compute_branch(DisasContext
>>> *ctx, uint32_t opc,
>>> target_ulong btgt = -1;
>>> int blink = 0;
>>>
s->itu.saar = >CP0_SAAR;
> }
>
> In order to avoid that, pass the MIPS_CPU object via a QOM
> link property, and set the 'saar' pointer in mips_itu_realize().
>
> Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Jiaxun Yang
Reviewed-by: Jiaxun Yang
Previously switchable NaN2008 requires fcsr31.nan2008 to be writable
for guest. However as per MIPS arch spec this bit can never be writable.
This cause NaN2008 ELF to be rejected by QEMU.
NaN2008 can be enabled on R2~R5 processors, just make it available
unconditionally.
Signed-off-by: Jiaxun
> 2023年2月5日 11:48，Philippe Mathieu-Daudé 写道：
>
> Hi Jiaxun,
>
> On 2/2/23 14:21, Jiaxun Yang wrote:
>> MIPS virt board is design to utilize existing VirtIO infrastures
>> but also comptitable with MIPS's existing internal simulation tools.
>> It includes
This board had been deprecated long ago.
Signed-off-by: Jiaxun Yang
---
docs/system/target-mips.rst | 14 --
1 file changed, 14 deletions(-)
diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst
index 138441bdec..83239fb9df 100644
--- a/docs/system/target-mips.rst
with any MIPS CPU cores.
Signed-off-by: Jiaxun Yang
---
v1:
- Rename to virt board
- Convert BIOS flash to ROM
- Cleanups
---
MAINTAINERS |7 +
configs/devices/mips-softmmu/common.mak |1 +
docs/system/target-mips.rst | 24 +
hw/mips/Kconfig
-by: Jiaxun Yang
---
v1: Rewording commit message
---
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/mips_trickbox.c | 97 +
hw/misc/trace-events| 4 ++
include/hw/misc/mips_trickbox.h | 41
Generic MIPS
kernel.
For testing purpose I've built little endian kernel[1] to work with this
machine with R4X00, loongson2f, octeon, mips32r2, mips64r2 and mips64r6.
TODO:
- Documentation
- Test against big endian kernel
- nanoMIPS options
Thanks
Jiaxun Yang (3):
docs/system: Remove "mips&q
> 2022年12月10日 15:55，Philippe Mathieu-Daudé 写道：
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/mips/bootloader.c | 25 -
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index cc3df385df..541b59bf84
> 2022年12月10日 16:01，Philippe Mathieu-Daudé 写道：
>
> On 10/12/22 16:54, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> hw/mips/bootloader.c | 29 ++---
>> 1 file changed, 26 insertions(+), 3 deletions(-)
>> diff --git
be 30, on N64 ABI build it should be 48 and 32 for N32 or O32 build.
It is defined in target/mips/cpu-param.h .
Thanks.
>
> On Thu, Dec 8, 2022 at 4:55 PM Jiaxun Yang wrote:
>
> Hi,
>
> This address range is located in KSEG3… Doesn’t seems to be a good location
> for u
Hi,
This address range is located in KSEG3… Doesn’t seems to be a good location
for userspace program.
I think you have two options to make target_mmap work, the first would be rising
TARGET_VIRT_ADDR_SPACE_BITS to 64 bit. That may break some user space
applications storing pointer tags on
> 2022年11月25日 13:25，Philippe Mathieu-Daudé 写道：
>
> On 24/11/22 22:29, Jiaxun Yang wrote:
>> MIPS VirtIO board is design to utilize existing VirtIO infrastures
>> but also comptitable with MIPS's existing internal simulation tools.
>> It includes virtio-mmio, p
with any MIPS CPU cores.
Signed-off-by: Jiaxun Yang
---
configs/devices/mips-softmmu/common.mak |1 +
hw/mips/Kconfig | 18 +
hw/mips/meson.build |1 +
hw/mips/virt.c | 1039 +++
4 files changed
/tree/main/kernel
Jiaxun Yang (3):
hw/intc: Add missing include for goldfish_pic.h
hw/misc: Add MIPS Trickbox device
hw/mips: Add MIPS VirtIO board
configs/devices/mips-softmmu/common.mak |1 +
hw/mips/Kconfig | 18 +
hw/mips/meson.build |1
hw/sysbus.h is missed in goldfish_pic.h.
Signed-off-by: Jiaxun Yang
---
include/hw/intc/goldfish_pic.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/hw/intc/goldfish_pic.h b/include/hw/intc/goldfish_pic.h
index e9d552f796..3e79580367 100644
--- a/include/hw/intc/goldfish_pic.h
MIPS Trickbox is a emulated device present in MIPS's proprietary
simulators for decadeds. It's capable for managing simulator status,
signaling interrupts, doing DMA and EJTAG stimulations.
For now we just borrow this device and implement power management
related functions.
Signed-off-by: Jiaxun
> 2022年11月22日 12:37，BALATON Zoltan 写道：
>
> Hello,
>
> On Mon, 21 Nov 2022, Bernhard Beschow wrote:
>> Am 21. November 2022 22:43:50 UTC schrieb "Philippe Mathieu-Daudé"
>> :
>>> On 21/11/22 16:34, Bernhard Beschow wrote:
Am 27. Oktober 2022 20:47:19 UTC schrieb "Philippe Mathieu-Daudé"
> 2022年11月14日 16:25，Jiaxun Yang 写道：
>
> Value of C0_CMGCRBase will be reseted to default when cpu reset
> happens. In some cases software may move GCR base and then initiate
> a CPU reset, this will leave C0_CMGCRBase of reseted core incorrect.
>
> Implement a cal
to be overriden after CPU reset.
Signed-off-by: Jiaxun Yang
---
This fixes SMP boot for Boston board.
I'm not sure if it's the best palce to make such a callback,
but we can add more global states such as BEV here in future.
---
hw/mips/cps.c| 3 ++-
hw/misc/mips_cmgcr.c | 5 +
target/mips/cpu.c
在 2022/11/7 23:29, Philippe Mathieu-Daudé 写道:
On 7/11/22 23:47, Philippe Mathieu-Daudé wrote:
On 2/11/22 17:57, Jiaxun Yang wrote:
Some implementations (i.e. Loongson-2F) may decide to implement a 64
bit
FPU without implmenting COP1X instructions.
As the eligibility of 64 bit FP
在 2022/11/7 22:35, Philippe Mathieu-Daudé 写道:
On 2/11/22 17:57, Jiaxun Yang wrote:
Accroading to "MIPS Architecture for Programmers Volume IV-c:
The MIPS-3D Application-Specific Extension to the MIPS64 Architecture"
(MD00099). CABS.cond.fmt belongs to MIPS-3D ASE, and it has noth
Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit
FPU without implmenting COP1X instructions.
As the eligibility of 64 bit FP instructions is already determined by
CP0St_FR, there is no need to check for COP1X again.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg
ailability
in decoding code path.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/translate.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index e49d2a25a8..23e575ad95 100644
--- a/target/mips/tcg/translate.c
++
eon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.
Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.
So I believe we shouldn't emulate DSP in QEMU as well.
Signed-off-by: Jiaxun Y
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
---
v2:
Do casting in decodetree. (philmd)
---
targe
As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
Acked-by: Richard Henderson
---
v2
/FlyGoat/qemu/-/tree/mips-virt
v2: Address review comments
Jiaxun Yang (3):
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
target/mips: Cast offset field of Octeon BBIT to int16_t
target/mips: Disable DSP ASE for Octeon68XX
target/mips/cpu-defs.c.inc| 4 ++--
target/mips/cpu.c
> 2022年10月30日 00:19，Philippe Mathieu-Daudé 写道：
>
> On 29/10/22 21:50, Jiaxun Yang wrote:
>>> 2022年10月29日 18:44，Philippe Mathieu-Daudé 写道：
>>>
>>> On 29/10/22 04:00, Jiaxun Yang wrote:
>>>> As per "Loongson-2F processor user man
> 2022年10月29日 18:44，Philippe Mathieu-Daudé 写道：
>
> On 29/10/22 04:00, Jiaxun Yang wrote:
>> As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX}
>> should is not writeable and hardcoded to 1.
>> Without those bits set, kernel is unable to acce
/FlyGoat/qemu/-/tree/mips-virt
Jiaxun Yang (3):
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
target/mips: Cast offset field of Octeon BBIT to int16_t
target/mips: Disable DSP ASE for Octeon68XX
target/mips/cpu-defs.c.inc | 4 ++--
target/mips/cpu.c | 6
As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX}
should is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
---
target/mips/cpu.c | 6 ++
1 file
eon CN7130 processor
and I can confirm CP0C3_DSPP is read as 0 on that processor.
Further more, in linux kernel:
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
cpu_has_dsp is overridden as 0.
So I believe we shouldn't emulate DSP in QEMU as well.
Signed-off-by: Jiaxun Yang
-
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/octeon_translate.c | 2 +-
1 file
mu-devel/5a22bbe1-5023-6fc3-a41b-8d72ec2bb...@flygoat.com/
For the series:
Tested-by: Jiaxun Yang
Reviewed-by: Jiaxun Yang
I thought this series was committed in whole.. Just forgot that there are still
something remaining :-)
Thanks
- Jiaxun
>
> *** BLURB HERE ***
>
So we can do decodetree translation for those exts alone.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/loongson_translate.c | 1290 +
target/mips/tcg/meson.build |1 +
target/mips/tcg/translate.c | 1577 --
target/mips/tcg
Introduce register access functions with value extend capability
to prepare for decodetree based translation implmentation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/translate.c | 143 +++-
target/mips/tcg/translate.h | 54 ++
2 files changed
form MIPS's internal
architecture validation tools so they are gureented to be correct.
Note:
There are some checkpatch warning/error on test cases but I'm not going to
touch them as they are generated code.
Thanks.
RFC->v1:
- Tidy up test cases
- Convert TX79 as well
- Jiaxun
Jiaxun Yang
Move MUL family instructions into decodetree.
Also implement RDHWR emulation for user instructions in decodetree
SQ translation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/translate.c | 410 +--
target/mips/tcg/tx79.decode | 14 ++
target/mips/tcg
MXU is treated as an ISA extension for now.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/mxu_translate.c | 98 ++---
target/mips/tcg/translate.c | 13 ++---
2 files changed, 60 insertions(+), 51 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b
Mostly copy paste from translate.c, with some simplification
based on newly introduced register access functions.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/insn_trans/trans_arith.c.inc | 352 +++
target/mips/tcg/legacy.decode| 62
target/mips/tcg
Those cases are delivered from MIPS internal architecture validation
tools.
Signed-off-by: Jiaxun Yang
---
tests/tcg/mips/include/test_utils_32.h| 75 +++
.../tcg/mips/user/isa/mips32/arithmatic/add.c | 99 ++
.../mips/user/isa/mips32/arithmatic/addi.c| 70
-by: Jiaxun Yang
---
hw/mips/boston.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index d2ab9da1a0..aa7942bbc0 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -424,7 +424,7 @@ static inline XilinxPCIEHost *
xilinx_pcie_init
Please ignore this mail.
Sorry for the noise.
Thanks.
> 2022年10月24日 15:35，Jiaxun Yang 写道：
>
> Hi all,
>
> Just a small addition to make boston board easier to use :-)
>
> Thanks
> - Jiaxun
>
> Jiaxun Yang (2):
> mips/boston: Support initrd for ELF kernel
&
Hi all,
Just a small addition to make boston board easier to use :-)
Thanks
- Jiaxun
Jiaxun Yang (2):
mips/boston: Support initrd for ELF kernel
hw/mips/boston: Pack fdt in fdt filter
hw/mips/boston.c | 40
1 file changed, 40 insertions
2-bit ABI that passes 64-bit arguments in pairs of GPRs. Fix by
> excluding TARGET_ABI_MIPSN32 from various TARGET_ABI_BITS == 32 checks.
>
> Closes: https://gitlab.com/qemu-project/qemu/-/issues/1238
> Signed-off-by: WANG Xuerui
> Cc: Philippe Mathieu-Daudé
> Cc: Jiaxun Yang
> 2022年9月27日 11:33，Jiaxun Yang 写道：
>
>
>
>> 2022年9月26日 22:35，Philippe Mathieu-Daudé 写道：
>>
>> Hi Jiaxun,
>>
>> On Mon, Sep 26, 2022 at 4:44 PM Jiaxun Yang wrote:
>>>> 2022年9月21日 13:41，Jiaxun Yang 写道：
>>>>
>>
> 2022年9月26日 22:35，Philippe Mathieu-Daudé 写道：
>
> Hi Jiaxun,
>
> On Mon, Sep 26, 2022 at 4:44 PM Jiaxun Yang wrote:
>>> 2022年9月21日 13:41，Jiaxun Yang 写道：
>>>
>>> Hi,
>>>
>>> This is my attempt of converting MIPS translation
> 2022年9月21日 13:41，Jiaxun Yang 写道：
>
> Hi,
>
> This is my attempt of converting MIPS translation code into decodetree.
>
> Currently only MIPS I to MIPS Release 5 arithmatic functions are converted.
> Old decoding functions are perserved in codebase for now du
dealing with
release 6.
Both instruction encoding and test cases are generated form MIPS's internal
architecture validation tools so they are gureented to be correct.
Thanks.
- Jiaxun
Jiaxun Yang (3):
target/mips: Introduce register access helper functions
target/mips: Convert legacy
Mostly copy paste from translate.c, with some simplification
based on newly introduced register access functions.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/insn_trans/trans_arith.c.inc | 352 +++
target/mips/tcg/legacy.decode| 62
target/mips/tcg
Introduce register access functions with value extend capability
to prepare for decodetree based translation implmentation.
Signed-off-by: Jiaxun Yang
---
target/mips/tcg/translate.c | 143 +++-
target/mips/tcg/translate.h | 54 ++
2 files changed
Those cases are delivered from MIPS internal architecture validation
tools.
Signed-off-by: Jiaxun Yang
---
tests/tcg/mips/include/test_utils_32.h| 75 +++
.../tcg/mips/user/isa/mips32/arithmatic/add.c | 99 ++
.../mips/user/isa/mips32/arithmatic/addi.c| 70
> 2022年8月16日 01:44，Philippe Mathieu-Daudé 写道：
>
> On 13/8/22 18:27, Jiaxun Yang wrote:
>> FDT can be awfully fat after series of modifications in fdt
>> filter. Just pack it up before add to ram.
>> Signed-off-by: Jiaxun Yang
>> ---
>> hw/mips/boston.
Hi all,
Just a small addition to make boston board easier to use :-)
Thanks
- Jiaxun
Jiaxun Yang (2):
mips/boston: Support initrd for ELF kernel
hw/mips/boston: Pack fdt in fdt filter
hw/mips/boston.c | 40
1 file changed, 40 insertions
When loading ELF kernel we can just load out initrd after DTB
and append initrd information to DeviceTree's chosen node.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/hw/mips/boston.c b/hw/mips
FDT can be awfully fat after series of modifications in fdt
filter. Just pack it up before add to ram.
Signed-off-by: Jiaxun Yang
---
hw/mips/boston.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 5145179951..a40f193f78 100644
--- a/hw/mips
Hi all,
This series properly filled AT_BASE_PLATFORM of MIPS.
There is a checkpatch error about braces after if statement,
I intentionally left it for style consistency.
v2: Commit meesage rewording (philmd)
Thanks.
- Jiaxun
Jiaxun Yang (2):
linux-user: Introduce stubs for ELF
AT_BASE_PLATFORM is a elf auxiliary vector pointing to a string
to pass some architecture information.
See getauxval(3) man-page.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 29 +++--
1 file changed, 27 insertions(+), 2
Match most appropriate base platform string based on insn_flags.
Logic is aligned with aligned with set_isa() from
arch/mips/kernel/cpu-probe.c in Linux kernel.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 31 +++
1 file
AT_BASE_PLATFORM is a elf auxiliary vector pointing to a string
to pass some architecture information.
Signed-off-by: Jiaxun Yang
---
linux-user/elfload.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user
Match most appropriate base platform string based on insn_flags.
Logic is aligned with arch/mips/kernel/cpu-probe.c in Linux kernel.
Signed-off-by: Jiaxun Yang
---
linux-user/elfload.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/linux-user/elfload.c b
Hi all,
This series properly filled AT_BASE_PLATFORM of MIPS.
There is a checkpatch error about braces after if statement,
I intentionally left it for style consistency.
Thanks.
- Jiaxun
Jiaxun Yang (2):
linux-user: Introduce stubs for ELF AT_BASE_PLATFORM
linux-user: Set ELF_BASE_PLATFORM
has some patches applied.
For the whole series:
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Run some sample program with GCC unaligned-access enabled.
Thanks.
r~
Richard Henderson (2):
tcg/mips: Support unaligned access for user-only
tcg/mips: Support unaligned access for sof
在2021年12月26日十二月 上午12:19，Philippe Mathieu-Daudé写道：
> Unfortunately this fails:
>
> $ make run-tcg-tests-mips64el-linux-user
> ...
> Files float_convs.out and tests/tcg/mips64el/float_convs.ref differ
> --- float_convs.out 2021-12-26 01:03:48.585973637 +0100
> +++
在2021年12月2日十二月 下午6:01，Philippe Mathieu-Daudé写道：
> On 12/2/21 11:51, Jiaxun Yang wrote:
>> 在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
>>> On 11/30/21 22:17, Jiaxun Yang wrote:
>>>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>>&
在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
> On 11/30/21 22:17, Jiaxun Yang wrote:
>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>> while sd is illegal on 32 bit CPUs.
>>
>> Replace sd with sw on 32bit CPUs.
>>
>> Fixes: 3ebbf86 ("
load_elf gives negative return in case of error, not zero.
Fixes: 10e3f30 ("hw/mips/boston: Allow loading elf kernel and dtb")
Signed-off-by: Jiaxun Yang
---
For 6.2.
---
hw/mips/boston.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/mips/boston.c
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