On Tue, 7 May 2024 00:22:00 +
"Xingtao Yao (Fujitsu)" wrote:
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: Tuesday, April 30, 2024 10:43 PM
> > To: Yao, Xingtao/姚 幸涛
> > Cc: fan...@samsung.com; qemu-devel@nongnu.org
> > Subject: Re: [PATCH v2] mem/cxl_type3: support
> > >> > +# @hid: host id
> > >>
> > >> @host-id, unless "HID" is established terminology in CXL DCD land.
> > >
> > > host-id works.
> > >>
> > >> What is a host ID?
> > >
> > > It is an id identifying the host to which the capacity is being added.
> >
> > How are these IDs
On Mon, 29 Apr 2024 09:58:42 +0200
Markus Armbruster wrote:
> fan writes:
>
> > On Fri, Apr 26, 2024 at 11:12:50AM +0200, Markus Armbruster wrote:
> >> nifan@gmail.com writes:
>
> [...]
>
> >> > diff --git a/qapi/cxl.json b/qapi/cxl.json
> >> > index 4281726dec..2dcf03d973 100644
>
On Wed, 24 Apr 2024 01:36:56 +
"Xingtao Yao (Fujitsu)" wrote:
> ping.
>
> > -Original Message-
> > From: Yao Xingtao
> > Sent: Sunday, April 7, 2024 11:07 AM
> > To: jonathan.came...@huawei.com; fan...@samsung.com
> > Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛
> > Subject:
On Tue, 30 Apr 2024 08:55:12 +0200
Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > On Tue, 23 Apr 2024 12:56:21 +0200
> > Markus Armbruster wrote:
> >
> >> Jonathan Cameron writes:
> >>
> >> > These are very similar to the recently added Generic Initiators
> >> > but instead
On Tue, 23 Apr 2024 12:56:21 +0200
Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > These are very similar to the recently added Generic Initiators
> > but instead of representing an initiator of memory traffic they
> > represent an edge point beyond which may lie either targets or
>
On Thu, 25 Apr 2024 10:30:51 -0700
Ira Weiny wrote:
> Markus Armbruster wrote:
> > fan writes:
> >
> > > On Wed, Apr 24, 2024 at 03:09:52PM +0200, Markus Armbruster wrote:
> > >> nifan@gmail.com writes:
> > >>
> > >> > From: Fan Ni
> > >> >
> > >> > Since fabric manager emulation
On Wed, 24 Apr 2024 10:33:33 -0700
Ira Weiny wrote:
> Markus Armbruster wrote:
> > nifan@gmail.com writes:
> >
> > > From: Fan Ni
> > >
> > > Since fabric manager emulation is not supported yet, the change implements
> > > the functions to add/release dynamic capacity extents as QMP
On Mon, 22 Apr 2024 15:23:16 +0100
Jonathan Cameron wrote:
> On Mon, 22 Apr 2024 13:04:48 +0100
> Jonathan Cameron wrote:
>
> > On Sat, 20 Apr 2024 16:35:46 -0400
> > Gregory Price wrote:
> >
> > > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> > > > On Fri, Apr 19, 2024 at
On Mon, 22 Apr 2024 13:04:48 +0100
Jonathan Cameron wrote:
> On Sat, 20 Apr 2024 16:35:46 -0400
> Gregory Price wrote:
>
> > On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> > > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> > > >
> > > > added review to all
On Sat, 20 Apr 2024 16:35:46 -0400
Gregory Price wrote:
> On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> > On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> > >
> > > added review to all patches, will hopefully be able to add a Tested-by
> > > tag early next week, along
On Thu, 18 Apr 2024 16:11:00 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
Hi Fan,
Please expand CC list to include QAPI maintainers.
+CC Markus and Micheal.
Also, for future versions +CC Michael Tsirkin.
I'm find rolling these up as a series with the precursors but
if it is already some
On Fri, 19 Apr 2024 13:27:59 -0400
Gregory Price wrote:
> On Thu, Apr 18, 2024 at 04:10:57PM -0700, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > Add (file/memory backed) host backend for DCD. All the dynamic capacity
> > regions will share a single, large enough host backend. Set up
On Thu, 18 Apr 2024 16:10:57 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend for DCD. All the dynamic capacity
> regions will share a single, large enough host backend. Set up address
> space for DC regions to support read/write operations to dynamic
On Fri, 19 Apr 2024 17:40:07 +0200
Philippe Mathieu-Daudé wrote:
> On 18/4/24 12:04, Zhao Liu wrote:
> > From: Zhao Liu
>
>
> > ---
> > Zhao Liu (3):
> >hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean
> >hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean
> >
On Fri, 19 Apr 2024 13:52:07 +0200
Gerd Hoffmann wrote:
> Hi,
>
> > Gerd, any ideas? Maybe I needs something subtly different in my
> > edk2 build? I've not looked at this bit of the qemu infrastructure
> > before - is there a document on how that image is built?
>
> There is
On Fri, 5 Apr 2024 00:07:06 +
"Ho-Ren (Jack) Chuang" wrote:
> The current implementation treats emulated memory devices, such as
> CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> (E820_TYPE_RAM). However, these emulated devices have different
> characteristics
On Thu, 18 Apr 2024 09:15:55 +0100
Jonathan Cameron via wrote:
> On Wed, 17 Apr 2024 13:07:35 -0700
> Richard Henderson wrote:
>
> > On 4/16/24 08:11, Jonathan Cameron wrote:
> > > On Fri, 1 Mar 2024 10:41:09 -1000
> > > Richard Henderson wrote:
> > &
On Thu, 18 Apr 2024 14:06:39 +0200
Philippe Mathieu-Daudé wrote:
> On 18/4/24 12:04, Zhao Liu wrote:
> > From: Zhao Liu
>
>
> > ---
> > Zhao Liu (3):
> >hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean
> >hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean
> >
On Wed, 17 Apr 2024 13:07:35 -0700
Richard Henderson wrote:
> On 4/16/24 08:11, Jonathan Cameron wrote:
> > On Fri, 1 Mar 2024 10:41:09 -1000
> > Richard Henderson wrote:
> >
> >> If translation is disabled, the default memory type is Device, which
> >> requires alignment checking. This is
On Tue, 16 Apr 2024 09:37:09 -0700
fan wrote:
> On Tue, Apr 16, 2024 at 04:00:56PM +0100, Jonathan Cameron wrote:
> > On Mon, 15 Apr 2024 10:37:00 -0700
> > fan wrote:
> >
> > > On Fri, Apr 12, 2024 at 06:54:42PM -0400, Gregory Price wrote:
> > > > On Mon, Mar 25, 2024 at 12:02:28PM -0700,
> > >
> > > ret = cxl_detect_malformed_extent_list(ct3d, in);
> > > if (ret != CXL_MBOX_SUCCESS) {
> > > +cxl_extent_group_list_delete_front(>dc.extents_pending);
> >
> > If it's a bad message from the host, I don't think the device is supposed to
> > do anything with
On Fri, 1 Mar 2024 10:41:09 -1000
Richard Henderson wrote:
> If translation is disabled, the default memory type is Device, which
> requires alignment checking. This is more optimally done early via
> the MemOp given to the TCG memory operation.
>
> Reviewed-by: Philippe Mathieu-Daudé
>
On Mon, 15 Apr 2024 10:37:00 -0700
fan wrote:
> On Fri, Apr 12, 2024 at 06:54:42PM -0400, Gregory Price wrote:
> > On Mon, Mar 25, 2024 at 12:02:28PM -0700, nifan@gmail.com wrote:
> > > From: Fan Ni
> > >
> > > All dpa ranges in the DC regions are invalid to access until an extent
> > >
On Mon, 15 Apr 2024 13:06:04 -0700
fan wrote:
> From ce75be83e915fbc4dd6e489f976665b81174002b Mon Sep 17 00:00:00 2001
> From: Fan Ni
> Date: Tue, 20 Feb 2024 09:48:31 -0800
> Subject: [PATCH 09/13] hw/cxl/events: Add qmp interfaces to add/release
> dynamic capacity extents
>
> To simulate FM
On Tue, 9 Apr 2024 15:58:46 +0800
Li Zhijian wrote:
> After the kernel commit
> 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not
> match a CFMWS window")
> CXL type3 devices cannot be enabled again after the reboot because the
> control register(see 8.1.3.2 in CXL
On Tue, 9 Apr 2024 14:26:51 -0700
fan wrote:
> On Fri, Apr 05, 2024 at 01:18:56PM +0100, Jonathan Cameron wrote:
> > On Mon, 25 Mar 2024 12:02:27 -0700
> > nifan@gmail.com wrote:
> >
> > > From: Fan Ni
> > >
> > > To simulate FM functionalities for initiating Dynamic Capacity Add
> > >
On Tue, 9 Apr 2024 12:02:31 -0700
"Ho-Ren (Jack) Chuang" wrote:
> Hi Jonathan,
>
> On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 5 Apr 2024 15:43:47 -0700
> > "Ho-Ren (Jack) Chuang" wrote:
> >
> > > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron
> > > wrote:
>
On Fri, 5 Apr 2024 15:43:47 -0700
"Ho-Ren (Jack) Chuang" wrote:
> On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron
> wrote:
> >
> > On Fri, 5 Apr 2024 00:07:06 +
> > "Ho-Ren (Jack) Chuang" wrote:
> >
> > > The current implementation treats emulated memory devices, such as
> > > CXL1.1
On Fri, 5 Apr 2024 14:09:23 -0400
Gregory Price wrote:
> On Fri, Apr 05, 2024 at 06:44:52PM +0100, Jonathan Cameron wrote:
> > On Fri, 5 Apr 2024 12:07:45 -0400
> > Gregory Price wrote:
> >
> > > 3. (C) Upon Device receiving Release Dynamic Capacity Request
> > >a. check for a pending
On Mon, 8 Apr 2024 13:58:00 +0200
Marcin Juszkiewicz wrote:
> For quite a while I am experimenting with PCI Express setup on SBSA-Ref
> system. And finally decided to write.
>
> We want to play with NUMA setup and "pxb-pcie" can be assigned to NUMA
> node other than cpu0 one. But adding it
On Fri, 5 Apr 2024 12:07:45 -0400
Gregory Price wrote:
> On Fri, Apr 05, 2024 at 01:27:19PM +0100, Jonathan Cameron wrote:
> > On Wed, 3 Apr 2024 14:16:25 -0400
> > Gregory Price wrote:
> >
> > A few follow up comments.
> >
> > >
> > > > +error_setg(errp, "no valid extents to
On Fri, 15 Mar 2024 10:29:07 +0800
Shiyang Ruan wrote:
> 在 2024/2/14 0:51, Jonathan Cameron 写道:
> >
> >> +
> >> +void cxl_event_handle_record(struct cxl_memdev *cxlmd,
> >> + enum cxl_event_log_type type,
> >> + enum cxl_event_type event_type,
> >>
On Mon, 1 Apr 2024 17:00:50 +0100
Jonathan Cameron via wrote:
> On Thu, 28 Mar 2024 06:24:24 +
> "Xingtao Yao (Fujitsu)" wrote:
>
> > Jonathan
> >
> > thanks for your reply!
> >
> > > -Original Message-
> > > From: Jo
On Fri, 5 Apr 2024 00:07:06 +
"Ho-Ren (Jack) Chuang" wrote:
> The current implementation treats emulated memory devices, such as
> CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> (E820_TYPE_RAM). However, these emulated devices have different
> characteristics
On Fri, 5 Apr 2024 00:07:05 +
"Ho-Ren (Jack) Chuang" wrote:
> Since different memory devices require finding, allocating, and putting
> memory types, these common steps are abstracted in this patch,
> enhancing the scalability and conciseness of the code.
>
> Signed-off-by: Ho-Ren (Jack)
On Mon, 25 Mar 2024 12:02:30 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Before the change, the QMP interface used for add/release DC extents
> only allows to release an extent whose DPA range is contained by a single
> accepted extent in the device.
>
> With the change, we relax the
On Mon, 25 Mar 2024 12:02:29 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, we extend the extent release mailbox command processing
> to allow more flexible release. As long as the DPA range of the extent to
> release is covered by accepted extent(s) in the device, the
On Mon, 25 Mar 2024 12:02:28 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> All dpa ranges in the DC regions are invalid to access until an extent
Let's be more consistent for commit logs and use DPA DC HPA etc all
caps. It's a bit of a mixture in this series at the moment.
> covering
On Wed, 3 Apr 2024 14:16:25 -0400
Gregory Price wrote:
A few follow up comments.
> On Mon, Mar 25, 2024 at 12:02:27PM -0700, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > To simulate FM functionalities for initiating Dynamic Capacity Add
> > (Opcode 5604h) and Dynamic Capacity Release
On Mon, 25 Mar 2024 12:02:27 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> To simulate FM functionalities for initiating Dynamic Capacity Add
> (Opcode 5604h) and Dynamic Capacity Release (Opcode 5605h) as in CXL spec
> r3.1 7.6.7.6.5 and 7.6.7.6.6, we implemented two QMP interfaces to
On Mon, 25 Mar 2024 12:02:26 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Per CXL spec 3.1, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
>
> For the process of the above two
On Thu, 4 Apr 2024 13:32:23 +
Jørgen Hansen wrote:
Hi Jørgen,
> > +static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
> > + uint8_t *payload_in,
> > + size_t len_in,
> > +
On Mon, 25 Mar 2024 12:02:25 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add dynamic capacity extent list representative to the definition of
> CXLType3Dev and implement get DC extent list mailbox command per
> CXL.spec.3.1:.8.2.9.9.9.2.
>
> Signed-off-by: Fan Ni
One really minor
On Mon, 25 Mar 2024 12:02:24 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend, all the dynamic capacity regions
> will share a single, large enough host backend.
This doesn't parse. I suggests splitting it into 2 sentences.
Add (file/memory backend)
On Wed, 3 Apr 2024 22:56:58 +0800
Shiyang Ruan wrote:
> 在 2024/3/30 9:50, Dan Williams 写道:
> > Shiyang Ruan wrote:
> >> The GMER only has "Physical Address" field, no such one indicates length.
> >> So, when a poison event is received, we could use GET_POISON_LIST command
> >> to get the
> > > @@ -858,7 +910,8 @@ static int __init memory_tier_init(void)
> > >* For now we can have 4 faster memory tiers with smaller adistance
> > >* than default DRAM tier.
> > >*/
> > > - default_dram_type = alloc_memory_type(MEMTIER_ADISTANCE_DRAM);
> > > +
A few minor comments inline.
> diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h
> index a44c03c2ba3a..16769552a338 100644
> --- a/include/linux/memory-tiers.h
> +++ b/include/linux/memory-tiers.h
> @@ -140,12 +140,13 @@ static inline int mt_perf_to_adistance(struct
>
On Tue, 2 Apr 2024 00:17:37 +
"Ho-Ren (Jack) Chuang" wrote:
> Since different memory devices require finding, allocating, and putting
> memory types, these common steps are abstracted in this patch,
> enhancing the scalability and conciseness of the code.
>
> Signed-off-by: Ho-Ren (Jack)
Given this is a new configuration, there are affects on APIC, CEDT
and DSDT, but the key elements are in SRAT (plus related data in
HMAT). The configuration has node to exercise many different combinations.
0) CPUs + Memory
1) GI only
2) GP only
3) CPUS only
4) Memory only
5) CPUs + HP memory
Add a test with 6 nodes to exercise most interesting corner cases
of SRAT and HMAT generation including the new Generic Initiator
and Generic Port Affinity structures. More details of the
set up in the following patch adding the table data.
Signed-off-by: Jonathan Cameron
---
The test to be added exercises many corners of the SRAT and HMAT
table generation.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +
tests/data/acpi/q35/APIC.acpihmat-generic-x | 0
tests/data/acpi/q35/CEDT.acpihmat-generic-x | 0
These are very similar to the recently added Generic Initiators
but instead of representing an initiator of memory traffic they
represent an edge point beyond which may lie either targets or
initiators. Here we add these ports such that they may
be targets of hmat_lb records to describe the
This will simplify reuse when adding acpi-generic-port.
Note that some error_printf() messages will now print acpi-generic-node
whereas others will move to type specific cases in next patch so
are left alone for now.
Signed-off-by: Jonathan Cameron
---
include/hw/acpi/acpi_generic_initiator.h |
Before making additional modification, tidy up this misleading indentation.
Signed-off-by: Jonathan Cameron
---
hw/acpi/acpi_generic_initiator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/acpi_generic_initiator.c b/hw/acpi/acpi_generic_initiator.c
index
ACPI 6.5 introduced Generic Port Affinity Structures to close a system
description gap that was a problem for CXL memory systems.
It defines an new SRAT Affinity structure (and hence allows creation of an
ACPI Proximity Node which can only be defined via an SRAT structure)
for the boundary between
On Tue, 2 Apr 2024 09:46:47 +0800
Li Zhijian wrote:
> After the kernel commit
> 0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not
> match a CFMWS window")
Fixes tag seems appropriate.
> CXL type3 devices cannot be enabled again after the reboot because this
> flag was
On Tue, 2 Apr 2024 09:46:46 +0800
Li Zhijian wrote:
> It helps to figure out where the first dvsec register is located. In
> addition, replace offset and size hardcore with existing macros.
>
> Signed-off-by: Li Zhijian
I agree we should be using the macros.
The offset calc is a bit
On Sun, 21 Jan 2024 21:50:00 -0500
Hyeonggon Yoo <42.hye...@gmail.com> wrote:
> On Tue, Jan 9, 2024 at 12:54 PM Jonathan Cameron
> wrote:
> >
> > On Fri, 22 Dec 2023 18:00:50 +0900
> > Hyeonggon Yoo <42.hye...@gmail.com> wrote:
> >
> > > The spec states that reads/writes should have no effect
On Thu, 28 Mar 2024 16:54:16 +0100
Philippe Mathieu-Daudé wrote:
> CXL depends on PCIe, which isn't available on non-PCI
> machines such the ISA-only PC one.
> Move CXLState to PcPciMachineState, and move the CXL
> specific calls to pc_pci_machine_initfn() and
> pc_pci_machine_done().
>
>
On Wed, 27 Mar 2024 17:16:42 +0100
Philippe Mathieu-Daudé wrote:
> CXL is based on PCIe. In is pointless to initialize
> its context on non-PCI machines.
>
> Signed-off-by: Philippe Mathieu-Daudé
Seems a reasonable restriction.
Acked-by: Jonathan Cameron
Jonathan
> ---
> hw/i386/pc.c | 4
On Thu, 28 Mar 2024 06:24:24 +
"Xingtao Yao (Fujitsu)" wrote:
> Jonathan
>
> thanks for your reply!
>
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: Wednesday, March 27, 2024 9:28 PM
> > To: Yao, Xingtao/姚 幸涛
> > Cc: fan...@samsung.com; qemu-devel@nongnu.org; Cao,
On Tue, 26 Mar 2024 21:46:53 -0400
Yao Xingtao wrote:
> In 3, 6, 12 interleave ways, we could not access cxl memory properly,
> and when the process is running on it, a 'segmentation fault' error will
> occur.
>
> According to the CXL specification '8.2.4.20.13 Decoder Protection',
> there are
On Mon, 18 Mar 2024 10:29:28 +0800
Yuquan Wang wrote:
> The dev_dbg info for Clear Event Records mailbox command would report
> the handle of the next record to clear not the current one.
>
> This was because the index 'i' had incremented before printing the
> current handle value.
>
>
On Wed, 13 Mar 2024 21:24:06 +0300
Michael Tokarev wrote:
> 07.03.2024 19:03, Jonathan Cameron via wrote:
> > With a numa set up such as
> >
> > -numa nodeid=0,cpus=0 \
> > -numa nodeid=1,memdev=mem \
> > -numa nodeid=2,cpus=1
> >
> > and a
On Fri, 15 Mar 2024 09:52:28 +0800
Yuquan Wang wrote:
> Hello, Jonathan
>
> When during the test of qmps of CXL events like
> "cxl-inject-general-media-event",
> I am confuesd about the argument "flags". According to "qapi/cxl.json" in
> qemu,
> this argument represents "Event Record Flags"
On Fri, 8 Mar 2024 20:35:53 -0800
fan wrote:
> On Thu, Mar 07, 2024 at 12:45:55PM +, Jonathan Cameron wrote:
> > ...
> >
> > > > > +list = records;
> > > > > +extents = g_new0(CXLDCExtentRaw, num_extents);
> > > > > +while (list) {
> > > > > +CXLDCExtent *ent;
> > > >
On Fri, 8 Mar 2024 14:55:25 +
wrote:
> From: Ankit Agrawal
>
> The acpi-generic-initiator object is added to allow a host device
> to be linked with a NUMA node. Qemu use it to build the SRAT
> Generic Initiator Affinity structure [1]. Add support for i386.
>
> [1] ACPI Spec 6.3, Section
On Fri, 8 Mar 2024 14:38:55 +
Peter Maydell wrote:
> On Fri, 8 Mar 2024 at 14:34, Jonathan Cameron
> wrote:
> >
> > On Fri, 8 Mar 2024 13:47:47 +
> > Peter Maydell wrote:
> > > Is there a way we could write this that would catch this error?
> > > I'm thinking maybe something like
> >
The r3.1 specification introduced a new 2 byte field, but
to maintain DWORD alignment, a additional 2 reserved bytes
were added. Forgot those in updating the structure definition
but did include them in the size define leading to a buffer
overrun.
Also use the define so that we don't duplicate
On Fri, 8 Mar 2024 13:47:47 +
Peter Maydell wrote:
> On Wed, 14 Feb 2024 at 11:16, Michael S. Tsirkin wrote:
> >
> > From: Jonathan Cameron
> >
> > Previously not all references mentioned any spec version at all.
> > Given r3.1 is the current specification available for evaluation at
> >
On Fri, 8 Mar 2024 10:01:34 +0800
Yuquan Wang wrote:
> On 2024-03-07 20:10, jonathan.cameron wrote:
>
> > Hack is fine the relevant device with lspci -tv and then use
> > setpci -s 0d:00.0 0x208.l=0
> > to clear all the mask bits for uncorrectable errors.
>
> Thanks! The suggestions from
On Thu, 4 Jan 2024 00:44:43 +
Hao Xiang wrote:
> * Add a DSA task completion callback.
> * DSA completion thread will call the tasks's completion callback
> on every task/batch task completion.
> * DSA submission path to wait for completion.
> * Implement CPU fallback if DSA is not able to
With a numa set up such as
-numa nodeid=0,cpus=0 \
-numa nodeid=1,memdev=mem \
-numa nodeid=2,cpus=1
and appropriate hmat_lb entries the initiator list is correctly
computed and writen to HMAT as 0,2 but then the LB data is accessed
using the node id (here 2), landing outside the entry_list
If qemu is started with a proximity node containing CPUs alone,
it will provide one of these structures to say memory in this
node is directly connected to itself.
This description is arguably pointless even if there is memory
in the node. If there is no memory present, and hence no SRAT
entry
v2: Fixed a link in patch 1 description so it points somewhere stable.
Two unrelated fixes here:
1) Linux really doesn't like it when you claim non existent memory
is directly connected to an initiator (here a CPU).
It is a nonsense entry, though I also plan to try and get
a relaxation
From: Gregory Price
CXL emulation of interleave requires read and write hooks due to
requirement for subpage granularity. The Linux kernel stack now enables
using this memory as conventional memory in a separate NUMA node. If a
process is deliberately forced to run from that node
$ numactl
Previously: tcg/i386: Page tables in MMIO memory fixes (CXL)
Richard Henderson picked up patches 1 and 3 which were architecture independent
leaving just this x86 specific patch.
No change to the patch. Resending because it's hard to spot individual
unapplied patches in a larger series.
Original
If the access is bigger than the MemoryRegion supports,
flatview_read/write_continue() will attempt to update the Memory Region.
but the address passed to flatview_translate() is relative to the cache, not
to the FlatView.
On arm/virt with interleaved CXL memory emulation and virtio-blk-pci this
This code will be reused for the address_space_cached accessors
shortly.
Also reduce scope of result variable now we aren't directly
calling this in the loop.
Signed-off-by: Jonathan Cameron
---
v2: Thanks to Peter Xu
- Fix alignment of code.
- Drop unused addr parameter.
- Carry through new
Precursor to factoring out the inner loops for reuse.
Reviewed-by: Peter Xu
Signed-off-by: Jonathan Cameron
---
v2: Picked up tag from Peter.
system/physmem.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/system/physmem.c
The calls to flatview_read/write[_continue]() have parameters addr and
addr1 but the names give no indication of what they are addresses of.
Rename addr1 to mr_addr to reflect that it is the translated address
offset within the MemoryRegion returned by flatview_translate().
Similarly rename the
v2: (Thanks to Peter Xu for reviewing!)
- New patch 1 to rename addr1 to mr_addr in the interests of meaningful naming.
- Take advantage of a cached address space only allow for a single MR to
simplify
the new code.
- Various cleanups of indentation etc.
- Cover letter and some patch
On Fri, 1 Mar 2024 13:44:01 +0800
Peter Xu wrote:
> On Thu, Feb 15, 2024 at 02:28:17PM +, Jonathan Cameron wrote:
>
> Can we rename the subject?
>
> physmem: Fix wrong MR in large address_space_read/write_cached_slow()
>
> IMHO "wrong MR" is misleading, as the MR was wrong only because
On Fri, 1 Mar 2024 13:35:26 +0800
Peter Xu wrote:
> On Fri, Mar 01, 2024 at 01:29:04PM +0800, Peter Xu wrote:
> > On Thu, Feb 15, 2024 at 02:28:16PM +, Jonathan Cameron wrote:
> > > This code will be reused for the address_space_cached accessors
> > > shortly.
> > >
> > > Also reduce
> >
> > > + * remove it from the pending extent list, so later when the
> > > add
> > > + * response for the extent arrives, the device can reject the
> > > + * extent as it is not in the pending list.
> > > + */
> > > +ent =
...
> > > +list = records;
> > > +extents = g_new0(CXLDCExtentRaw, num_extents);
> > > +while (list) {
> > > +CXLDCExtent *ent;
> > > +bool skip_extent = false;
> > > +
> > > +offset = list->value->offset;
> > > +len = list->value->len;
> > > +
> > > +
> > > +static void cxl_destroy_dc_regions(CXLType3Dev *ct3d)
> > > +{
> > > +CXLDCExtent *ent;
> > > +
> > > +while (!QTAILQ_EMPTY(>dc.extents)) {
> > > +ent = QTAILQ_FIRST(>dc.extents);
> > > +cxl_remove_extent_from_extent_list(>dc.extents, ent);
> >
> > Isn't this same
On Wed, 6 Mar 2024 13:39:50 -0800
fan wrote:
> > > +}
> > > +if (len2) {
> > > +cxl_insert_extent_to_extent_list(extent_list,
> > > dpa + len,
> > > + len2, NULL, 0);
> > >
> > > @@ -868,16 +974,24 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev
> > > *ct3d,
> > > AddressSpace **as,
> > > uint64_t *dpa_offset)
> > > {
> > > -MemoryRegion *vmr = NULL, *pmr = NULL;
> > > +
On Thu, 7 Mar 2024 10:58:56 +1000
Alistair Francis wrote:
> The Security Protocol and Data Model (SPDM) Specification defines
> messages, data objects, and sequences for performing message exchanges
> over a variety of transport and physical media.
> -
>
On Thu, 7 Mar 2024 03:03:02 +
Ankit Agrawal wrote:
> >>
> >> [1] ACPI Spec 6.3, Section 5.2.16.6
> >> [2] ACPI Spec 6.3, Table 5.80
> >>
> >> Cc: Jonathan Cameron
> >> Cc: Alex Williamson
> >> Cc: Cedric Le Goater
> >> Signed-off-by: Ankit Agrawal
> >
> > I guess we gloss over the
On Mon, 4 Mar 2024 11:34:07 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Before the change, the QMP interface used for add/release DC extents
> only allows to release extents that exist in either pending-to-add list
> or accepted list in the device, which means the DPA range of the
On Mon, 4 Mar 2024 11:34:06 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, we extend the extent release mailbox command processing
> to allow more flexible release. As long as the DPA range of the extent to
> release is covered by valid extent(s) in the device, the
On Mon, 4 Mar 2024 11:34:05 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Not all dpa range in the DC regions is valid to access until an extent
All DPA ranges in the DC regions are invalid to access until an extent
covering the range has been added.
> covering the range has been
On Mon, 4 Mar 2024 11:34:04 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Since fabric manager emulation is not supported yet, the change implements
> the functions to add/release dynamic capacity extents as QMP interfaces.
We'll need them anyway, or to implement an fm interface via QMP
On Mon, 4 Mar 2024 11:34:03 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Per CXL spec 3.1, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
>
> Signed-off-by: Fan Ni
Hmm. So I
On Mon, 4 Mar 2024 11:34:02 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add dynamic capacity extent list representative to the definition of
> CXLType3Dev and add get DC extent list mailbox command per
> CXL.spec.3.1:.8.2.9.9.9.2.
>
> Signed-off-by: Fan Ni
Hi Fan,
A small thing in
On Mon, 4 Mar 2024 11:34:01 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend, all the dynamic capacity regions
> will share a single, large enough host backend. Set up address space for
> DC regions to support read/write operations to dynamic capacity
On Mon, 4 Mar 2024 11:34:00 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> The function ct3_build_cdat_entries_for_mr only uses size of the passed
> memory region argument, refactor the function definition to make the passed
> arguments more specific.
>
> Signed-off-by: Fan Ni
1 - 100 of 1599 matches
Mail list logo
