00 callq 401d20 __libc_start_main
401c17: f4 hlt
401c18: 0f 1f 84 00 00 00 00nopl 0x0(%rax,%rax,1)
401c1f: 00
On Sun, Jun 7, 2015 at 6:34 AM, Peter Maydell peter.mayd...@linaro.org
wrote:
On 6 June 2015 at 08:36, Sandhya Kumar
2015 at 10:24, Sandhya Kumar insatiablecuriousit...@gmail.com
wrote:
Well, I think we can also achieve this like adding a flag in the
structure
of CPUTLBEntry.
Am I missing something?
The point of the TLB data structure is to allow very fast access
in the common case of TLB hit to guest RAM
, Paolo Bonzini pbonz...@redhat.com wrote:
On 03/06/2015 09:41, Sandhya Kumar wrote:
Thanks for your mail. Are these TLB modes logic specific to QEMU
implementation for x86?
Yes, they are specific to QEMU.
Asking this as I am not able to get any information about seperate TLBs
from
[Query on intended logic]
I am trying to learn qemu's MMU emulation logic for x86 and came across H.
Peter Anvin's SMAP commit (link
http://lists.gnu.org/archive/html/qemu-devel/2012-09/msg04622.html). I
have the following doubt on the intended logic (apologies if it is trivial)
As per my
Well, I think we can also achieve this like adding a flag in the structure
of CPUTLBEntry.
Am I missing something?
On Wed, Jun 3, 2015 at 4:22 PM, Paolo Bonzini pbonz...@redhat.com wrote:
On 03/06/2015 10:07, Sandhya Kumar wrote:
Thanks again. One more question.
On versions prior
Thanks for your mail. Are these TLB modes logic specific to QEMU
implementation for x86?
Asking this as I am not able to get any information about seperate TLBs
from Intel developer manuals
On Wed, Jun 3, 2015 at 3:01 PM, Paolo Bonzini pbonz...@redhat.com wrote:
On 03/06/2015 08:51, Sandhya
