On Fri, May 19, 2023 at 10:29:47AM +0200, Paolo Bonzini wrote:
> On 5/19/23 05:06, Yang Zhong wrote:
> >
> > Paolo, please help add below queued sgx fix into this PULL request, which
> > was
> > missed from last time, thanks a lot!
> > https://lists.nongnu.or
Paolo, please help add below queued sgx fix into this PULL request, which was
missed from last time, thanks a lot!
https://lists.nongnu.org/archive/html/qemu-devel/2023-04/msg00841.html
https://lists.nongnu.org/archive/html/qemu-devel/2023-04/msg00896.html
Regards,
Yang
On Sun, Apr 09, 2023 at 04:40:50PM +0300, Michael Tokarev wrote:
> 06.04.2023 09:40, Yang Zhong wrote:
> > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> > SGX enclave only supporte
On Thu, Apr 06, 2023 at 02:05:06PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
>
Paolo, thanks!
Yang
> Paolo
>
>
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by:
previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > > > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> > > > SGX enclave only supported SSE and x87 feature(xfrm=0x3).
> > > >
> > > > Fixes: 301e90675c3f ("target
On Wed, Mar 22, 2023 at 12:22:27PM -0600, Alex Williamson wrote:
> On Wed, 22 Mar 2023 09:10:20 -0400
> Yang Zhong wrote:
>
> > On Wed, Mar 22, 2023 at 01:56:13PM +0100, Cédric Le Goater wrote:
> > > On 3/22/23 13:28, Yang Zhong wrote:
> > > > On Tue, Mar
On Wed, Mar 22, 2023 at 01:56:13PM +0100, Cédric Le Goater wrote:
> On 3/22/23 13:28, Yang Zhong wrote:
> > On Tue, Mar 21, 2023 at 06:30:14PM +0100, Cédric Le Goater wrote:
> > > On 3/20/23 10:31, Yang Zhong wrote:
> > > > Hello Alex and Paolo,
> > > &g
On Tue, Mar 21, 2023 at 09:44:18PM +0100, Paolo Bonzini wrote:
> Il mar 21 mar 2023, 18:30 Cédric Le Goater ha scritto:
>
> > I would have thought that user_creatable_cleanup would have taken care
> > of it. But it's not. This needs some digging.
> >
>
> user_creatable_cleanup is only for
On Tue, Mar 21, 2023 at 06:30:14PM +0100, Cédric Le Goater wrote:
> On 3/20/23 10:31, Yang Zhong wrote:
> > Hello Alex and Paolo,
> >
> > There is one instance_finalize callback definition in hw/vfio/pci.c, but
> > i find this callback(vfio_instance_finalize()) never
Hello Alex and Paolo,
There is one instance_finalize callback definition in hw/vfio/pci.c, but
i find this callback(vfio_instance_finalize()) never be called during the
VM shutdown with close VM or "init 0" command in guest.
The Qemu related command:
..
-device vfio-pci,host=d9:00.0
i/misc-target.json | 12 ++--
> 4 files changed, 21 insertions(+), 32 deletions(-)
>
Tested-by: Yang Zhong
By the way, there is another sgx bug, please help review, thanks!
https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg04825.html
Yang
>
>
In fact, one month ago, I have sent out V2 for this issue. thanks!
https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg04825.html
Yang
On Wed, Dec 07, 2022 at 09:47:47PM -0500, Xiaocheng Dong wrote:
> The previous patch changes the name from FEAT_XSAVE_COMP_{LO|HI}
> to
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by:
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by:
On Wed, Oct 12, 2022 at 09:59:04AM +, Huang, Kai wrote:
> On Wed, 2022-10-12 at 04:26 -0400, Yang Zhong wrote:
> > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):ECX,
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):ECX, which made SGX
enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by:
On Mon, Sep 26, 2022 at 09:51:13AM +0100, Dr. David Alan Gilbert wrote:
> * Yang Zhong (yang.zh...@linux.intel.com) wrote:
> > On Sat, Sep 24, 2022 at 12:01:16AM +0800, Xiaoyao Li wrote:
> > > On 9/23/2022 9:30 PM, Yang Zhong wrote:
> > > > On Wed, Sep 21, 2022 at 03
On Sat, Sep 24, 2022 at 12:01:16AM +0800, Xiaoyao Li wrote:
> On 9/23/2022 9:30 PM, Yang Zhong wrote:
> > On Wed, Sep 21, 2022 at 03:51:42PM +0100, Dr. David Alan Gilbert wrote:
> > > * Wang, Lei (lei4.w...@intel.com) wrote:
> > > > The new CPU model mostly inherit
On Wed, Sep 21, 2022 at 03:51:42PM +0100, Dr. David Alan Gilbert wrote:
> * Wang, Lei (lei4.w...@intel.com) wrote:
> > The new CPU model mostly inherits features from Icelake-Server, while
> > adding new features:
> > - AMX (Advance Matrix eXtensions)
> > - Bus Lock Debug Exception
> > and new
Signed-off-by: Yang Zhong
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index bb6a5dd498..9fdfec9d8b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5559,7 +5559,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint
On Thu, Apr 28, 2022 at 02:56:50PM +0200, Jinpu Wang wrote:
> On Thu, Apr 28, 2022 at 2:32 PM Yang Zhong wrote:
> >
> > On Thu, Apr 28, 2022 at 02:18:54PM +0200, Jinpu Wang wrote:
> > > On Thu, Apr 28, 2022 at 2:05 PM Yang Zhong wrote:
> > > >
> > &g
On Thu, Apr 28, 2022 at 02:18:54PM +0200, Jinpu Wang wrote:
> On Thu, Apr 28, 2022 at 2:05 PM Yang Zhong wrote:
> >
> > On Thu, Apr 28, 2022 at 01:59:33PM +0200, Jinpu Wang wrote:
> > > Hi Yang, hi Paolo,
> > >
> > > We noticed sgx-epc machine type
On Thu, Apr 28, 2022 at 01:59:33PM +0200, Jinpu Wang wrote:
> Hi Yang, hi Paolo,
>
> We noticed sgx-epc machine type is not listed in the output of
> "qemu-system-x86_64 -M ?",
> This is what I got with qemu-7.0
> Supported machines are:
> microvm microvm (i386)
> pc
On Thu, Mar 24, 2022 at 08:35:10AM +0100, Paolo Bonzini wrote:
> On 3/24/22 04:18, Yang Zhong wrote:
> >The kvm_arch_get_supported_cpuid() only call KVM_GET_SUPPORTED_CPUID one
> >time, so the cpuid buffer information still keep older value. Once Qemu
> >enable new dynamic xfe
in kvm_init_xsave() if XTILEDATA
has been enabled by arch_prctl.
assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
env->xsave_buf_len);
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 3 +++
target/i386/kvm/kvm.c | 15 +--
2 files changed, 16 insertions
aveArea array to match the host, ignore features that
> KVM does not report as supported. This will cause QEMU to skip the incorrect
> CPUID leaf instead of tripping the assertion.
>
> Reported-by: Daniel P. Berrangé
> Analyzed-by: Yang Zhong
> Signed-off-by: Paolo Bonzini
On Wed, Mar 16, 2022 at 04:57:39PM +0100, Peter Krempa wrote:
> On Tue, Mar 08, 2022 at 12:34:38 +0100, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Kernel allocates 4K xstate buffer by default. For XSAVE features
> > which require large state compone
On Fri, Mar 18, 2022 at 11:13:56AM +0100, Michal Prívozník wrote:
> On 3/16/22 16:57, Peter Krempa wrote:
> > On Tue, Mar 08, 2022 at 12:34:38 +0100, Paolo Bonzini wrote:
> >> From: Yang Zhong
> >>
> >> Kernel allocates 4K xstate buffer by default. For XSA
to read this new KVM_GET_DEVICE_ATTR ioctl.
Signed-off-by: Yang Zhong
---
target/i386/kvm/kvm.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index ef2c68a6f4..cda95e7ba6 100644
--- a/target/i386/kvm/kvm.c
+++ b/target
On Wed, Mar 16, 2022 at 04:57:39PM +0100, Peter Krempa wrote:
> On Tue, Mar 08, 2022 at 12:34:38 +0100, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Kernel allocates 4K xstate buffer by default. For XSAVE features
> > which require large state compone
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
Reviewed-by: David Edmondson
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions
This patch will be dropped once Qemu sync linux 5.17 header.
Making all linux-headers changes here are only for maintainers
to easily remove those changes once those patches are queued.
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 3 +++
linux-headers/linux/kvm.h | 1 +
2 files
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by: Yang
-by: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 4
target/i386/kvm/kvm.c | 42 --
target/i386/xsave_helper.c | 33 ++
3 files changed, 64 insertions
of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
Reviewed-by: David Edmondson
---
target/i386/cpu.h | 18 +-
target/i386/cpu.c | 8
2 files changed, 25 insertions(+), 1 deletion(-)
diff
use no supported component
needed the bit to be set, but the upcoming AMX feature will
use it. Fix the subleaves value according to KVM's supported
cpuid.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
Reviewed-by: David Edmondson
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c
(5):
x86: Fix the 64-byte boundary enumeration for extended state
x86: Add AMX XTILECFG and XTILEDATA components
x86: Add XFD faulting bit for state components
x86: Add AMX CPUIDs enumeration
x86: Add support for KVM_CAP_XSAVE2 and AMX state migration
Yang Zhong (2):
x86: Grant AMX permissio
to
get host side supported_xcr0 and Qemu can decide if it can request
dynamically enabled XSAVE features permission.
https://lore.kernel.org/all/20220126152210.3044876-1-pbonz...@redhat.com/
Suggested-by: Paolo Bonzini
Signed-off-by: Yang Zhong
Signed-off-by: Jing Liu
---
target/i386/cpu.h
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
On Thu, Feb 17, 2022 at 02:44:10PM +0100, Paolo Bonzini wrote:
> On 2/17/22 06:58, Yang Zhong wrote:
> >>+
> >>+if ((mask & XSTATE_XTILE_DATA_MASK) == XSTATE_XTILE_DATA_MASK) {
> >>+bitmask = kvm_arch_get_supported_cpuid(s, 0xd, 0,
On Mon, Feb 21, 2022 at 01:25:53PM +, David Edmondson wrote:
> On Wednesday, 2022-02-16 at 22:04:32 -08, Yang Zhong wrote:
>
> > From: Jing Liu
> >
> > When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave
> > area would be larger than 4KB. KV
On Mon, Feb 21, 2022 at 01:00:41PM +, David Edmondson wrote:
> On Wednesday, 2022-02-16 at 22:04:30 -08, Yang Zhong wrote:
>
> > From: Jing Liu
> >
> > Intel introduces XFD faulting mechanism for extended
> > XSAVE features to dynamically enable the features in
On Wed, Feb 16, 2022 at 10:04:29PM -0800, Yang Zhong wrote:
> Kernel allocates 4K xstate buffer by default. For XSAVE features
> which require large state component (e.g. AMX), Linux kernel
> dynamically expands the xstate buffer only after the process has
> acquired the necessary
This patch will be dropped once Qemu sync linux 5.17 header.
Making all linux-headers changes here are only for maintainers
to easily remove those changes once those patches are queued.
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 17 +
linux-headers/linux/kvm.h
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions(+)
diff --git a/target/i386
-by: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 4
target/i386/kvm/kvm.c | 42 --
target/i386/xsave_helper.c | 33 ++
3 files changed, 64 insertions
of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 18 +-
target/i386/cpu.c | 8
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by: Yang
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
use no supported component
needed the bit to be set, but the upcoming AMX feature will
use it. Fix the subleaves value according to KVM's supported
cpuid.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c | 1 +
target/i386/kvm/kvm-cpu.c
kvm_arch_init_vcpu() to
make the request permission before KVM_CAP_XSAVE2 extension check(Paolo).
- Removed RFC prefix.
Jing Liu (5):
x86: Fix the 64-byte boundary enumeration for extended state
x86: Add AMX XTILECFG and XTILEDATA components
x86: Add XFD faulting bit for state compo
to
get host side supported_xcr0 and Qemu can decide if it can request
dynamically enabled XSAVE features permission.
https://lore.kernel.org/all/20220126152210.3044876-1-pbonz...@redhat.com/
Suggested-by: Paolo Bonzini
Signed-off-by: Yang Zhong
Signed-off-by: Jing Liu
---
target/i386/cpu.h
where the 'nn' varies depending on what devices were already created.
> >
> > With this change the SGX-EPC objects are now at
> >
> > /machine/sgx-epc[nn]
> >
> > where the 'nn' of the first SGX-EPC object is always zero.
>
> yet again, why it'
tual device from /machine/unattached/device[nn]
to /machine/sgx-epc[nn], which seems more clear. Thanks!
Yang
>
> >
> > Reported-by: Yang Zhong
> > Suggested-by: Paolo Bonzini
> > Reviewed-by: Daniel P. Berrangé
> > Signed-off-by: Philippe Mathieu-Daudé
On Mon, Jan 24, 2022 at 11:15:25AM +0100, Paolo Bonzini wrote:
> On 1/24/22 08:55, Yang Zhong wrote:
> >
> >+if (buflen > sizeof(struct kvm_xsave)) {
> >+e = _ext_save_areas[XSTATE_XTILE_DATA_BIT];
> >+
> >+if (e->size && e-
On Mon, Jan 24, 2022 at 11:13:07AM +0100, Paolo Bonzini wrote:
> On 1/24/22 08:55, Yang Zhong wrote:
> >diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> >index caf1388d8b..25d26a15f8 100644
> >--- a/target/i386/kvm/kvm.c
> >+++ b/target/i386/kvm/kvm.c
&
On Mon, Jan 24, 2022 at 11:16:36AM +0100, Paolo Bonzini wrote:
> On 1/24/22 08:55, Yang Zhong wrote:
> >Kernel allocates 4K xstate buffer by default. For XSAVE features
> >which require large state component (e.g. AMX), Linux kernel
> >dynamically expands the xstate buffer o
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions(+)
diff --git a/target/i386
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by: Yang
-by: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 14 +
linux-headers/linux/kvm.h | 2 ++
target/i386/cpu.h | 4
target/i386/kvm/kvm.c | 42 -
target/i386
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 18 +-
target/i386/cpu.c | 8
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target
use no supported component
needed the bit to be set, but the upcoming AMX feature will
use it. Fix the subleaves value according to KVM's supported
cpuid.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c | 1 +
target/i386/kvm/kvm-cpu.c
xfeatures).
There are separate permissions for native tasks and guests.
Qemu should request the guest permissions for dynamic xfeatures
which will be exposed to the guest. This only needs to be done
once before the first vcpu is created.
Suggested-by: Paolo Bonzini
Signed-off-by: Yang Zhong
Signed
dd support for KVM_CAP_XSAVE2 and AMX state migration
Yang Zhong (1):
x86: Grant AMX permission for guest
Zeng Guang (1):
x86: Support XFD and AMX xsave data migration
linux-headers/asm-x86/kvm.h | 14 ++
linux-headers/linux/kvm.h | 2 +
target/i386/cpu.h | 46 +
On Mon, Jan 17, 2022 at 12:48:10PM +0100, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
> >We have one SGX-EPC address/size/node per memory backend,
> >make it child of the backend in the QOM composition tree.
> >
> >Cc: Yang Zhong
> &g
On Tue, Jan 18, 2022 at 02:06:55PM +0100, Paolo Bonzini wrote:
> Sorry, hit send on the wrong window. This is the only patch that
> will require a bit more work.
>
> On 1/18/22 13:52, Paolo Bonzini wrote:
> >>@@ -124,6 +150,8 @@ void x86_cpus_init(X86MachineState *x86ms,
> >>int
On Tue, Jan 18, 2022 at 01:52:51PM +0100, Paolo Bonzini wrote:
> On 1/7/22 10:31, Yang Zhong wrote:
> >-uint32_t need_align;
> >+uint32_t need_align, support_xfd;
>
> These can be replaced by a single field "uint32_t ecx".
>
> You
On Tue, Jan 18, 2022 at 01:39:59PM +0100, Paolo Bonzini wrote:
> On 1/10/22 09:23, Tian, Kevin wrote:
> >>
> >>AMX XTILECFG and XTILEDATA are managed by XSAVE feature
> >>set. State component 17 is used for 64-byte TILECFG register
> >>(XTILECFG state) and component 18 is used for 8192 bytes
>
On Tue, Jan 18, 2022 at 01:37:20PM +0100, Paolo Bonzini wrote:
> On 1/11/22 03:22, Yang Zhong wrote:
> > Thanks Kevin, I will update this in next version.
>
> Also:
>
> The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
> indicate whether the exten
-size", which can avoid incompatible
API breakage. The "@section-size" will be deprecated in 7.2 version.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Yang Zhong
Reviewed-by: Daniel P. Berrangé
---
docs/about/deprecated.rst | 13 +
qapi/machine.json
On Thu, Jan 20, 2022 at 09:44:34AM +, Daniel P. Berrangé wrote:
> On Thu, Jan 20, 2022 at 05:16:01PM +0800, Yang Zhong wrote:
> > On Thu, Jan 20, 2022 at 09:10:34AM +, Daniel P. Berrangé wrote:
> > > On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
> >
On Thu, Jan 20, 2022 at 09:10:34AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
> > The SGX NUMA patches were merged into Qemu 7.0 release, we need
> > clarify detailed version history information and also change
> > some re
-size", which can avoid incompatible
API breakage. The "@section-size" will be deprecated in 7.2 version.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Yang Zhong
Reviewed-by: Daniel P. Berrangé
---
qapi/machine.json | 4 ++--
qapi/misc-target.json | 17
On Wed, Jan 19, 2022 at 09:16:46AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 19, 2022 at 07:00:14AM -0500, Yang Zhong wrote:
> > The SGX NUMA patches were merged into Qemu 7.0 release, we need
> > clarify detailed version history information and also change
> > some re
The SGX NUMA patches were merged into Qemu 7.0 release, we need
clarify detailed version history information and also change
some related comments, which make SGX related comments clearer.
Signed-off-by: Yang Zhong
---
qapi/machine.json | 4 ++--
qapi/misc-target.json | 14
On Mon, Jan 17, 2022 at 12:48:10PM +0100, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
> >We have one SGX-EPC address/size/node per memory backend,
> >make it child of the backend in the QOM composition tree.
> >
> >Cc: Yang Zhong
> &g
On Mon, Jan 17, 2022 at 01:48:46PM +, Daniel P. Berrangé wrote:
> On Mon, Jan 17, 2022 at 12:53:30AM +0100, Philippe Mathieu-Daudé via wrote:
> > Avoid having CPUs objects dangling as unattached QOM ones,
> > directly attach them to the machine.
>
> Lets be more explicit here
>
> [quote]
>
On Thu, Jan 13, 2022 at 04:15:10PM +, Daniel P. Berrangé wrote:
> On Wed, Dec 15, 2021 at 09:25:13PM +0100, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Add the SGXEPCSection list into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not
On Mon, Jan 17, 2022 at 04:53:45AM +0200, Jarkko Sakkinen wrote:
> On Tue, Nov 30, 2021 at 08:15:36PM +0800, Yang Zhong wrote:
> > On Thu, Nov 25, 2021 at 08:47:22PM +0800, Yang Zhong wrote:
> > > Hello Paolo,
> > >
> > > Our customer used the Libvi
Hi Daniel,
On Wed, Jan 12, 2022 at 10:11:35AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 12, 2022 at 11:55:17AM -0500, Yang Zhong wrote:
> > When Libvirt start, it get the vcpu's unavailable-features from
> > /machine/unattached/device[0] path by qom-get command, but in SGX
&
] is occupied by sgx-epc device, which
fail to get the unvailable-features from /machine/unattached/device[0].
This patch make one new /machine/sgx object to avoid this issue.
(qemu) qom-list /machine/unattached/
device[0] (child)
(qemu) qom-list /machine/sgx
device[0] (child)
Signed-off-by: Yang
here are separate permissions for native tasks and guests.
>
> Qemu should request the guest permissions for dynamic xfeatures
> which will be exposed to the guest. This only needs to be done
> once before the first vcpu is created."
This is clearer. Will update this in new vers
features in
> > runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
> > as 1, it indicates support for XFD faulting of this
> > state component.
> >
> > Signed-off-by: Jing Liu
> > Signed-off-by: Yang Zhong
> > ---
> > target/i386/cpu.h
On Mon, Jan 10, 2022 at 04:20:41PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang
> > Sent: Friday, January 7, 2022 5:31 PM
> >
> > From: Jing Liu
> >
> > The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
> > are all zero, while spec actually introduces that bit 01
> > should indicate
; up AMX components. Add structs that define the layout of
> > AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
> > structs sizes.
> >
> > Signed-off-by: Jing Liu
> > Signed-off-by: Yang Zhong
> > ---
> > target/i386/cpu.h | 16 ++
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions(+)
diff --git a/target/i386
From: Jing Liu
Extended feature has large state while current
kvm_xsave only allows 4KB. Use new XSAVE ioctls
if the xstate size is large than kvm_xsave.
Signed-off-by: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 14
. Add structs that define the layout of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 16 +++-
target/i386/cpu.c | 8
2 files changed, 23 insertions(+), 1 deletion(-)
diff
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
for guest only once
before the first vCPU is created. KVM checks the guest
permission when Qemu advertises the features, and the
advertising operation fails w/o permission.
Signed-off-by: Yang Zhong
Signed-off-by: Jing Liu
---
target/i386/cpu.h | 7 +++
hw/i386/x86.c | 28
ml
Thanks,
Yang
Jing Liu (5):
x86: Fix the 64-byte boundary enumeration for extended state
x86: Add AMX XTILECFG and XTILEDATA components
x86: Add XFD faulting bit for state components
x86: Add AMX CPUIDs enumeration
x86: Use new XSAVE ioctls handling
Yang Zhong (1):
x86:
AVE area is
used.
Fix the subleaves value according to the host supported
cpuid. The upcoming AMX feature would be the first one
using it.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 1 +
target/i386/cpu.c | 1 +
target/i386/kvm/kvm-cpu.c | 3 +++
3 fi
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by: Yang
On Thu, Nov 25, 2021 at 08:47:22PM +0800, Yang Zhong wrote:
> Hello Paolo,
>
> Our customer used the Libvirt XML to start a SGX VM, but failed.
>
> libvirt.libvirtError: internal error: unable to execute QEMU command
> 'qom-get': Property 'sgx-epc.unavailable-features' not
Hello Paolo,
Our customer used the Libvirt XML to start a SGX VM, but failed.
libvirt.libvirtError: internal error: unable to execute QEMU command 'qom-get':
Property 'sgx-epc.unavailable-features' not found
The XML file,
The new compound property command
On Thu, Nov 11, 2021 at 08:55:35AM +0100, Philippe Mathieu-Daudé wrote:
> On 11/11/21 07:18, Yang Zhong wrote:
> > On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote:
> >> On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote:
> >>> Add the SGXEPCSec
On Wed, Nov 10, 2021 at 05:07:40PM +0100, Paolo Bonzini wrote:
> On 11/10/21 13:56, Yang Zhong wrote:
> > Paolo, thanks!
> >
> > No other maintainers to review numa patches, so i will send the numa
> > patches again? thanks!
>
> The patch look good, but th
On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote:
> On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote:
> > Add the SGXEPCSection list into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not the total size like before.
> > This patch ca
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